JP3678401B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).
[0002]
[Prior art]
An AC (alternating discharge) type PDP is known as one of such matrix display type PDPs.
The AC-type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs that are arranged orthogonally to the column electrodes and form one scan line as a pair. Each of these row electrode pairs and column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .
[0003]
At this time, since the PDP uses a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, the subfield method is used to realize halftone luminance display using such PDP. In the subfield method, a display period of one field is divided into N subfields, and a light emission period having a period length corresponding to the weighting of each bit digit of pixel data (N bits) is assigned to each subfield. The light emission is driven.
[0004]
For example, as shown in FIG. 1, when one field period is divided into six subfields SF1 to SF6,
SF1: 1
SF2: 2
SF3: 4
SF4: 8
SF5: 16
SF6: 32
The light emission drive is performed at the light emission period ratio.
[0005]
Here, when the discharge cell emits light with a luminance of “32”, as shown in FIG. 1, the light emission is performed only with SF6 among the subfields SF1 to SF6. Further, when light is emitted with luminance "31", light emission is performed in the subfields SF1 to SF5 other than the subfield SF6. This makes it possible to express halftone luminance in 64 levels.
[0006]
As apparent from the sequence of FIG. 1, the number of subfields may be increased in order to increase the number of gradations.
However, since a pixel data writing process for selecting a light emitting cell is required in one subfield, the number of pixel data writing processes to be performed in one field increases as the number of subfields increases. As a result, the time allotted to the light emission period (the length of the light emission maintenance process) within one field period becomes relatively short, leading to a decrease in luminance.
[0007]
Therefore, in order to realize video display by PDP, it is necessary to perform some multi-gradation processing on the video signal itself. For example, error diffusion processing is known as a multi-gradation technique. The error diffusion process is a method of artificially increasing the number of gradations by adding an error between pixel data corresponding to a certain pixel (discharge cell) and a predetermined threshold value to pixel data corresponding to surrounding pixels.
[0008]
However, when the original number of gradations is small, the error diffusion pattern becomes conspicuous and there is a problem that the S / N deteriorates.
[0009]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a plasma display panel driving method capable of improving the gradation expression power while improving the display quality.
[0010]
[Means for Solving the Problems]
Claim 1The plasma display panel driving method according to the method forms discharge cells corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. The unit display period is divided into N divided display periods, and N is obtained by performing multi-gradation processing on an input video signal in each of the divided display periods. A pixel data writing process in which each of the discharge cells is set to one of a non-light emitting cell or a light emitting cell in accordance with bit display driving pixel data, and the number of times of light emission corresponding to the weighting of each of the divided display periods. A light emission driving sequence for executing only the light emission sustaining step, wherein the light emission driving sequence includes the light emission driving sequence in the sustain light emission step in each of the N divided display periods. A first driving pattern in which each of the first and second light emission driving sequences having different frequency ratios are alternately switched for each unit display period and executed in the sustain light emission process in each of the N divided display periods. A second drive pattern that executes each of the third and fourth light emission drive sequences having a different ratio of the number of times of light emission alternately for each unit display period;Of the number of times of light emission assigned to each of the N divided display periods in the first light emission drive sequence, k times (k: an integer not less than N and less than N) and (k + 1) th number of light emission times. T1 (k) and T1 (k + 1), respectively, and the light emission that is the kth and (k + 1) th smallest among the number of times of light emission assigned to each of the N divided display periods in the second light emission drive sequence. When the number of times is T2 (k) and T2 (k + 1), respectively,
        T1 (k) <T2 (k) <T1 (k + 1) <T2 (k + 1)
  Has a large and small relationship
  Of the number of times of light emission assigned to each of the N divided display periods in the third light emission drive sequence, the number of times of light emission that is the kth and (k + 1) th smallest is set to T3 (k) and T3 (k + 1), respectively. The number of times of light emission that is the kth and (k + 1) th smallest among the number of times of light emission assigned to each of the N divided display periods in the fourth light emission drive sequence is T4 (k) and T4 ( k + 1),
        T3 (k) <T4 (k) <T3 (k + 1) <T4 (k + 1)
  Has a large and small relationship
  The first drive pattern and the second drive pattern are alternatively executed according to the type of the input video signal.
  According to a fifth aspect of the present invention, there is provided a plasma display panel driving method in which one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to intersect the row electrodes. A driving method of a plasma display panel in which a corresponding discharge cell is formed, wherein a unit display period is divided into N divided display periods, and multi-gradation processing is performed on an input video signal in each of the divided display periods. A pixel data writing step for setting each of the discharge cells to one of a non-light-emitting cell or a light-emitting cell in accordance with N-bit display driving pixel data obtained by performing the above, and only the light-emitting cell for each of the divided display periods. A light emission sustaining sequence for emitting light for the number of times corresponding to the weighting, wherein the light emission driving sequence includes the sustain emission for each of the N divided display periods. The first and second light emission drive sequences are different from each other in the ratio of the number of times of light emission in the process, and the first light emission drive sequence and the second light emission drive sequence are alternately executed, and the first light emission drive sequence is executed. The luminance level of each gradation luminance point obtained is made to coincide with the luminance level at each gradation luminance point obtained by the multi-gradation processing when the second light emission drive sequence is executed.
  According to another aspect of the present invention, there is provided a plasma display panel driving method in which one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to intersect the row electrodes. A driving method of a plasma display panel in which a corresponding discharge cell is formed, wherein a unit display period is divided into N divided display periods, and multi-gradation processing is performed on an input video signal in each of the divided display periods. A pixel data writing step for setting each of the discharge cells to one of a non-light-emitting cell or a light-emitting cell in accordance with N-bit display driving pixel data obtained by performing the above, and only the light-emitting cell for each of the divided display periods. Light emission maintenance line that emits light for the number of times corresponding to weighting The first and second light emission drive sequences have different ratios of the number of times of light emission in the sustain light emission process in each of the N divided display periods. And alternately executing the first light emission drive sequence and the second light emission drive sequence, The luminance level at each gradation luminance point obtained by executing the first light emission driving sequence is different from the luminance level at each gradation luminance point obtained by the multi-gradation processing when the second light emission driving sequence is executed. Make it.
  The plasma display panel driving method according to claim 24 is characterized in that one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A driving method of a plasma display panel in which a corresponding discharge cell is formed, wherein a unit display period is divided into N divided display periods, and multi-gradation processing is performed on an input video signal in each of the divided display periods. A pixel data writing step for setting each of the discharge cells to one of a non-light-emitting cell or a light-emitting cell in accordance with N-bit display driving pixel data obtained by performing the above, and only the light-emitting cell for each of the divided display periods. A light emission driving sequence for executing a light emission sustaining step of emitting light for the number of times of light emission corresponding to the weighting, and the light emission driving sequence includes the maintenance of each of the N divided display periods. A first drive pattern for executing each of the first and second light emission drive sequences having different ratios of the number of times of light emission in the light stroke alternately for each unit display period, and each of the N divided display periods. The first light emission drive sequence includes a second drive pattern in which the third and fourth light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process are alternately switched for each unit display period. The luminance levels of the kth gradation (k: an integer greater than or equal to N and less than N) and the (k + 1) th gradation obtained by executing are set to Y1 (k) and Y1 (k + 1), respectively, and the second light emission drive sequence is executed. When the luminance levels of the k-th gradation and the (k + 1) -th gradation obtained by the above are Y2 (k) and Y2 (k + 1), respectively,
        Y1 (k) <Y2 (k) <Y1 (k + 1) <Y2 (k + 1)
  Has a large and small relationship
  The luminance levels of the kth gradation and the (k + 1) th gradation obtained by executing the third light emission driving sequence are Y3 (k) and Y3 (k + 1), respectively, and the fourth light emission driving sequence obtained by executing the fourth light emission driving sequence. When the luminance levels of the k gradation and the (k + 1) th gradation are Y4 (k) and Y4 (k + 1), respectively.
        Y3 (k) <Y4 (k) <Y1 (k + 1) <Y2 (k + 1)
  Has a large and small relationship
  The first drive pattern and the second drive pattern are alternatively executed according to the type of the input video signal..
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 is a diagram showing a schematic configuration of a plasma display device that drives a plasma display panel to emit light based on the driving method according to the present invention.
The plasma display device includes an operation device 1, a drive control circuit 2, an input selector 3, an A / D converter 4, a data conversion circuit 30, a memory 5, an address driver 6, a first sustain driver 7 and a second sustain driver 8. And a PDP 10 as a plasma display panel.
[0012]
This plasma display device is compatible with a PC video signal which is a video signal from a personal computer in addition to a television signal such as the NTSC system. A dedicated input terminal (not shown) is individually provided.
In FIG. 2, the controller device 1 includes an input video designation signal S corresponding to a video signal designated by the user._VIs supplied to each of the drive control circuit 2, the input selector 3, and the data conversion circuit 30. For example, when the user designates the PC video signal as a video signal to be displayed, the controller device 1 designates a logical level “0” and a color television signal (hereinafter referred to as a TV signal). In this case, the input video designation signal S having a logic level “1” is used._VIs generated.
[0013]
The input selector 3 receives the input video designation signal S from the PC video signal and the TV signal supplied via the input terminal._VIs selected as an input video signal and supplied to the A / D converter 4 as an input video signal. Note that each of the PC video signal and the TV signal has been subjected to gamma correction processing in advance.
The A / D converter 4 samples the input video signal supplied from the input selector 3 in accordance with the clock signal supplied from the drive control circuit 2, and converts it into, for example, 8-bit pixel data D for each pixel. Convert. That is, the A / D converter 4 converts the analog input video signal supplied from the input selector 3 into 8-bit pixel data that can express the luminance in 256 gradations.
[0014]
The data conversion circuit 30 displays the data obtained by subjecting the 8-bit pixel data D to brightness adjustment and multi-gradation processing, and display drive pixel data for actually driving each pixel of the PDP 10 to emit light. Converted to GD and supplied to the memory 5.
FIG. 3 is a diagram showing an internal configuration of the data conversion circuit 30. As shown in FIG.
As shown in FIG. 3, the data conversion circuit 30 includes an ABL (automatic brightness control) circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second data conversion circuit 34.
[0015]
The ABL circuit 31 applies the pixel data D for each pixel sequentially supplied from the A / D converter 4 so that the average luminance of the image displayed on the screen of the PDP 10 is within an appropriate luminance range. The brightness level is adjusted, and the brightness adjustment pixel data D obtained at this time is adjusted._BLIs supplied to the first data conversion circuit 32.
FIG. 4 is a diagram showing an internal configuration of the ABL circuit 31. As shown in FIG.
[0016]
In FIG. 4, a level adjustment circuit 310 adjusts the brightness adjustment pixel data D obtained by adjusting the level of the pixel data D according to the average brightness obtained by the average brightness detection circuit 311 described later._BLIs output. The data conversion circuit 312 receives the brightness adjustment pixel data D_BLAs shown in FIG. 5, the inverse gamma characteristic (Y = X^2.2) Is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, luminance adjustment pixel data D_BLBy applying inverse gamma correction processing to the pixel data, the pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal for which the gamma correction has been canceled is restored. The average luminance detection circuit 311 first obtains the average luminance of the inverse gamma conversion pixel data Dr. Here, the average luminance detection circuit 311 determines whether the average luminance corresponds to one of the luminance modes 1 to 4 in which the range from the highest luminance to the lowest luminance is classified into four stages, and this corresponding luminance mode. Is supplied to the drive control circuit 2, and the average brightness obtained as described above is supplied to the level adjustment circuit 310. That is, the level adjustment circuit 310 adjusts the level of the pixel data D in accordance with the average luminance and uses the luminance adjustment pixel data D._BLIs supplied to the data conversion circuit 312 and the first data conversion circuit 32 in the next stage.
[0017]
FIG. 6 is a diagram showing an internal configuration of the first data conversion circuit 32.
In FIG. 6, the data conversion circuit 321 includes the brightness adjustment pixel data D._BL7A, 8-bit converted pixel data A from "0" to "192" based on the conversion characteristics as shown in FIG.₁And this is supplied to the selector 322. The data conversion circuit 323 receives the luminance adjustment pixel data D_BL7B, 8-bit converted pixel data B from “0” to “192” based on the conversion characteristics as shown in FIG.₁And this is supplied to the selector 322. The selector 322 selects the converted pixel data A₁And B₁Of these, the one corresponding to the logic level of the conversion characteristic selection signal is alternatively selected and supplied to the selector 324. The conversion characteristic selection signal is supplied from the drive control circuit 2 and changes from the logic level “1” to “0” or “0” to “1” according to the vertical synchronization timing of the input video signal. It is a signal that changes. The data conversion circuit 325 receives the brightness adjustment pixel data D_BLAs shown in FIG. 8A, 9-bit converted pixel data A from “0” to “384” based on the conversion characteristics as shown in FIG.₂And this is supplied to the selector 326. The data conversion circuit 327 outputs the brightness adjustment pixel data D_BL8B, 9-bit conversion pixel data B from “0” to “384” based on the conversion characteristics as shown in FIG.₂And this is supplied to the selector 326. The selector 326 outputs the converted pixel data A₂And B₂Of these, the one corresponding to the logic level of the conversion characteristic selection signal is alternatively selected and supplied to the selector 324. The selector 324 is the conversion pixel data A supplied from the selector 322.₁(Or B₁), And converted pixel data A supplied from the selector 326₂(Or B₂), The input video designation signal S_VIs selected in accordance with the logic level of the first conversion pixel data D._HTo the multi-gradation processing circuit 33 in the next stage.
[0018]
With the configuration shown in FIG. 6, the first data conversion circuit 32 becomes “0” to “255” based on the conversion characteristics shown in FIG. 7 when the input of the TV signal is designated in the controller device 1. 8-bit brightness adjustment pixel data D_BL8 bits of first conversion pixel data D from “0” to “192”_HAnd converted to the multi-gradation processing circuit 33. On the other hand, when a PC video signal is designated as input, 8-bit luminance adjustment pixel data D from “0” to “255” based on the conversion characteristics shown in FIG._BL9-bit first conversion pixel data D from “0” to “384”_HThen, the converted signal is supplied to the multi-gradation processing circuit 33. 7A and 8A show conversion characteristics used when displaying odd fields (odd frames), and FIGS. 7B and 8B show conversion characteristics used when displaying even fields (even frames). . That is, when a TV signal is designated as input, the first data conversion circuit 32 switches the conversion characteristics used at the time of conversion as shown in FIGS. 7A and 7B for each field (frame). When a PC video signal is designated for input, the conversion characteristics are switched for each field as shown in FIGS. 8A and 8B.
[0019]
As described above, the first data conversion circuit 32 is provided in the previous stage of the multi-gradation processing circuit 33 to be described later, and data conversion is performed according to the number of display gradations and the number of compression bits by multi-gradation. Luminance saturation due to gradation processing and generation of a flat portion of display characteristics (that is, generation of gradation distortion) that occurs when the display gradation is not at the bit boundary are prevented.
FIG. 9 is a diagram showing an internal configuration of the multi-gradation processing circuit 33.
[0020]
As shown in FIG. 9, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.
First, the data separation circuit 331 in the error diffusion processing circuit 330 receives the first or the 8-bit converted pixel data D supplied from the first data conversion circuit 32._HThe upper 6 bits are separated as display data, and the lower 2 or 3 bits are separated as error data. The adder 332 outputs the first converted pixel data D as the error data._HAn addition value obtained by adding the lower 2 or 3 bits of the middle, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 is supplied to the delay circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and delays the addition value AD.₁Are supplied to the coefficient multiplier 335 and the delay circuit 337, respectively. The coefficient multiplier 335 receives the delay addition signal AD.₁The predetermined coefficient value K₁A multiplication result obtained by multiplying (for example, “7/16”) is supplied to the adder 332. The delay circuit 337 receives the delay addition signal AD.₁Is further delayed by a time of (1 horizontal scanning period−the delay time D × 4).₂To the delay circuit 338. The delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D to obtain a delayed addition signal AD_ThreeAs a coefficient multiplier 339. In addition, the delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D × 2 to obtain a delayed addition signal AD_FourIs supplied to the coefficient multiplier 340. Further, the delay circuit 338 receives the delayed addition signal AD.₂Is obtained by delaying the delay time D × 3 by the delay time signal D × 3._FiveIs supplied to the coefficient multiplier 341. The coefficient multiplier 339 outputs the delayed addition signal AD_ThreeThe predetermined coefficient value K₂The multiplication result obtained by multiplying (for example, “3/16”) is supplied to the adder 342. The coefficient multiplier 340 receives the delayed addition signal AD._FourThe predetermined coefficient value K_ThreeThe multiplication result obtained by multiplying (for example, “5/16”) is supplied to the adder 342. The coefficient multiplier 341 receives the delayed addition signal AD._FiveThe predetermined coefficient value K_FourThe multiplication result obtained by multiplying (for example, “1/16”) is supplied to the adder 342. The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 outputs the error data (first converted pixel data D_H(The lower 2 or 3 bits), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 are added. At this time, if there is no carry, the logic level is "0" and the carry is In some cases, a carry-out signal C with a logic level "1"_OIs generated and supplied to the adder 333. The adder 333 receives the display data (first converted pixel data D_HIn the upper 6 bits), the above carry-out signal C_OIs added as 6-bit error diffusion processed pixel data ED.
[0021]
The operation of the error diffusion processing circuit 330 having such a configuration will be described below.
For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 10, first, the pixel G (j, k) on the left side of the pixel G (j, k) is first obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Each error data corresponding to each, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD₁
Error data corresponding to pixel G (j-1, k + 1): delayed addition signal AD_Three
Error data corresponding to pixel G (j-1, k): delayed addition signal AD_Four
Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD_Five
For each, a predetermined coefficient value K as described above₁~ K_FourTo perform weighted addition. Next, the first conversion pixel data D is added to the addition result._HThe error data corresponding to the lower 2 or 3 bits, that is, the pixel G (j, k) is added, and the 1-bit carryout signal C obtained at this time is added._OThe first conversion pixel data D_HThe upper 6 bits, that is, the display data corresponding to the pixel G (j, k) is added to the display data corresponding to the pixel G (j, k) as error diffusion processing pixel data ED.
[0022]
That is, the error diffusion processing circuit 330 performs the first conversion pixel data D_HThe upper 6 bits are displayed as display data and the remaining lower bits as error data, and the surrounding pixels {G (j, k-1), G (j-1, k + 1), G (j-1, k ), G (j−1, k−1)}, which is obtained by weighting and adding the error data, is reflected in the display data. By such an operation, the luminance component corresponding to the lower bits in the original pixel {G (j, k)} is pseudo-expressed by the peripheral pixels, and therefore, the number of bits less than 8 bits, that is, display data for 6 bits. Thus, luminance gradation equivalent to the 8-bit pixel data can be expressed.
[0023]
If this error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Therefore, the error diffusion coefficient K to be assigned to each of the four pixels as in the case of the dither coefficient described later.₁~ K_FourMay be changed for each field (frame).
[0024]
The dither processing circuit 350 performs a dither process on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to the 6-bit error diffusion processing pixel data ED. Multi-gradation processing pixel data D with the number of bits further reduced to 4 bits_SIs generated. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.
[0025]
However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.
Therefore, in the dither processing circuit 350, the dither coefficients a to d to be assigned to each of the four pixels are changed for each field.
[0026]
FIG. 11 is a diagram showing an internal configuration of the dither processing circuit 350.
In FIG. 11, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351. The dither coefficient generation circuit 352 is connected to the input video designation signal S._VThe dither coefficients a to d to be generated are varied according to the input designated video signal indicated by.
[0027]
That is, the input video designation signal S_VWhen the video signal designated to be input at is a TV signal, as shown in FIG.
Dither coefficient a: 0
Dither coefficient b: 1
Dither coefficient c: 2
Dither coefficient d: 3
When the dither coefficients a to d each consisting of 2 bits are generated, and the video signal designated as input is a PC video signal, as shown in FIG.
Dither coefficient a: 0 (or 1)
Dither coefficient b: 2 (or 3)
Dither coefficient c: 4 (or 5)
Dither coefficient d: 6 (or 7)
The dither coefficients a to d each consisting of 3 bits are generated.
[0028]
Each of these dither coefficients a to d corresponds to the pixel G (j, k), the pixel G (j, k + 1), the (j + 1) th row corresponding to the jth row, for example, as shown in FIG. The pixel G (j + 1, k) and the pixel G (j + 1, k + 1) that are adjacent to each other are assigned to each of the four pixels. The dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.
[0029]
That is, the dither coefficient generation circuit 352 performs the following operation in the first first field.
Pixel G (j, k): Dither coefficient a
Pixel G (j, k + 1): Dither coefficient b
Pixel G (j + 1, k): Dither coefficient c
Pixel G (j + 1, k + 1): Dither coefficient d
In the next second field,
Pixel G (j, k): Dither coefficient b
Pixel G (j, k + 1): Dither coefficient a
Pixel G (j + 1, k): Dither coefficient d
Pixel G (j + 1, k + 1): Dither coefficient c
In the next third field,
Pixel G (j, k): Dither coefficient d
Pixel G (j, k + 1): Dither coefficient c
Pixel G (j + 1, k): Dither coefficient b
Pixel G (j + 1, k + 1): Dither coefficient a
And in the fourth field,
Pixel G (j, k): Dither coefficient c
Pixel G (j, k + 1): Dither coefficient d
Pixel G (j + 1, k): Dither coefficient a
Pixel G (j + 1, k + 1): Dither coefficient b
The dither coefficients a to d are repeatedly generated by the assignment as described above and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated. The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each of the dither coefficients a to d assigned to each field as described above, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.
[0030]
For example, in the first field shown in FIG.
Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
Error diffusion pixel data ED corresponding to pixel G (j + 1, k + 1) + dither coefficient d
Are sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data. The upper bit extraction circuit 353 extracts up to the upper 4 bits of the dither addition pixel data, and converts this to the multi-gradation pixel data D_SOutput as.
[0031]
As described above, the dither processing circuit 350 shown in FIG. 9 reduces the visual noise due to the dither pattern by changing the dither coefficients a to d to be assigned to the four pixels for each field. Is also visually multi-gradation 4-bit multi-gradation pixel data D_SIs supplied to the second data conversion circuit 34.
[0032]
The second data conversion circuit 34 outputs the 4-bit multi-gradation pixel data D_SIs converted into display drive pixel data GD composed of the first to twelfth bits in accordance with a conversion table as shown in FIG. Each of these first to twelfth bits corresponds to each of subfields SF1 to SF12 described later.
As described above, according to the data conversion circuit 30 including the ABL circuit 31, the first data conversion circuit 32, the multi-gradation processing circuit 33, and the second data conversion circuit 34, a pixel capable of expressing 256 gradations with 8 bits. As shown in FIG. 14, the data D is converted into 12-bit display drive pixel data GD having a total of 13 patterns.
[0033]
The memory 5 in FIG. 2 sequentially writes and stores the display drive pixel data GD in accordance with the write signal supplied from the drive control circuit 2. With this writing operation, display drive pixel data GD for one screen (n rows, m columns) is displayed._11-nmWhen the writing operation is completed, the memory 5 displays the display drive pixel data GD in accordance with the readout signal supplied from the drive control circuit 2._11-nmAre sequentially read for each row by the same bit digits and supplied to the address driver 6. In other words, the memory 5 stores the drive display drive pixel data GD for one screen each having 12 bits._11-nmFor each bit digit,
DB1_11-nm: Display drive pixel data GD_11-nm1st bit of
DB2_11-nm: Display drive pixel data GD_11-nm2nd bit of
DB3_11-nm: Display drive pixel data GD_11-nmThe third bit of
DB4_11-nm: Display drive pixel data GD_11-nm4th bit of
DB5_11-nm: Display drive pixel data GD_11-nm5th bit of
DB6_11-nm: Display drive pixel data GD_11-nm6th bit of
DB7_11-nm: Display drive pixel data GD_11-nm7th bit of
DB8_11-nm: Display drive pixel data GD_11-nm8th bit of
DB9_11-nm: Display drive pixel data GD_11-nm9th bit of
DB10_11-nm: Display drive pixel data GD_11-nm10th bit of
DB11_11-nm: Display drive pixel data GD_11-nm11th bit of
DB12_11-nm: Display drive pixel data GD_11-nm12th bit of
The display drive pixel data bit DB1 divided into 12 as shown in FIG._11-nm~ DB12_11-nmDB1_11-nm, DB2_11-nm... DB12_11-nmEach of them is sequentially read for each row in accordance with the read signal supplied from the drive control circuit 2 and supplied to the address driver 6.
[0034]
The drive control circuit 2 generates a clock signal for the A / D converter 4 and a write / read signal for the memory 5 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates various timing signals for driving and controlling the address driver 6, the first sustain driver 7 and the second sustain driver 8 in synchronization with the horizontal and vertical synchronization signals.
[0035]
In response to the timing signal supplied from the drive control circuit 2, the address driver 6 has m voltages having voltages corresponding to the logical levels of the display drive pixel data bits DB for one row read from the memory 5. Pixel data pulses are generated and are generated by the column electrode D of the PDP 10₁~ D_mRespectively.
The PDP 10 includes the column electrode D as an address electrode.₁~ D_mAnd row electrodes X arranged orthogonal to these column electrodes₁~ X_nAnd row electrode Y₁~ Y_nIt has. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y. That is, the first row electrode pair in the PDP 10 is the row electrode X.₁And Y₁The row electrode pair in the nth row is the row electrode X_nAnd Y_nIt is. The row electrode pair and the column electrode are covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to a pixel is formed at the intersection of each row electrode pair and the column electrode.
[0036]
Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with the timing signal supplied from the drive control circuit 2, and outputs these drive pulses to the row electrode X of the PDP 10.₁~ X_nAnd Y₁~ Y_nApply to. FIG. 15 shows that the address driver 6, the first sustain driver 7 and the second sustain driver 8 are connected to the column electrode D of the PDP 10, respectively.₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nIt is a figure which shows an example of the application timing of the various drive pulses applied to.
[0037]
In the example shown in FIG. 15, the display period of one field is divided into twelve subfields SF1 to SF12, and gradation driving for the PDP 10 is performed. At this time, in each subfield, pixel data writing process Wc for writing pixel data to each discharge cell of PDP 10 to set “light emitting cell” and “non-light emitting cell”, and the above “light emitting cell”. A light emission sustaining process Ic is performed in which only the light emission is maintained for a period (number of times) corresponding to the weighting of each subfield. However, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and the erase process E is executed only in the last subfield SF12.
[0038]
First, in the simultaneous reset process Rc, each of the first sustain driver 7 and the second sustain driver 8 is connected to the row electrode X of the PDP 10.₁~ X_nAnd Y₁~ Y_nFor each, a reset pulse RP as shown in FIG._xAnd RP_YAre simultaneously applied. These reset pulses RP_xAnd RP_YIn response to the application, all the discharge cells in the PDP 10 are reset and discharge, and predetermined wall charges are uniformly formed in each discharge cell. As a result, all the discharge cells are once set to the “light emitting cells”.
[0039]
Next, in the pixel data writing process Wc, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of the display drive pixel data bit DB supplied from the memory 5, and this is generated for one row. Each column electrode D sequentially_1-mApply to. That is, first, in the pixel data writing process Wc of the subfield SF1, the display drive pixel data bit DB1 is used._11-nmThe portion corresponding to the first line from that, that is, DB1_11-1mAnd extract these DB1_11-1mPixel data pulse group DP1 consisting of m pixel data pulses corresponding to each logic level₁To generate a column electrode D_1-mApply to. Next, such display drive pixel data bit DB1._11-nmDB1 corresponding to the second row of_21-2mAnd extract these DB1_21-2mPixel data pulse group DP1 consisting of m pixel data pulses corresponding to each logic level₂To generate a column electrode D_1-mApply to. Hereinafter, similarly, in the pixel data writing process Wc of the subfield SF1, the pixel data pulse group DP1 for each row is processed._Three~ DP1_nSequentially column electrode D_1-mApply to. Subsequently, in the pixel data writing process Wc of the subfield SF2, first, the display drive pixel data bit DB2 is selected._11-nmThe amount corresponding to the first line from the inside, that is, DB2_11-1mAnd extract these DB2_11-1mPixel data pulse group DP2 consisting of m pixel data pulses corresponding to each logic level₁To generate a column electrode D_1-mApply to. Next, such display drive pixel data bit DB2_11-nmDB2 corresponding to the second row of_21-2mAnd extract these DB2_21-2mPixel data pulse group DP2 consisting of m pixel data pulses corresponding to each logic level₂To generate a column electrode D_1-mApply to. Similarly, in the pixel data writing process Wc of the subfield SF2, the pixel data pulse group DP2 for each row is similarly processed._Three~ DP2_nSequentially column electrode D_1-mApply to. Hereinafter, in the pixel data writing process Wc in each of the subfields SF3 to SF12, the address driver 6 similarly displays the display drive pixel data bit DB3._11-nm~ DB12_11-nmPixel data pulse group DP3 generated based on each_1-n~ DP12_1-nEach is assigned to each of the subfields SF3 to SF12, and these are assigned to the column electrode D._1-mIt is applied to. The address driver 6 generates a high-voltage pixel data pulse when the logic level of the display drive pixel data bit DB is “1”, and generates a low voltage (0 volt) when it is “0”. Assume that a pixel data pulse is generated.
[0040]
Further, in the pixel data writing process Wc, the second sustain driver 8 generates a negative scan pulse SP as shown in FIG. 15 at the same timing as each application timing of the pixel data pulse group DP as described above. This is the row electrode Y₁~ Y_nApply sequentially to. At this time, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining in are selectively erased. That is, each of the first to twelfth bits in the display drive pixel data GD determines whether or not to cause selective erasure discharge in the pixel data writing process Wc in each of the subfields SF1 to SF12. Due to the selective erasing discharge, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc is changed to the “non-light emitting cell”. On the other hand, no discharge occurs in the discharge cells formed in the “column” to which the low-voltage pixel data pulse is applied, and the current state is maintained. That is, the discharge cell of “non-light emitting cell” remains “non-light emitting cell”, and the discharge cell of “light emitting cell” maintains the state of “light emitting cell” as it is. As described above, the pixel data writing process Wc for each subfield includes a “light emitting cell” in which a sustain discharge is generated in the light emission sustaining process Ic immediately after that and a “non-light emitting cell” in which no sustain discharge is generated. Is set.
[0041]
Next, in the light emission sustaining process Ic of each subfield, the first sustain driver 7 and the second sustain driver 8 are respectively connected to the row electrode X.₁~ X_nAnd Y₁~ Y_nOn the other hand, as shown in FIG._XAnd IP_YApply.
Here, the number of sustain pulses IP applied in the light emission sustain process Ic is set for each subfield in accordance with the weighting, and the luminance mode supplied from the data conversion circuit 30 shown in FIG. Depending on the type of the signal LC and the video signal selected as the input video signal in the input selector 3.
[0042]
FIG. 16 is a diagram showing the number of sustain pulses IP applied in the light emission sustain process Ic of each of the subfields SF1 to SF12 when the TV signal is selected as the input video signal. Note that FIG. 16A shows the number of sustain pulses IP applied according to the luminance mode signal LC when displaying odd fields (odd frames), and FIG. 16B shows when displaying even fields (even frames). This is shown for each mode.
[0043]
On the other hand, FIG. 17 is a diagram showing the number of sustain pulses IP to be applied in the light emission sustain process Ic of each of the subfields SF1 to SF12 when the PC video signal is selected as the input video signal. Note that FIG. 17A shows the number of sustain pulses IP applied in accordance with the luminance mode signal LC when displaying odd fields (odd frames), and FIG. 17B shows when displaying even fields (even frames). This is shown for each mode.
[0044]
For example, the drive control circuit 2 has an input video designation signal S that designates a TV signal as the input video signal._VWhen the luminance mode signal LC indicating the luminance mode 1 is supplied, various timing signals for performing the operation according to the light emission driving sequence as shown in FIG. This is supplied to the driver 7 and the second sustain driver 8 respectively.
[0045]
FIG. 18A shows a light emission drive sequence executed when odd fields (odd frames) are displayed, and FIG. 18B shows even fields (even frames).
That is, when the input designated video signal is a TV signal and the luminance mode is 1, the ratio of the number of sustain pulses IP applied in the light emission sustain process Ic of each of the subfields SF1 to SF12 is:
When displaying an odd field (odd frame), as shown in FIG.
SF1: 2
SF2: 2
SF3: 6
SF4: 8
SF5: 11
SF6: 17
SF7: 22
SF8: 28
SF9: 35
SF10: 43
SF11: 51
SF12: 30
When an even field (even frame) is displayed, as shown in FIG.
SF1: 1
SF2: 2
SF3: 4
SF4: 6
SF5: 10
SF6: 14
SF7: 19
SF8: 25
SF9: 31
SF10: 39
SF11: 47
SF12: 57
It becomes.
[0046]
On the other hand, an input video designation signal S for designating a PC video signal as an input video signal._VWhen each of the luminance mode signals LC indicating the luminance mode 1 is supplied, the drive control circuit 2 sends various timing signals for performing the operation according to the light emission driving sequence as shown in FIG. , And supplied to the first sustain driver 7 and the second sustain driver 8 respectively.
[0047]
FIG. 19A shows an odd field (odd frame) display, and FIG. 19B shows a light emission drive sequence executed when an even field (even frame) is displayed.
That is, when the input video signal is a PC video signal and the luminance mode is 1, the frequency ratio of the sustain pulse IP applied in the light emission sustain process Ic of each of the subfields SF1 to SF12 is:
When displaying an odd field (odd frame), as shown in FIG.
SF1: 1
SF2: 2
SF3: 4
SF4: 7
SF5: 11
SF6: 14
SF7: 20
SF8: 25
SF9: 33
SF10: 40
SF11: 48
SF12: 50
When an even field (even frame) is displayed, as shown in FIG.
SF1: 1
SF2: 2
SF3: 4
SF4: 6
SF5: 10
SF6: 14
SF7: 19
SF8: 25
SF9: 31
SF10: 39
SF11: 47
SF12: 57
It becomes.
[0048]
At this time, the ratio of the number of sustain pulses IP applied in each of the subfields SF1 to SF12 is nonlinear (that is, the inverse gamma ratio, Y = X²,²As a result, the nonlinear characteristic (gamma characteristic) previously applied to the input video signal is corrected. Of the subfields SF1 to SF12, the number of subfields responsible for low-luminance light emission is greater than the number of subfields responsible for high-luminance light emission. That is, the number of subfields responsible for relatively low-luminance light emission for which the number of application of sustain pulse IP is 25 or less is eight from SF1 to SF8, which is greater than the number of subfields SF9 to SF12 responsible for high-luminance light emission. Many.
[0049]
Then, the erase step E is executed only in the last subfield SF12.
In the erasing process E, the address driver 6 generates a positive erasing pulse AP as shown in FIG._1-mApply to. Further, the second sustain driver 8 generates a negative erase pulse EP as shown in FIG. 15 simultaneously with the application timing of the erase pulse AP, and supplies this to the row electrode Y.₁~ Y_nApply to each. By simultaneously applying these erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, by this erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.
[0050]
Here, in each subfield shown in FIG. 18 or FIG. 19, only the discharge cell set as the “light emitting cell” in the pixel data writing process Wc is described above in the light emission sustaining process Ic performed immediately thereafter. The sustain discharge is repeated a number of times according to the frequency ratio, and the light emission state is maintained.
At this time, whether each discharge cell is set to “light emitting cell” or “non-light emitting cell” for each subfield is determined by display drive pixel data GD as shown in FIG. That is, each of the first to twelfth bits of the display drive pixel data GD corresponds to each of the subfields SF1 to SF12, and only when the logical level of the bit is a logical level “1”, for example, The selective erasure discharge is generated in the pixel data writing process Wc of the subfield corresponding to the above, and the discharge cell is set to the “non-light emitting cell”. On the other hand, when the logical level of the bit is the logical level “0”, the selective erasing discharge is not generated, and the current state is maintained. That is, the discharge cell of “non-light emitting cell” remains “non-light emitting cell”, and the discharge cell of “light emitting cell” maintains the state of “light emitting cell” as it is. At this time, in the subfields SF1 to SF12, the opportunity to change the discharge cell from the “non-light emitting cell” state to the “light emitting cell” is only the reset process Rc in the first subfield SF1. Therefore, after the end of the reset process Rc, the selective erasure discharge is generated in the pixel data writing process Wc in any one of the subfields SF1 to SF12, and the discharge cells once changed to the “non-light emitting cell” are In this field, there is no transition to the “light emitting cell” again. Therefore, according to the data pattern of the display drive pixel data GD as shown in FIG. 14, each discharge cell is “light emitting cell” only until the selective erasing discharge is generated in the subfield indicated by the black circle in FIG. The sustain discharge is performed as many times as described above in the light emission sustaining step Ic of each of the subfields indicated by white circles existing between them.
[0051]
As a result, when the input video signal is a TV signal and the luminance mode is 1, as shown in FIG.
When displaying odd fields (odd frames)
{0: 2: 4: 10: 18: 29: 46: 68: 96: 131: 174: 225: 255}
Gradation driving having luminance expression for 13 gradations is made,
When displaying even fields (even frames)
{0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 255}
Gradation driving having luminance expression for 13 gradations is performed.
[0052]
FIG. 20 is a diagram illustrating a correspondence relationship between the input video signal and the display luminance of an image actually displayed on the PDP 10 in accordance with the input video signal when the input video signal is a TV signal.
In FIG. 20, “□” indicates a gradation luminance point obtained by gradation driving according to the light emission driving sequence as shown in FIG. 18A, and “◇” indicates in FIG. 18B. The gradation luminance points obtained by gradation driving according to such a light emission driving sequence are shown.
[0053]
As shown in FIG. 20, when the input video signal is a TV signal, the light emission drive sequence as shown in FIGS. 18 (A) and 18 (B) is alternately performed for each field (one frame). Switch and implement. According to such driving, the gradation luminance point obtained by the other light emission driving sequence is added between the two gradation luminance points obtained by one light emission driving sequence.
[0054]
In FIG. 20, the luminance levels adjacent to each other, that is, the luminance between “□” and “" ”are obtained by multi-gradation processing such as error diffusion processing and dither processing as described above. .
FIG. 21 shows the gradation luminance point (“□”) obtained by the light emission drive sequence shown in FIG. 18A and the light emission drive sequence shown in FIG. 18B in the region E1 in FIG. Indicates the positional relationship between the gradation luminance point obtained ("◇"), the gradation luminance point obtained by error diffusion processing ("●"), and the gradation luminance point obtained by dither processing ("■") FIG.
[0055]
At this time, as shown in FIG. 21, a part (“■”) of each gradation luminance point that is obtained in a pseudo manner by the dither processing is shown in FIGS. 18 (A) and 18 (B). It has the same luminance level as the gradation luminance point (“□”) obtained by performing the light emission driving sequence.
Therefore, for an input video signal having a relatively poor S / N such as a TV signal, a pseudo gradation by the error diffusion process and the dither process while suppressing the flicker by the integration effect in the time direction and reducing the dither noise. The number will be increased.
[0056]
On the other hand, when the input video signal is a PC video signal having a relatively good S / N, as shown in FIG.
When displaying odd fields (odd frames)
{0: 1: 3: 7: 14: 25: 39: 59: 84: 117: 157: 205: 255}
Gradation driving having luminance expression for 13 gradations is made,
When displaying even fields (even frames)
{0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 255}
Gradation driving having luminance expression for 13 gradations is performed.
[0057]
FIG. 22 is a diagram illustrating a correspondence relationship between the input video signal and the display luminance of an image displayed on the PDP 10 in accordance with the input video signal when the input video signal is the PC video signal.
In FIG. 22, “□” indicates a gradation luminance point obtained by gradation driving according to the light emission driving sequence as shown in FIG. 19A, and “◇” indicates in FIG. 19B. The gradation luminance points obtained by gradation driving according to such a light emission driving sequence are shown.
[0058]
As shown in FIG. 22, when the input video signal is a PC video signal, as shown in FIG. 19 (A) and FIG. 19 (B) for each field (one frame), the gradation luminance is mutually equal. The light emission drive sequence in which the points are slightly shifted is alternately performed. According to such driving, a gradation luminance point obtained by the other light emission driving sequence is added at a position close to one gradation luminance point between two gradation luminance points obtained by one light emission driving sequence. It will be.
[0059]
In FIG. 22, the luminances other than the luminances indicated by the gradation luminance points “□” and “◇” are obtained by multi-gradation processing such as error diffusion processing and dither processing as described above.
FIG. 23 shows the gradation luminance point (“□”) obtained by the light emission drive sequence shown in FIG. 19A and the light emission drive sequence shown in FIG. 19B in the region E2 in FIG. Indicates the positional relationship between the gradation luminance point obtained ("◇"), the gradation luminance point obtained by error diffusion processing ("●"), and the gradation luminance point obtained by dither processing ("■") FIG.
[0060]
In this way, when the PC video signal is designated as input, at the time of the dither processing, as shown in FIG. 12, 3-bit dither coefficients a to d (a = 0, b = 2, c = 4, Since d = 6) is used, as shown in FIG. 23, the distribution of the gradation luminance points obtained by the error diffusion processing is coarse and dense.
Therefore, as shown in FIG. 23, each of the gradation luminance points obtained in a pseudo manner by the error diffusion process and the dither process, and the light emission drive sequence as shown in FIGS. 19 (A) and 19 (B). The gradation levels obtained from the above are different from each other.
[0061]
Therefore, due to the integration effect in the time direction, the number of display gradations in the visual sense employs the light emission drive sequence shown in FIG. 18 (that is, the light emission drive sequence used when a TV signal is designated as the input video signal). It increases approximately twice as much as the case.
That is, when a video signal having a relatively good S / N such as a PC video signal is designated as input, pseudo gradation luminance points obtained by error diffusion processing and dither processing are shown in FIG. As shown in FIG. 19B, the number of gradations expressed in a pseudo manner is greatly increased by shifting the gradation luminance points obtained by the light emission driving sequence.
[0062]
In the above embodiment, as a method for writing pixel data, wall charges are formed in advance in each discharge cell and all discharge cells are set as light emitting cells, and then the wall is selectively selected according to pixel data. The case where the so-called selective erasure address method of writing pixel data by erasing electric charges has been described.
However, the present invention can be similarly applied to a case where a so-called selective write addressing method in which wall charges are selectively formed according to pixel data as a pixel data writing method.
[0063]
FIG. 24 shows that the address driver 6, the first sustain driver 7 and the second sustain driver 8 are connected to the column electrode D of the PDP 10 when this selective write address method is adopted.₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nIt is a figure which shows an example of the application timing of the various drive pulses applied to.
FIG. 25 is a diagram showing a light emission drive sequence performed when a TV signal is designated as an input video signal when the selective write address method is adopted, and FIG. 26 is a diagram showing designation of a PC video signal. It is a figure which shows the light emission drive sequence implemented at the time. 25A and FIG. 26A each display an odd field (odd frame), and FIG. 25B and FIG. 26B each perform light emission when displaying an even field (even frame). Each drive sequence is shown.
[0064]
Further, FIG. 27 shows a conversion table used in the second data conversion circuit 34 shown in FIG. 6 and all the patterns of light emission driving performed within one field period when such a selective write address method is adopted. FIG.
Here, as shown in FIG. 24, when the selective write address method is adopted, first, in the simultaneous reset process Rc in the first subfield SF12, the first sustain driver 7 and the second sustain driver 8 are used. Are reset pulses RP to the row electrodes X and Y of the PDP 10, respectively._xAnd RP_YAre simultaneously applied. As a result, all discharge cells in the PDP 10 are reset and discharged, and wall charges are forcibly formed in each discharge cell (R₁). Immediately thereafter, the first sustain driver 7 sends the erase pulse EP to the row electrode X of the PDP 10.₁~ X_nTo all the discharge cells to erase the wall charges (R₂). That is, according to the execution of the simultaneous reset process Rc as shown in FIG. 24, all the discharge cells in the PDP 10 are once initialized to a “non-light emitting cell” state.
[0065]
Next, in the pixel data writing process Wc, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of the display drive pixel data bit DB supplied from the memory 5, and this is generated for one row. Each column electrode D sequentially_1-mApply to. That is, first, in the pixel data writing process Wc of the subfield SF12, the display drive pixel data bit DB12 is set._11-nmThe portion corresponding to the first line from the inside, that is, DB12_11-1mAnd extract these DB12_11-1mPixel data pulse group DP12 composed of m pixel data pulses corresponding to each logic level₁To generate a column electrode D_1-mApply to. Next, the display drive pixel data bit DB12 is displayed._11-nmDB12 corresponding to the second row of_21-2mAnd extract these DB12_21-2mPixel data pulse group DP12 composed of m pixel data pulses corresponding to each logic level₂To generate a column electrode D_1-mApply to. Similarly, in the pixel data writing process Wc of the subfield SF12, the pixel data pulse group DP12 for each row is similarly processed._Three~ DP12_nSequentially column electrode D_1-mApply to. Subsequently, in the pixel data writing process Wc of the subfield SF11, first, the display drive pixel data bit DB11 is used._11-nmThe portion corresponding to the first line from the inside, that is, DB11_11-1mAnd extract these DB11_11-1mPixel data pulse group DP11 composed of m pixel data pulses corresponding to each logic level₁To generate a column electrode D_1-mApply to. Next, such display drive pixel data bit DB11._11-nmDB11 corresponding to the second row of_21-2mAnd extract these DB11_21-2mPixel data pulse group DP11 composed of m pixel data pulses corresponding to each logic level₂To generate a column electrode D_1-mApply to. Hereinafter, similarly, in the pixel data writing process Wc of the subfield SF11, the pixel data pulse group DP11 for each row is processed._Three~ DP11_nSequentially column electrode D_1-mApply to. Hereinafter, in the pixel data writing process Wc in each of the subfields SF10 to SF1, the address driver 6 similarly displays the display drive pixel data bit DB10._11-nm~ DB1_11-nmPixel data pulse group DP10 generated based on each_1-n~ DP1_1-nEach is assigned to each of subfields SF10 to SF1, and these are assigned to column electrode D._1-mIt is applied to. The address driver 6 generates a high-voltage pixel data pulse when the logic level of the display drive pixel data bit DB is “1”, and generates a low voltage (0 volt) when it is “0”. Assume that a pixel data pulse is generated.
[0066]
Further, in the pixel data writing process Wc, the second sustain driver 8 generates the negative scan pulse SP as shown in FIG. 246 at the same timing as each application timing of the pixel data pulse group DP as described above. This is the row electrode Y₁~ Y_nApply sequentially to. At this time, a discharge (selective write discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. Wall charges are selectively formed inside. Due to the selective write discharge, the discharge cell initialized to the “non-light emitting cell” state in the simultaneous reset process Rc changes to “light emitting cell”. On the other hand, the selective write discharge does not occur in the discharge cells formed in the “column” to which the low-voltage pixel data pulse is applied, and the current state is maintained. That is, the discharge cell of “non-light emitting cell” remains “non-light emitting cell”, and the discharge cell of “light emitting cell” maintains the state of “light emitting cell” as it is. As described above, the pixel data writing process Wc for each subfield includes a “light emitting cell” in which a sustain discharge is generated in the light emission sustaining process Ic immediately after that and a “non-light emitting cell” in which no sustain discharge is generated. Is set.
[0067]
Next, in the light emission sustaining process Ic of each subfield, the first sustain driver 7 and the second sustain driver 8 are respectively connected to the row electrode X.₁~ X_nAnd Y₁~ Y_nOn the other hand, as shown in FIG._XAnd IP_YApply. At this time, as shown in FIG. 25 or FIG. 26, the number of sustain pulses IP to be applied in the light emission sustain process Ic of each subfield varies depending on the type of the video signal selected as the input video signal.
[0068]
Then, as shown in FIG. 24, when the selective write address method is adopted, the erase process E is executed only in the last subfield SF1.
In the erasing process E, the address driver 6 generates a negative erasing pulse EP as shown in FIG.₁~ Y_nApply to each simultaneously. By the simultaneous application of the erase pulse EP, an erase discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, by this erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.
[0069]
Here, in the pixel data writing process Wc in each subfield shown in FIG. 25 or FIG. 26, only the discharge cell set as the “light emitting cell” is in the light emission sustaining process Ic performed immediately thereafter. The sustain discharge is repeated as many times as described in the figure, and the light emission state is maintained.
At this time, whether the discharge cell is set to “light emitting cell” or “non-light emitting cell” in the data writing process Wc of each subfield is determined by display drive pixel data GD as shown in FIG. . That is, each of the first to twelfth bits of the display drive pixel data GD corresponds to each of the subfields SF1 to SF12, and only when the logical level of the bit is, for example, the logical level “1”, In the corresponding sub-field pixel data writing step Wc, the selective writing discharge as described above is generated, and the discharge cell is set to the “light emitting cell”. On the other hand, when the logical level of the bit is the logical level “0”, the selective write discharge as described above is not generated, and the current state is maintained. That is, the discharge cell of “non-light emitting cell” remains “non-light emitting cell”, and the discharge cell of “light emitting cell” maintains the state of “light emitting cell” as it is. At this time, in the subfields SF12 to SF1, the opportunity to change the discharge cell from the “light emitting cell” state to the “non-light emitting cell” is only the reset process Rc in the first subfield SF12. Accordingly, after this reset process Rc is completed, a selective write discharge is generated in the pixel data writing process Wc of any one of the subfields SF12 to SF1, and the discharge cells that have once shifted to the “light emitting cell” are In this field, there is no transition to a “non-light emitting cell” again.
Therefore, according to the display drive pixel data GD shown in FIG. 27, each discharge cell is in a “non-light emitting cell” state until the selective write discharge is generated in the subfield indicated by the black circle in FIG. In the emission sustaining process Ic for each subfield after the black circle, the sustain discharge is repeated as many times as described in FIG. 25 or 26 to maintain the discharge light emission state.
[0070]
Thus, when the input video signal is a TV signal and the luminance mode is 1, as shown in FIG.
When displaying odd fields (odd frames)
{0: 2: 4: 10: 18: 29: 46: 68: 96: 131: 174: 225: 255}
Gradation driving having luminance expression for 13 gradations is made,
When displaying even fields (even frames)
{0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 255}
Gradation driving having luminance expression for 13 gradations is performed.
[0071]
On the other hand, when the input video signal is a PC video signal, as shown in FIG.
When displaying odd fields (odd frames)
{0: 1: 3: 7: 14: 25: 39: 59: 84: 117: 157: 205: 255}
Gradation driving having luminance expression for 13 gradations is made,
When displaying even fields (even frames)
{0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 255}
Gradation driving having luminance expression for 13 gradations is performed.
[0072]
At this time, the luminance expression by such gradation driving is the same as when the selective erasure address method as described above is adopted as the pixel data writing method.
Therefore, even when the selective write address method is employed, the number of pseudo gradations can be increased appropriately according to the type of the video signal designated as input, as in the case where the selective erase address method is employed. .
[0073]
In the above embodiment, in one of the subfields SF1 to SF12, the selective erase (write) discharge is performed by simultaneously applying the scan pulse SP and the high-voltage pixel data pulse in the pixel data write process Wc. However, if the amount of charged particles remaining in the discharge cell is small, this selective erasing (writing) discharge is not normally generated, and the wall charge in the discharge cell is normally erased (formed). ) It may not be possible. At this time, even if the pixel data D after A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, which causes a problem that the image quality is remarkably deteriorated.
[0074]
Therefore, the conversion table used in the second data conversion circuit 34 is changed from the one shown in FIGS. 14 and 27 to the one shown in FIGS. 28 and 29, and gradation driving is performed. FIG. 28 is a diagram showing a conversion table used by the second data conversion circuit 34 when the selective erasure address method is adopted, and a light emission driving pattern implemented within one field period, and FIG. It is a figure which shows the said conversion table and light emission drive pattern at the time of employ | adopting a built-in address method. Here, “*” shown in FIG. 28 and FIG. 29 indicates that either the logic level “1” or “0” may be used, and the triangle mark indicates that “*” is the logic level “1”. This indicates that selective erasing (writing) discharge is generated only when.
[0075]
According to the display drive pixel data GD shown in FIGS. 28 and 29, at least two “selective erasure (write) discharges” are performed continuously. In short, since there is a possibility that writing of pixel data may fail in the first selective erasing (writing) discharge, selective erasing (writing) discharge is performed again in at least one of the subfields existing thereafter. By doing so, the writing of the pixel data is ensured and an erroneous light emission operation is prevented.
[0076]
【The invention's effect】
As described above in detail, in the method for driving a plasma display panel according to the present invention, the ratio of the number of times of light emission performed in each of the light emission sustaining steps in one field (one frame) period depends on the type of the input video signal. The first and second light emission drive sequences that are executed by alternately switching the first and second light emission drive sequences for each field (one frame), and the third and third light emission frequency ratios that are executed in each of the light emission sustaining steps are different from each other. One of the four light emission drive sequences is selectively executed from the second drive pattern executed by alternately switching the four light emission drive sequences for each field (one frame).
[0077]
At this time, if the type of the input video signal is a TV signal, the gradation luminance point obtained by the first light emission drive sequence and the second light emission are obtained by selectively executing the first drive pattern. The gradation luminance point that is artificially obtained by multi-gradation processing such as error diffusion and dither processing during execution of the drive sequence is set to the same luminance level. On the other hand, when the type of the input video signal is a PC video signal, the gradation luminance point obtained by the third light emission drive sequence and the fourth light emission are obtained by selectively executing the second drive pattern. When the drive sequence is executed, the gradation luminance points that are artificially obtained by the multi-gradation processing such as error diffusion and dither processing are set to different luminance levels.
[0078]
Therefore, when performing display based on a video signal having a relatively poor S / N such as a TV signal, multi-gradation such as error diffusion and dither processing is performed while suppressing generation of flicker and noise due to dither. The number of pseudo gradations can be increased by the processing. On the other hand, when displaying based on a video signal having a relatively good S / N such as a PC video signal, the number of gradations obtained in a pseudo manner by the multi-gradation processing such as the error diffusion and dither processing is substantially omitted. Can be doubled.
[Brief description of the drawings]
FIG. 1 is a diagram showing a light emission drive sequence for carrying out halftone display of 64 gradations.
FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.
3 is a diagram showing an internal configuration of a data conversion circuit 30. FIG.
4 is a diagram showing an internal configuration of an ABL circuit 31. FIG.
FIG. 5 is a diagram showing conversion characteristics in the data conversion circuit 312;
6 is a diagram showing an internal configuration of a first data conversion circuit 32. FIG.
7 is a diagram showing data conversion characteristics used in the first data conversion circuit 32 when a TV signal is designated for input. FIG.
FIG. 8 is a diagram showing data conversion characteristics used in the first data conversion circuit 32 when a PC video signal is designated as input.
9 is a diagram showing an internal configuration of a multi-gradation processing circuit 33. FIG.
FIG. 10 is a diagram for explaining the operation of an error diffusion processing circuit 330;
11 is a diagram showing an internal configuration of a dither processing circuit 350. FIG.
FIG. 12 is a diagram illustrating values of dither coefficients a to d for each type of input video signal.
13 is a diagram for explaining the operation of a dither processing circuit 350. FIG.
14 is a diagram showing a conversion table of the second data conversion circuit 34, and a light emission drive pattern and display luminance based on display drive pixel data GD obtained by the conversion table. FIG.
FIG. 15 is a diagram showing application timings of various drive pulses applied to the PDP 10 within one field display period when the selective erase address method is employed.
FIG. 16 is a diagram showing a correspondence relationship between each luminance mode and the number of application times of the sustain pulse IP in the light emission sustain process Ic of each of the subfields SF1 to SF12 when a TV signal is designated as input.
FIG. 17 is a diagram illustrating a correspondence relationship between a luminance mode and the number of times of application of a sustain pulse IP in the light emission sustain process Ic of each of subfields SF1 to SF12 when a PC video signal is designated as input.
FIG. 18 is a diagram illustrating an example of a light emission driving sequence that is performed when a TV signal is input.
FIG. 19 is a diagram illustrating an example of a light emission drive sequence performed when a PC video signal is input.
FIG. 20 is a diagram showing display luminance characteristics with respect to an input video signal when a TV signal is designated for input.
FIG. 21 is a diagram showing a positional relationship between each gradation luminance point obtained by the light emission drive sequence shown in FIG. 18 and each gradation luminance point obtained by the error diffusion processing and dither processing in the area E1 in FIG. It is.
FIG. 22 is a diagram showing display luminance characteristics with respect to an input video signal when a PC video signal is designated for input.
FIG. 23 is a diagram showing a positional relationship between each gradation luminance point obtained by the light emission drive sequence shown in FIG. 19 and each gradation luminance point obtained by the error diffusion processing and dither processing in the area E2 in FIG. It is.
FIG. 24 is a diagram showing application timings of various drive pulses applied to the PDP 10 within one field display period when the selective write address method is employed.
FIG. 25 is a diagram showing a light emission drive sequence (adopting a selective writing address method) that is performed when an input designated video signal is a TV signal.
FIG. 26 is a diagram showing a light emission drive sequence (adopting a selective writing address method) that is performed when an input designated video signal is a PC video signal.
FIG. 27 shows a conversion table of the second data conversion circuit 34 used when the selective write address method is adopted, and a light emission drive pattern and display luminance corresponding to the display drive pixel data GD obtained by this conversion table. FIG.
FIG. 28 shows another example of the conversion table of the second data conversion circuit 34 used when the selective erasure address method is adopted, and the light emission drive pattern and display corresponding to the display drive pixel data GD obtained by this conversion table. It is a figure which shows a brightness | luminance.
29 shows another example of the conversion table of the second data conversion circuit 34 used when the selective write address method is adopted, and the light emission drive pattern according to the display drive pixel data GD obtained by this conversion table; It is a figure which shows display luminance.
[Explanation of main part codes]
1 Operation device
2 Drive control circuit
3 Input selector
6 Address driver
7 First Sustain Driver
8 Second Sustain Driver
10 PDP
30 Data conversion circuit
31 ABL circuit 31
32 First data conversion circuit
33 Multi-gradation processing circuit
34 Second data conversion circuit
330 Error diffusion processing circuit
350 dither processing circuit

Claims (24)

A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
The unit display period is divided into N divided display periods, and in each of the divided display periods, the discharge cell of the discharge cell is changed according to N-bit display drive pixel data obtained by performing multi-gradation processing on the input video signal. A light emission drive sequence for executing a pixel data writing step for setting each of the light emitting cells or one of the light emitting cells and a light emission maintaining step for causing only the light emitting cells to emit light for the number of times corresponding to the weighting of each of the divided display periods. Have
In the light emission drive sequence, first and second light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process in each of the N divided display periods are alternately switched for each unit display period. The first drive pattern to be executed and the third and fourth light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process of each of the N divided display periods are alternately displayed for each unit display period. It consists of a second drive pattern to be switched and
Of the number of times of light emission assigned to each of the N divided display periods in the first light emission drive sequence, k times (k: an integer not less than N and less than N) and (k + 1) th number of light emission times. T1 (k) and T1 (k + 1), respectively, and the light emission that is the kth and (k + 1) th smallest among the number of times of light emission assigned to each of the N divided display periods in the second light emission drive sequence. When the number of times is T2 (k) and T2 (k + 1), respectively,
T1 (k) <T2 (k) <T1 (k + 1) <T2 (k + 1)
Has a large and small relationship
Of the number of times of light emission assigned to each of the N divided display periods in the third light emission drive sequence, the number of times of light emission that is the kth and (k + 1) th smallest is set to T3 (k) and T3 (k + 1), respectively. The number of times of light emission that is the kth and (k + 1) th smallest among the number of times of light emission assigned to each of the N divided display periods in the fourth light emission drive sequence is T4 (k) and T4 ( k + 1),
T3 (k) <T4 (k) <T3 (k + 1) <T4 (k + 1)
Has a large and small relationship
A driving method of a plasma display panel, wherein the first driving pattern and the second driving pattern are alternatively executed according to a type of the input video signal. 2. The method of claim 1, wherein the input video signal is a video signal or a television signal from a personal computer. 2. The method of driving a plasma display panel according to claim 1, wherein the unit display period is one field or one frame display period of the input video signal. The luminance level of each gradation luminance point obtained by executing the first light emission driving sequence is made to coincide with the luminance level at each gradation luminance point obtained by the multi-gradation processing when the second light emission driving sequence is executed. ,
The luminance level of each gradation luminance point obtained by execution of the third light emission driving sequence is different from the luminance level at each gradation luminance point obtained by the multi-gradation processing when the fourth light emission driving sequence is executed. The method of driving a plasma display panel according to claim 1, wherein: A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
The unit display period is divided into N divided display periods, and in each of the divided display periods, the discharge cell of the discharge cell is changed according to N-bit display drive pixel data obtained by performing multi-gradation processing on the input video signal. A light emission drive sequence for executing a pixel data writing step for setting each of the light emitting cells or one of the light emitting cells and a light emission maintaining step for causing only the light emitting cells to emit light for the number of times corresponding to the weighting of each of the divided display periods. Have
The light emission drive sequence includes first and second light emission drive sequences in which the ratio of the number of times of light emission in the sustain light emission process of each of the N divided display periods is different from each other.
Alternately executing the first light emission drive sequence and the second light emission drive sequence;
The luminance level at each gradation luminance point obtained by executing the first light emission driving sequence is made to coincide with the luminance level at each gradation luminance point obtained by the multi-gradation processing when the second light emission driving sequence is executed. A method for driving a plasma display panel. 6. The method of driving a plasma display panel according to claim 5, wherein the input video signal is a television signal. 6. The method of driving a plasma display panel according to claim 5, wherein the unit display period is one field or one frame display period of the input video signal. A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
The unit display period is divided into N divided display periods, and in each of the divided display periods, the discharge cell of the discharge cell is changed according to N-bit display drive pixel data obtained by performing multi-gradation processing on the input video signal. A light emission drive sequence for executing a pixel data writing step for setting each of the light emitting cells or one of the light emitting cells and a light emission maintaining step for causing only the light emitting cells to emit light for the number of times corresponding to the weighting of each of the divided display periods. Have
The light emission drive sequence includes first and second light emission drive sequences in which the ratio of the number of times of light emission in the sustain light emission process of each of the N divided display periods is different from each other.
Alternately executing the first light emission drive sequence and the second light emission drive sequence;
The luminance level at each gradation luminance point obtained by executing the first light emission driving sequence is different from the luminance level at each gradation luminance point obtained by the multi-gradation processing at the time of executing the second light emission driving sequence. A method for driving a plasma display panel. 9. The method according to claim 8, wherein the input video signal is a video signal from a personal computer. 9. The method of driving a plasma display panel according to claim 8, wherein the unit display period is one field or one frame display period of the input video signal. 2. The plasma display panel according to claim 1, wherein a nonlinear display characteristic of the input video signal is corrected by setting a ratio of the number of times of light emission in the light emission maintenance process in each of the divided display periods to be nonlinear. Driving method. 12. The driving method of the plasma display panel according to claim 11, wherein the nonlinear display characteristic is a gamma characteristic. 12. The method of driving a plasma display panel according to claim 11, wherein the multi-gradation processing is executed before correcting the nonlinear display characteristic of the input video signal. The multi-gradation processing includes de I The process The method as claimed in claim 1, wherein changing the dither coefficients in the dither processing for each of the unit display period. The pixel data corresponding to the input video signal is separated at a bit boundary between an upper bit group and a lower bit group necessary for the multi-gradation process before the multi-gradation process is performed. 2. A driving method of a plasma display panel according to 1. Performing a reset process that initializes all the discharge cells to either the light emitting cells or the non-light emitting cells only in the divided display period at the top of the unit display period,
The discharge cell is set to one of a non-light-emitting cell and a light-emitting cell only in the pixel data writing process in any one of the divided display periods according to the display driving pixel data. 2. A driving method of a plasma display panel according to 1. Performing a reset process that initializes all the discharge cells to either the light emitting cells or the non-light emitting cells only in the divided display period at the top of the unit display period,
In the pixel data writing process in any one of the divided display periods, a first discharge that causes the discharge cell to be set to one of the non-light emitting cell or the light emitting cell according to the display driving pixel data is generated. A pixel data pulse is applied to the column electrode, and a second pixel data pulse that is the same as the first pixel data pulse is applied to the column electrode in the pixel data writing process in the divided display period that exists immediately thereafter. 2. The method of driving a plasma display panel according to claim 1, wherein the voltage is applied. 18. The driving of a plasma display panel according to claim 16, further comprising an erasing process for setting all the discharge cells to a non-light emitting cell state only in the last divided display period in the unit display period. Method. In the reset process, all the discharge cells are initialized to the state of the light emitting cells,
18. In the pixel data writing step, the discharge cells are set to the non-light emitting cells by selectively erasing and discharging the discharge cells in accordance with the display driving pixel data. The method for driving a plasma display panel according to any one of the above. In the reset process, all the discharge cells are initialized to the state of the non-light emitting cells,
18. In the pixel data writing step, the discharge cell is set as the light emitting cell by selectively writing and discharging the discharge cell in accordance with the display driving pixel data. The method for driving a plasma display panel according to any one of the above. N + 1 gradation driving is performed by causing the light emitting cell to emit light only in the light emission sustaining process in each of the n (n is 0 to N) continuous display periods from the beginning of the unit display period. The method for driving a plasma display panel according to claim 1 or 19. N + 1 gradation driving is performed by causing the light emitting cell to emit light only in the light emission sustaining process in each of the n divided display periods (n is 0 to N) continuous from the end of the unit display period. 21. The method of driving a plasma display panel according to claim 1, wherein the plasma display panel is driven. In each of the divided display periods arranged in the unit display period, the number of divided display periods to which the number of light emission times smaller than the predetermined number is assigned is assigned the number of light emission times larger than the predetermined number of times. the method as claimed in claim 21 or 22, wherein a greater than the number of which divided display periods. A driving method of a plasma display panel in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
The unit display period is divided into N divided display periods, and in each of the divided display periods, the discharge cell of the discharge cell is changed according to N-bit display drive pixel data obtained by performing multi-gradation processing on the input video signal. A light emission drive sequence for executing a pixel data writing step for setting each of the light emitting cells or one of the light emitting cells and a light emission maintaining step for causing only the light emitting cells to emit light for the number of times corresponding to the weighting of each of the divided display periods. Have
In the light emission drive sequence, first and second light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process in each of the N divided display periods are alternately switched for each unit display period. The first drive pattern to be executed and the third and fourth light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process of each of the N divided display periods are alternately displayed for each unit display period. A second drive pattern that is executed by switching,
The first k-th gray level obtained by the execution of the light emission drive sequence (k: 1 or more integer less than N) and the (k + 1) the luminance level of the gradation and each Y1 (k) and Y1 (k + 1), the When the luminance levels of the kth gradation and the (k + 1) th gradation obtained by executing the second light emission drive sequence are Y2 (k) and Y2 (k + 1), respectively.
Y1 (k) <Y2 (k) <Y1 (k + 1) <Y2 (k + 1)
Has a large and small relationship
The luminance levels of the kth gradation and the (k + 1) th gradation obtained by executing the third light emission driving sequence are Y3 (k) and Y3 (k + 1), respectively, and the fourth light emission driving sequence obtained by executing the fourth light emission driving sequence. When the luminance levels of the k gradation and the (k + 1) th gradation are Y4 (k) and Y4 (k + 1), respectively.
Y3 (k) <Y4 (k) <Y1 (k + 1) <Y2 (k + 1)
Has a large and small relationship
A driving method of a plasma display panel, wherein the first driving pattern and the second driving pattern are alternatively executed according to a type of the input video signal.

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