JP2001056665A - Method for driving plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve display quality an gradation expressive power by selectively executing a first drive pattern and a second drive pattern according to the kind of an input video signal. SOLUTION: A plasma display device for luminous-driving this panel consists of a drive part consisting of an operating device 1, a drive control circuit 2, an input selector 3, an A/D converter 4, a data conversion circuit 30, a memory 5, an address driver 6 and first and second sustain drivers 7, 8 and a PDP 10 as a plasma display panel. At this time, the luminous drive sequence consists of the first drive pattern alternately switching respective first and second luminous drive sequences that the ratios of the number of luminous times in respective sustain luminous processes among N pieces of division display devices are different from each other to execute it and the second drive pattern alternately switching respective third and fourth luminous drive sequences that the ratios of the number of luminous times in respective sustained luminous processes among N pieces of division display devices are different from each other to execute it. Then, the first and the second drive patterns are executed selectively according to the kind of the input video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel (hereinafter, referred to as PDP) of a matrix display system.

[0002]

2. Description of the Related Art As one of such matrix display type PDPs, an AC (AC discharge) type PDP is known.
The AC type PDP includes a plurality of column electrodes (address electrodes),
They are arranged orthogonally to these column electrodes and
And a plurality of row electrode pairs forming a scanning line.
Each row electrode pair and column electrode is covered with a dielectric layer with respect to the discharge space, and has a structure in which a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .

At this time, since the PDP utilizes a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, a subfield method is used to realize halftone luminance display by such a PDP. In the subfield method, a display period of one field is divided into N subfields, and a light emission period having a period length corresponding to the weight of each bit digit of pixel data (N bits) is assigned to each subfield. To perform light emission driving.

For example, when one field period is divided into six subfields SF1 to SF6 as shown in FIG. 1, SF1: 1 SF2: 2 SF3: 4 SF4: 8 SF5: 16 SF6: 32 Light emission driving is performed at a light emission period ratio.

Here, when the discharge cells are to emit light at a luminance of "32", as shown in FIG.
Light emission is performed only in SF6 of F1 to SF6.
When light is emitted at a luminance of "31", light emission is performed in other subfields SF1 to SF5 except the subfield SF6. As a result, it is possible to express halftone luminance in 64 steps.

As is apparent from the sequence of FIG. 1, the number of gradations can be increased by increasing the number of subfields. However, in one subfield, a pixel data writing process for selecting a light emitting cell is required. Therefore, as the number of subfields increases, the number of pixel data writing processes to be performed in one field also increases. As a result, the time allocated to the light emission period (the length of the light emission sustaining step) within one field period becomes relatively short, which causes a reduction in luminance.

[0007] Therefore, in order to realize a video display by a PDP, it is necessary to perform some multi-gradation processing on the video signal itself. As a method of increasing the number of gradations, for example, an error diffusion process is known. The error diffusion process is a method of pseudoly increasing the number of gradations by adding an error between pixel data corresponding to a certain pixel (discharge cell) and a predetermined threshold to pixel data corresponding to peripheral pixels.

However, when the original number of gradations is small, the error diffusion pattern becomes conspicuous, and there is a problem that the S / N is deteriorated.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a method of driving a plasma display panel capable of improving the gradation expression while improving the display quality. The purpose is to provide.

[0010]

According to the present invention, there is provided a driving method of a plasma display panel, wherein each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A driving method of a plasma display panel forming discharge cells corresponding to one pixel, wherein a unit display period is divided into N divided display periods,
In each of the divided display periods, a pixel for setting each of the discharge cells as one of a non-light-emitting cell and a light-emitting cell according to N-bit display drive pixel data obtained by performing a multi-gradation process on an input video signal A light emission driving sequence for performing a data writing step and a light emission sustaining step of causing only the light emitting cells to emit light the number of times corresponding to the weighting of each of the divided display periods. A first drive pattern in which first and second light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process in each of the divided display periods are alternately executed for each unit display period; Third and fourth light emission drive sequences having different ratios of the number of times of light emission in the sustain light emission process in each of the divided display periods are alternately performed for each unit display period Switched it consists of a second drive pattern to be executed alternatively to perform the first drive pattern and the second drive pattern according to the type of the input video signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel to emit light based on a driving method according to the present invention. Such a plasma display device includes an operating device 1, a drive control circuit 2, an input selector 3, an A / D converter 4, a data conversion circuit 30, a memory 5, an address driver 6, a first sustain driver 7, and a second sustain driver 8. Drive unit and PDP1 as plasma display panel
0.

Incidentally, this plasma display device has an N
In addition to a television signal such as the TSC system, it also supports a PC video signal which is a video signal from a personal computer, and a dedicated input terminal (not shown) for inputting video signals of different systems. ) Are individually provided. In FIG. 2, the operation device 1 is configured to input an image designation signal S _V corresponding to the image signal designated by the user.
Is generated and supplied to each of the drive control circuit 2, the input selector 3, and the data conversion circuit 30. For example, when the user specifies the PC video signal as the video signal to be displayed, the operation device 1 sets the logical level to “0”,
When a color television signal (hereinafter, referred to as a TV signal) is designated, the input video designation signal S _{V at the} logical level “1”
Generate

The input selector 3 selects one of the PC video signal and the TV signal supplied through the input terminal,
The one corresponding to the input video designation signal S _V is selected and supplied to the A / D converter 4 as an input video signal. Each of the PC video signal and the TV signal has been subjected to gamma correction processing in advance. The A / D converter 4
The input video signal supplied from the input selector 3 is sampled according to the clock signal supplied from the drive control circuit 2 and converted into, for example, 8-bit pixel data D for each pixel. That is, the A / D converter 4 converts the analog input video signal supplied from the input selector 3 into 2
This is converted into 8-bit pixel data capable of expressing luminance in 56 gradations.

The data conversion circuit 30 displays the data obtained by subjecting the 8-bit pixel data D to the brightness adjustment and the multi-gradation processing to display each pixel of the PDP 10 for actually emitting light. The data is converted into driving pixel data GD and supplied to the memory 5. FIG. 3 is a diagram showing an internal configuration of the data conversion circuit 30. As shown in FIG. 3, the data conversion circuit 30 includes an ABL (automatic brightness control) circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second
It is composed of a data conversion circuit 34.

The ABL circuit 31 controls the pixel data D for each pixel sequentially supplied from the A / D converter 4 so that the average luminance of the image displayed on the screen of the PDP 10 falls within an appropriate luminance range. adjusts the luminance levels for, and supplies the time resulting luminance adjusted pixel data D _BL to the first data conversion circuit 32. FIG. 4 is a diagram showing the internal configuration of the ABL circuit 31.

In FIG. 4, the level adjustment circuit 310
Outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average luminance obtained by the average luminance detecting circuit 311 which will be described later. Data conversion circuit 31
2, the average luminance level detection circuit 311 converts the luminance adjustment pixel data _DBL into an inverse gamma characteristic (Y = X ^2.2 ) having a non-linear characteristic as shown in FIG. Supply. That is, by performing inverse gamma correction processing on the luminance adjustment pixel data _DBL , pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal from which gamma correction has been canceled is restored. The average luminance detection circuit 311 first obtains the average luminance of the inverse gamma conversion pixel data Dr. here,
The average brightness detection circuit 311 is a brightness mode 1 in which the range from the highest brightness to the lowest brightness is classified into four levels.
, And supplies the luminance mode signal LC indicating the corresponding luminance mode to the drive control circuit 2 and supplies the average luminance determined as described above to the level adjustment circuit 310. I do. In other words, the level adjustment circuit 310 supplies that adjusts the level of pixel data D in response to the average luminance to the data conversion circuit 312 and the next stage of the first data conversion circuit 32, as the luminance adjusted pixel data D _BL You do it.

FIG. 6 is a diagram showing the internal configuration of the first data conversion circuit 32. 6, the data conversion circuit 321, the luminance adjusted pixel data D _BL to based on it such conversion characteristics shown in Fig. 7 (A) 8-bit to "0" to "192" converted pixel data A ₁ And supplies this to the selector 322. Data conversion circuit 323 converts the luminance adjusted pixel data D _BL in FIG. 7 converts the 8-bit from "0" to "192" based on, but such conversion characteristics as shown in (B) pixel data B ₁ This is supplied to the selector 322. The selector 322 selects _{one of the} converted pixel data A ₁ and B ₁ according to the logic level of the conversion characteristic selection signal, and supplies the selected one to the selector 324. The conversion characteristic selection signal is transmitted to the drive control circuit 2
From the logical level "1" to "0" or from "0" to "0" according to the vertical synchronization timing of the input video signal.
This signal changes to 1 ". The data conversion circuit 325
Is this by converting the luminance adjusted pixel data D _BL 8 based on but such conversion characteristics as shown in (A) "0" ~ "384" in the 9-bit converted pixel data A ₂ to the selector 32
6 Data conversion circuit 327 converts the above luminance adjusted pixel data D _BL to based on it such conversion characteristics shown in FIG. 8 (B) of 9 bits to "0" to "384" converted pixel data B ₂ This is supplied to the selector 326. The selector 326 selects one of the conversion pixel data A ₂ and B ₂ according to the logic level of the conversion characteristic selection signal, and supplies the selected one to the selector 324. The selector 324 is converted supplied from the selector 322 pixel data A ₁ (or B _1), and from among the converted pixel data A ₂ supplied (or B ₂₎ from the selector 326, the logic of the input video designation signal S _V Select one according to the level,
This is supplied to the next-stage multiple gradation processing circuit 33 as first converted pixel data _DH .

With the configuration shown in FIG. 6, when the TV signal is designated by the operating device 1, the first data conversion circuit 32 outputs "0" to "0" based on the conversion characteristics shown in FIG. 255 "becomes 8 bits of the luminance adjusted pixel data D _BL" 0 "~" 192 "becomes 8 supplies is converted into first conversion pixel data D _H of bits in the multi-gradation processing circuit 33. On the other hand, when the input of the PC video signal is designated, the 8-bit luminance adjustment pixel data _DBL of "0" to "255" is changed from "0" to "384" based on the conversion characteristics shown in FIG. That is, the data is converted into 9-bit first converted pixel data D _H and supplied to the multi-gradation processing circuit 33. 7 (A) and FIG.
(A) Display of odd field (odd frame), FIG. 7 (B)
FIG. 8B shows conversion characteristics used when displaying an even-numbered field (even-numbered frame). That is, when a TV signal is specified as input, the first data conversion circuit 32 switches the conversion characteristics used for the conversion as shown in FIGS. 7A and 7B for each field (frame). When a PC video signal is specified, FIG.
And the conversion characteristics are switched as shown in FIG.

As described above, the multiple gradation processing circuit 3 described later
3, a first data conversion circuit 32 is provided in the preceding stage to perform data conversion in accordance with the number of display gradations and the number of compression bits by multi-gradation, so that luminance saturation and display gradation by multi-gradation processing are reduced. The occurrence of a flat portion of the display characteristics (that is, the occurrence of gradation distortion) that occurs when the display characteristic is not at the bit boundary is prevented. FIG. 9 is a diagram showing the internal configuration of the multi-gradation processing circuit 33.

As shown in FIG. 9, a multi-gradation processing circuit
33 is an error diffusion processing circuit 330 and a dither processing circuit 3
50. First, the error diffusion processing circuit 330
The data separation circuit 331 in the first data conversion circuit
8 or 9-bit first converted pixel data supplied from the
Data D_HThe upper 6 bits in the display data, lower 2 or
The three bits are separated as error data. Adder 3
32 is the first converted pixel data as such error data
D_HFrom the lower 2 or 3 bits in the middle and the delay circuit 334
And the multiplied output of the coefficient multiplier 335 are added.
The obtained sum is supplied to the delay circuit 336. Delay circuit 3
36, the added value supplied from the adder 332 is
Delay time D having the same time as the data clock cycle
, And this is delayed by the delayed addition signal AD.₁Multiplied by the above coefficient
The signals are supplied to an arithmetic unit 335 and a delay circuit 337, respectively. Power
The adder 335 outputs the delayed addition signal AD₁To the predetermined coefficient value K₁
(For example, "7/16")
It is supplied to the calculator 332. The delay circuit 337 provides the delay
Calculation signal AD ₁Further, (1 horizontal scanning period−the delay time D ×
4) A signal delayed by a certain time is a delayed addition signal AD_Two
Is supplied to the delay circuit 338. The delay circuit 338
Such a delay addition signal AD_TwoIs further delayed by the delay time D.
The delayed signal is a delayed addition signal AD_ThreeAs coefficient multiplier 3
39. Further, the delay circuit 338 controls the delay addition.
Calculation signal AD_TwoAnd the above delay time D × 2
The delayed signal is a delayed addition signal AD_FourAs coefficient multiplier
340. Further, the delay circuit 338 controls the delay.
Deferred addition signal AD_TwoFor the time of the delay time D × 3
The delayed signal is a delayed addition signal AD_FiveAs coefficient multiplier
341. The coefficient multiplier 339 performs the delay addition.
Signal AD_ThreeTo the predetermined coefficient value K_Two(For example, "3/16")
The obtained multiplication result is supplied to the adder 342. Coefficient multiplication
The device 340 receives the delay addition signal AD._FourTo the predetermined coefficient value K
_Three(For example, "5/16")
To the container 342. The coefficient multiplier 341 calculates the delay
Calculation signal AD_FiveTo the predetermined coefficient value K_Four(For example, "1/16")
The multiplication result obtained is supplied to the adder 342. Adder
342 is each of the coefficient multipliers 339, 340 and 341
Addition signal obtained by adding the multiplication results supplied from each
Is supplied to the delay circuit 334. The delay circuit 334
The sum signal is delayed by the time corresponding to the delay time D.
And supplies it to the adder 332. The adder 332 is
Error data (first converted pixel data D_HMiddle 2 or 3
Bit), the delay output from the delay circuit 334, and the coefficient power
And the multiplication output of the adder 335.
Logical level "0" if not present, logical if carry
Carry out signal C of level "1"_OAnd the adder 33
Supply 3 The adder 333 outputs the display data (first
Conversion pixel data D_H(For the upper 6 bits in the middle)
Out signal C_O6-bit error diffusion processing
Output as the physical pixel data ED.

The operation of the error diffusion processing circuit 330 having the above configuration will be described below. For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 10, first, the pixel G (j, k-1), upper left pixel G
(j-1, k-1), each error data corresponding to the pixel G (j-1, k) directly above and the pixel G (j-1, k + 1) diagonally right above, that is, Error data corresponding to G (j, k-1): delayed addition signal AD ₁ pixel G (j-1, k + 1) corresponding error data: delayed addition signal AD ₃ pixel G (j-1, k) error data corresponding to: delay addition signal AD ₄ pixel G (j-1, k- 1) to the error data corresponding: delayed addition signal AD for the ₅ each, as mentioned above predetermined coefficient value K ₁ ~K ₄ The weighted addition is performed with. Next, the result of this addition is
The error data corresponding to the lower 2 or 3 bits of the first converted pixel data D _H , that is, the error data corresponding to the pixel G (j, k) is added, and the obtained 1-bit carry-out signal C _O is converted to the first bit.
The upper 6 bits of the converted pixel data _DH , that is, the data added to the display data corresponding to the pixel G (j, k) are referred to as error diffusion processed pixel data ED.

That is, the error diffusion processing circuit 330 captures the upper 6 bits of the first converted pixel data _DH as display data, and captures the remaining lower bits as error data, and obtains peripheral pixels ΔG (j, k-1). , G (j-1, k + 1), G (j-1, k), G (j-1, k-
1) The weighted sum of the error data for each is reflected in the display data. With this operation, the luminance component corresponding to the lower bits in the original pixel {G (j, k)} is pseudo-expressed by the peripheral pixels, and therefore the number of bits less than 8 bits, that is, 6 bits of display data Thus, the same brightness gradation expression as that of the 8-bit pixel data can be achieved.

If the error diffusion coefficient value is constantly added to each pixel, noise due to the error diffusion pattern may be visually recognized, thereby deteriorating the image quality. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field (frame) as in the case of the dither coefficient described later.

The dither processing circuit 350 performs dither processing on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330 to thereby obtain a luminance gradation level equivalent to that of the 6-bit error diffusion processing pixel data ED. maintained to produce a multi-gradation processing pixel data D _S which was reduced to further 4 bits the number of bits while. In the dither processing, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when gradation display corresponding to 8 bits is performed using upper 6 bits of pixel data of 8 bits of pixel data, four pixels adjacent to each other in the left, right, up, and down directions are used.
One pixel is set as one set, and four dither coefficients a to d each having a different coefficient value are assigned to each piece of pixel data corresponding to each pixel of the set and added. According to such dither processing, combinations of four different intermediate display levels occur in four pixels. Therefore, even if the number of bits of the pixel data is 6 bits, the luminance gradation level that can be expressed is four times, that is, halftone display equivalent to 8 bits is possible.

However, if the dither patterns of the dither coefficients a to d are constantly added to each pixel,
Noise due to the dither pattern may be visually recognized, and image quality may be impaired. Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to each of the four pixels for each field.

FIG. 11 is a diagram showing the internal configuration of the dither processing circuit 350. In FIG. 11, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four pixels adjacent to each other, and supplies these to the adder 351 sequentially. The dither coefficient generation circuit 352
Is in response to an input designated image signal indicated by the input image specifying signal S _V, with different values of dither coefficients a~d should occur.

[0027] That is, when the input given video signal in the input video designation signal S _V is a TV signal, Fig. 12
As shown in FIG. 5, dither coefficients a: 0, dither coefficient b: 1, dither coefficient c: 2, dither coefficient d: 3, and two-bit dither coefficients a to d are generated. In the case of a video signal, as shown in FIG. 12, dither coefficient a: 0 (or 1) dither coefficient b: 2 (or 3) dither coefficient c: 4 (or 5) dither coefficient d: 6 (or 7) Generate dither coefficients a to d each consisting of 3 bits.

Each of these dither coefficients a to d is, for example,
As shown in FIG. 13, the pixel G (j,
k) and pixel G (j, k + 1), pixel G corresponding to the (j + 1) th row
It is assigned to each of four adjacent pixels, (j + 1, k) and pixel G (j + 1, k + 1). Dither coefficient generation circuit 352
Changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, the dither coefficient generation circuit 352
In the first first field, pixel G (j, k): dither coefficient a pixel G (j, k + 1): dither coefficient b pixel G (j + 1, k): dither coefficient c pixel G (j + 1, k + 1): dither coefficient d In the following second field, pixel G (j, k): dither coefficient b pixel G (j, k + 1): dither coefficient a pixel G (j + 1, k) ): Dither coefficient d pixel G (j + 1, k + 1): dither coefficient c In the next third field, pixel G (j, k): dither coefficient d pixel G (j, k + 1): dither Coefficient c pixel G (j + 1, k): dither coefficient b pixel G (j + 1, k + 1): dither coefficient a And, in the fourth field, pixel G (j, k): dither coefficient c pixel G (j, k + 1): dither coefficient d pixel G (j + 1, k): dither coefficient a pixel G (j + 1, k + 1): dither coefficient b Are repeatedly generated and supplied to the adder 351. The dither coefficient generation circuit 352 includes the first to fourth fields as described above.
Repeat the field operation. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated. The adder 351 supplies the pixel G (j,
k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j + 1, k
+1) Each of the error diffusion processing pixel data ED corresponding thereto is added with the dither coefficients a to d assigned to each field as described above, and the obtained dither added pixel data is used as an upper bit extraction circuit. 353.

For example, in the first field shown in FIG. 17, error diffusion pixel data ED + dither coefficient a corresponding to pixel G (j, k) and error diffusion processing corresponding to pixel G (j, k + 1) Processing pixel data ED + dither coefficient b, pixel G (j
+ 1 + k), the error diffusion processing pixel data ED + dither coefficient c corresponding to the pixel G (j + 1, k + 1) and the error diffusion processing pixel data ED + dither coefficient d corresponding to the pixel G (j + 1, k + 1). It is sequentially supplied to the bit extraction circuit 353. Upper bit extracting circuit 353 extracts until the upper 4 bits of such dither-added pixel data, and outputs it as a multi-gradation pixel data D _S.

As described above, the dither processing circuit 350 shown in FIG. 9 reduces the visual noise due to the dither pattern by changing the dither coefficients a to d to be assigned to each of the four pixels for each field. seeking a multi-gradation pixel data D _S of 4 bits was also visually multi-gradation while reducing is to supply it to the second data conversion circuit 34.

The second data conversion circuit 34 converts the multi-gradation pixel data D _S of such 4-bit display drive pixel data GD is shown in Figure 14 consists of first through twelfth bits in accordance with such a conversion table . In addition, these first to first
Each of the two bits includes sub-fields SF1 to S
This corresponds to each of F12. As mentioned above, ABL
According to the data conversion circuit 30 including the circuit 31, the first data conversion circuit 32, the multi-gradation processing circuit 33, and the second data conversion circuit 34, the pixel data D capable of expressing 256 gradations with 8 bits is shown in FIG. As shown in FIG. 14, the data is converted into 12-bit display drive pixel data GD consisting of a total of 13 patterns.

The memory 5 of FIG. 2 sequentially writes and stores the display drive pixel data GD in accordance with a write signal supplied from the drive control circuit 2. With this write operation, the display drive pixel data GD for one screen (n rows and m columns)
_When the writing of _11-nm is completed, the memory 5 sequentially reads the display drive pixel data GD _11-nm with the same bit digit for each row according to the read signal supplied from the drive control circuit 2. , To the address driver 6. That is, the memory 5 stores the driving display drive pixel data GD11 _-nm for one screen of 12 bits each for each bit digit, and DB1 _11-nm : the first bit of the display drive pixel data GD11 _-nm . DB2 _11-nm: the second bit DB3 _11-nm of the display drive pixel data GD _11-nm: the third bit DB4 _11-nm of the display drive pixel data GD _11-nm: the display drive pixel data GD _11-nm of the fourth bit DB 5 _11-nm: the fifth bit DB 6 _11-nm of the display drive pixel data GD _11-nm: the sixth bit DB7 _11-nm of the display drive pixel data GD _11-nm: the display drive pixel data GD 7th bit DB8 _11-nm of _11-nm: the eighth bit DB9 _11-nm of the display drive pixel data GD _11-nm: the display drive pixel data GD _11-nm ninth bit DB10 _11-nm: display 10th bit of drive pixel data GD _11-nm DB11 _11-nm : display drive pixel data G D 11 bit DB 12 _11-nm of _11-nm: the display drive pixel data GD _11-nm as the 12th bit 12 split display drive pixel data bits DB1
_11-nm regarded as ~DB12 _11-nm, these DB
1 _11-nm , DB2 _11-nm ,..., DB12 _11-nm
In accordance with the read signal supplied from the drive control circuit 2, the data is sequentially read out for each row and supplied to the address driver 6.

The drive control circuit 2 synchronizes with the horizontal and vertical synchronizing signals in the input video signal, and controls the A / D converter 4
And a write / read signal for the memory 5 are generated. Further, the drive control circuit 2 synchronizes with the horizontal and vertical synchronization signals,
Various timing signals for driving and controlling each of the first sustain driver 7 and the second sustain driver 8 are generated.

The address driver 6 responds to the timing signal supplied from the drive control circuit 2 by using the memory 5
Display drive pixel data bits D for one row read from
B generates m pixel data pulses having voltages corresponding to the respective logic levels, and supplies them to the column electrodes D of the PDP 10.
Respectively applied to the ₁ to D _m. PDP10 is provided with the column electrodes D ₁ to D _m as address electrodes, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are arranged orthogonal to these column electrodes. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y.
That is, a first row of row electrode pairs row electrodes X ₁ and Y ₁ in the PDP 10, the n-th row of the row electrode pair row electrodes X
a _n and Y _n. The row electrode pairs and the column electrodes are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to a pixel is formed at an intersection of each row electrode pair and a column electrode.

Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with a timing signal supplied from the drive control circuit 2, and supplies these to the row electrodes of the PDP 10. X ₁ ~
Applied to X _n and Y ₁ to Y _n. 15, the address driver 6, various driving the first sustain driver 7 and second sustain driver 8 each applied PDP10 column electrodes D ₁ to D _m, row electrodes X ₁ to X _n and Y ₁ to Y _n FIG. 4 is a diagram illustrating an example of a pulse application timing.

In the example shown in FIG.
The display period of the field is set to 12 subfields SF1
The gradation driving is performed on the PDP 10 by dividing it into SF12. At this time, in each subfield, PD
The pixel data writing process Wc for setting the “light emitting cell” and “non-light emitting cell” by writing pixel data to each discharge cell of P10, and only the above “light emitting cell” is weighted for each subfield. A light emission maintaining step Ic for maintaining light emission for a corresponding period (number of times) is performed. However, only in the first subfield SF1, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is executed,
The erasing process E is performed only in the last subfield SF12.

First, in the simultaneous reset step Rc, the first sustain driver 7 and the second sustain driver 8
Each, PDP 10 row electrodes X ₁ to X _n and Y ₁ to Y _n such is shown in Figure 15 reset pulse for each RP _x
And RP _Y are applied simultaneously. These reset pulses R
In response to the application of P _x and RP _Y , all the discharge cells in the PDP 10 undergo a reset discharge, and a predetermined wall charge is uniformly formed in each discharge cell. As a result, all the discharge cells are temporarily set to the “light emitting cells”.

Next, in the pixel data writing process Wc,
Driver 6 displays the display drive supplied from the memory 5.
The voltage corresponding to the logic level of the video element data bit DB
And generates a pixel data pulse having the
Next row electrode D_1-mTo be applied. That is, first,
In the pixel data writing process Wc of the field SF1,
Display drive pixel data bit DB1_11-nmThe first line from within
Minutes corresponding to eyes, that is, DB1_11-1mExtract these
DB1_11-1mM pixels corresponding to each logic level
Pixel data pulse group DP1 composed of data pulses₁Raw
And column electrode D_1-mIs applied. Next, such a display drive
Pixel data bit DB1_11-nmCorresponds to the second row of
DB1_21-2mAnd extract these DB1_21-2meach
M pixel data pulses corresponding to various logic levels
Pixel data pulse group DP1_TwoAnd the column electrode D
_1-mIs applied. Hereinafter, similarly, the subfield S
In the pixel data writing process Wc of F1, the pixels for each row
Data pulse group DP1_Three~ DP1_nTo the column electrode D_1-mTo
Apply. Subsequently, the pixels in the subfield SF2
In the data write process Wc, first, the display drive pixel data
Data bit DB2_11-nmCorresponding to the first line from
Minutes, DB2_11-1mAnd extract these DB2_{11- 1m}each
M pixel data pulses corresponding to various logic levels
Pixel data pulse group DP2₁And the column electrode D
_1-mIs applied. Next, the display drive pixel data bit
DB2_11-nmDB corresponding to the second row of
2_21-2mAnd extract these DB2_21-2mEach logical level
Pixel data consisting of m pixel data pulses corresponding to
Tap pulse group DP2_TwoAnd the column electrode D_1-mIs applied.
Hereinafter, similarly, the pixel data of the subfield SF2 is
In the writing process Wc, the pixel data pulse group D for each row
P2_Three~ DP2_nTo the column electrode D_1-mTo be applied. Less than
Bottom, pixel data in each of subfields SF3 to SF12
Similarly, in the address writing process Wc, the address driver 6
Is the display drive pixel data bit DB3_11-nm~ DB12
_11-nmPixel data pulse group DP generated based on each
3_1-n~ DP12_1-nEach of the subfields SF3 to SF
12 and assign these to the column electrodes D_1-mApplied to
Go. Note that the address driver 6 has a display drive image.
When the logical level of the raw data bit DB is "1"
Generates a high-voltage pixel data pulse, and if it is "0"
Generates a low-voltage (0 volt) pixel data pulse
And

Further, in the pixel data writing process Wc, the second
The sustain driver 8 generates a negative-polarity scan pulse SP as shown in FIG. 15 at the same timing as each application timing of the pixel data pulse group DP as described above, and sends this to the row electrodes Y ₁ to Y _n . Are sequentially applied. At this time, discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and the discharge cell in the discharge cell Are selectively erased. That is, each of the first to twelfth bits in the display drive pixel data GD determines whether or not to cause a selective erase discharge in the pixel data writing process Wc in each of the subfields SF1 to SF12. Due to the selective erasure discharge, the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc change to “non-light emitting cells”. On the other hand, the "column" to which the low-voltage pixel data pulse was applied
No discharge is generated in the discharge cells formed in the above, and the current state is maintained. That is, the discharge cells of the “non-light emitting cells” remain “non-light emitting cells”, and the discharge cells of the “light emitting cells” are the “light emitting cells”.
Is maintained as it is. As described above, by the pixel data writing process Wc for each subfield, the “light emitting cells” in which the sustain discharge is generated in the light emission sustaining process Ic immediately thereafter and the “non-light emitting cells” in which the sustain discharge is not generated. Is set.

Next, the light emission sustaining process I of each subfield
In c, a first sustain driver 7 and second sustain driver 8 each, the row electrodes X ₁ to X _n and Y ₁ to Y _n maintained alternately as shown in FIG. 15 positive with respect to the pulse I
Applying a P _X and IP _Y. Here, the number of sustain pulses IP applied in the light emission sustaining process Ic is set in accordance with the weight of each subfield, and further, the brightness mode supplied from the data conversion circuit 30 shown in FIG. The signal LC differs depending on the type of the video signal selected as the input video signal in the input selector 3 by the signal LC.

FIG. 16 is a diagram showing the number of sustain pulses IP applied in the light emission sustain step Ic in each of the subfields SF1 to SF12 when the TV signal is selected as the input video signal. FIG. 16A shows an odd field.
When (odd frame) is displayed, FIG.
Sustain pulse I applied during (even frame) display
The number of times P is shown for each mode according to the brightness mode signal LC.

On the other hand, FIG.
When a video signal is selected, subfields SF1 to S1
It is a figure which shows the frequency | count of the sustain pulse IP which should be applied in each light emission sustaining process Ic of F12. FIG. 17A shows the number of sustain pulses IP applied during display of odd fields (odd frames) and FIG. 17B shows display of even fields (even frames) in accordance with the brightness mode signal LC. This is shown for each mode.

For example, when each of the input video specifying signal S _V for specifying the TV signal and the luminance mode signal LC indicating the luminance mode 1 is supplied as the input video signal, the drive control circuit 2 returns to FIG. As shown, various timing signals for performing operations according to the light emission drive sequence are supplied to the address driver 6, the first sustain driver 7, and the second sustain driver 8, respectively.

FIG. 18A shows a light emission drive sequence executed when displaying an odd field (odd frame), and FIG. 18B shows a light emission driving sequence executed when displaying an even field (even frame). That is, the video signal designated as input is T
In the case of the V signal and the luminance mode 1, the ratio of the number of times of the sustain pulse IP applied in the light emission sustaining process Ic of each of the subfields SF1 to SF12 is such that when the odd field (odd frame) is displayed, FIG. ), SF1: 2 SF2: 2 SF3: 6 SF4: 8 SF5: 11 SF6: 17 SF7: 22 SF8: 28 SF9: 35 SF10: 43 SF11: 51 SF12: 30 and the even field (even frame) When) is displayed,
As shown in FIG. 18B, SF1: 1 SF2: 2 SF3: 4 SF4: 6 SF5: 10 SF6: 14 SF7: 19 SF8: 25 SF9: 31 SF10: 39 SF11: 47 SF12: 57.

On the other hand, when an input video designating signal S _V for designating a PC video signal and a luminance mode signal LC indicating a luminance mode 1 are supplied as input video signals, the drive control circuit 2 shown in FIG. As described above, various timing signals for performing operations according to the light emission drive sequence are supplied to each of the address driver 6, the first sustain driver 7, and the second sustain driver 8.

FIG. 19A shows a light emission driving sequence executed when displaying an odd field (odd frame), and FIG. 19B shows a light emission driving sequence executed when displaying an even field (even frame). That is, when the input video signal is a PC video signal and in the luminance mode 1, the frequency ratio of the sustain pulse IP applied in the light emission sustaining process Ic of each of the subfields SF1 to SF12 is the odd field (odd frame). At the time of display, as shown in FIG. 19A, SF1: 1 SF2: 2 SF3: 4 SF4: 7 SF5: 11 SF6: 14 SF7: 20 SF8: 25 SF9: 33 SF10: 40 SF11: 48 SF12: 50 When displaying an even field (even frame),
As shown in FIG. 19B, SF1: 1 SF2: 2 SF3: 4 SF4: 6 SF5: 10 SF6: 14 SF7: 19 SF8: 25 SF9: 31 SF10: 39 SF11: 47 SF12: 57.

At this time, the subfields SF1 to SF1
12, the frequency ratio of the sustain pulse IP applied is nonlinear (that is, the inverse gamma ratio, Y = X ² , ² ), whereby the nonlinear characteristic (gamma characteristic) previously applied to the input video signal is reduced. I am trying to correct it. In each of the subfields SF1 to SF12, the number of subfields responsible for low-luminance light emission is greater than the number of subfields responsible for high-luminance light emission. That is, the sustain pulse I
The number of subfields responsible for relatively low-luminance light emission in which the number of times of application of P is 25 or less is eight from SF1 to SF8, and subfields SF9 to SF12 responsible for high-luminance light emission.
More than the number of.

Then, the last subfield SF12
The erasing process E is executed only by the above. In the erase process E, the address driver 6, which column electrodes D _1-m to generate but such positive polarity erase pulse AP shown in FIG. 15
Is applied. Further, the second sustain driver 8 generates a negative-polarity erase pulse EP as shown in FIG. 15 at the same time as the application timing of the erase pulse AP, and applies this to each of the row electrodes Y _{1 to} Y _n . These erase pulses AP
By the simultaneous application of EP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, due to the erase discharge, all the discharge cells in the PDP 10 are "
It becomes a "non-light emitting cell".

Here, in each of the subfields shown in FIG. 18 or FIG.
Only the discharge cells set as “light emitting cells” maintain the light emitting state by repeating the sustain discharge by the number of times as described above in the light emission sustaining step Ic performed immediately thereafter. Whether the discharge cell is set to “light emitting cell” or “non-light emitting cell” for each subfield is determined by the display drive pixel data GD as shown in FIG.
Depends on That is, each of the first to twelfth bits of the display drive pixel data GD corresponds to the subfield SF1.
To SF12, and only when the logic level of the bit is, for example, the logic level "1", the pixel data writing process W of the subfield corresponding to the bit digit
At c, a selective erase discharge is generated, and the discharge cells are set to "non-light emitting cells". On the other hand, when the logical level of the bit is the logical level "0", the current state is maintained because the selective erase discharge is not generated. In other words, the discharge cells of the “non-light-emitting cells” remain “non-light-emitting cells”, and the discharge cells of the “light-emitting cells” maintain the state of the “light-emitting cells”. At this time, of the subfields SF1 to SF12,
The opportunity to change the discharge cell from the “non-light-emitting cell” state to the “light-emitting cell” depends on whether the first sub-field SF1
Is only the reset step Rc. Therefore, after the completion of the reset process Rc, the subfields SF1 to SF12
In a pixel data writing process Wc of any one of the above, a discharge cell which has been temporarily changed to a "non-light emitting cell" due to the occurrence of a selective erase discharge is changed to a "light emitting cell" again in this field. Absent. Therefore, according to the data pattern of the display drive pixel data GD as shown in FIG. 14, each discharge cell is "light emitting cell" only until a selective erase discharge is generated in a subfield indicated by a black circle in FIG. The sustain discharge is performed as many times as described above in the light emission sustaining process Ic of each of the sub-fields indicated by the white circles existing therebetween.

Thus, when the input video signal is a TV signal and the luminance mode is 1, as shown in FIG. 14, when an odd field (odd frame) is displayed,
｛0: 2: 4: 10: 18: 29: 46: 68: 96: 131: 174: 225:
A gradation drive having a luminance expression of 13 gradations of 255｝ is performed, and when an even field (even frame) is displayed,
｛0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 2
A gradation drive having a luminance expression for 13 gradations of 55 ° is performed.

FIG. 20 is a diagram showing a correspondence relationship between an input video signal and a display luminance of an image actually displayed on the PDP 10 according to the input video signal when the input video signal is a TV signal. It is. In FIG. 20, "□" indicates
The grayscale luminance point “、” obtained by the grayscale driving according to the light emission driving sequence as shown in FIG.
FIG. 8B shows the gradation luminance points obtained by gradation driving according to the light emission driving sequence as shown in FIG.

As shown in FIG. 20, when the input video signal is a TV signal, the light emission drive sequence as shown in FIGS.
The switching is performed alternately for each frame. According to such driving, a gray-scale luminance point obtained in the other light-emitting drive sequence is added to the middle of two gray-scale luminance points obtained in one light-emitting drive sequence.

In FIG. 20, the gradation luminance points adjacent to each other, that is, the luminance between "□" and "◇" are determined by multi-gradation processing such as error diffusion processing and dither processing as described above. Obtained by FIG. 21 shows a region E in FIG.
In FIG. 1, the gradation luminance point (“□”) obtained by the light emission drive sequence shown in FIG. 18A and the gradation luminance point (“◇”) obtained by the light emission drive sequence shown in FIG. ")When,
FIG. 9 is a diagram illustrating a positional relationship between a tone luminance point (“●”) obtained by an error diffusion process and a tone luminance point (“■”) obtained by a dither process.

At this time, as shown in FIG. 21, a part (“■”) of each of the gray-scale luminance points obtained in a pseudo manner by the dither processing is obtained by comparing FIG. 18 (A) and FIG. 18 (B). The same luminance level as the gradation luminance point (“□”) obtained by performing the light emission drive sequence shown in FIG. Therefore, TV
For an input video signal having a relatively low S / N such as a signal, a flicker is suppressed by an integration effect in a time direction, and a pseudo increase in the number of gray scales by the error diffusion processing and the dither processing is performed while reducing dither noise. It is planned.

On the other hand, when the input video signal is a PC video signal having a relatively good S / N, as shown in FIG. 14, when displaying an odd field (odd frame), ｛0:
1: 3: 7: 14: 25: 39: 59: 84: 117: 157: 205: 255｝
The gradation drive having a luminance expression of 13 gradations is performed.
When an even field (even frame) is displayed, ｛0: 1:
A gradation drive having a luminance expression of 13 gradations of 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 255 is performed.

FIG. 22 is a diagram showing a correspondence relationship between the input video signal and the display luminance of an image displayed on the PDP 10 according to the input video signal when the input video signal is the PC video signal. It is. In FIG. 22, "□"
Is a gradation luminance point obtained by gradation driving according to a light emission driving sequence as shown in FIG.
Each of the grayscale luminance points obtained by the grayscale drive according to the light emission drive sequence as shown in FIG.

As shown in FIG. 22, when the input video signal is a PC video signal, as shown in FIGS. 19A and 19B for each field (one frame),
The light emission driving sequence in which the gray scale luminance points are slightly shifted from each other is alternately performed. According to such driving,
A gradation luminance point obtained by the other light emission driving sequence is added to a position near one gradation luminance point between two gradation luminance points obtained by one light emission driving sequence.

In FIG. 22, the luminance other than the luminance indicated by the gradation luminance points “□” and “◇” can be obtained by the multiple gradation processing such as the error diffusion processing and the dither processing as described above. FIG. 23 shows the gradation luminance points (“□”) obtained in the light emission drive sequence shown in FIG. 19A and the light emission drive sequence shown in FIG. 19B in the area E2 in FIG. It shows the positional relationship between the obtained gradation luminance point (")"), the gradation luminance point ("●") obtained by the error diffusion processing, and the gradation luminance point (")") obtained by the dither processing. FIG.

As described above, when a PC video signal is designated for input, 3-bit dither coefficients a to d (a = 0, b = 2, c) as shown in FIG. = 4, d
= 6) is used, and as shown in FIG. 23, the distribution of each gradation luminance point obtained by the error diffusion processing has unevenness. Therefore, as shown in FIG. 23, each of the tone luminance points obtained by the error diffusion processing and the dither processing in a pseudo manner, and the light emission driving sequence as shown in FIGS. 19 (A) and 19 (B). Is different from each of the grayscale luminance points obtained by the above operation.

Therefore, due to the integration effect in the time direction, the number of gray scales to be visually displayed is determined by the light emission drive sequence shown in FIG. 18 (ie, the light emission drive sequence used when a TV signal is specified as an input video signal). Is almost doubled as compared with the case where is adopted. That is, when a video signal having a relatively good S / N such as a PC video signal is input and specified, the pseudo grayscale luminance point obtained by the error diffusion processing and the dither processing is calculated as shown in FIG. 19
By shifting the gradation luminance point obtained by performing the light emission drive sequence as shown in FIG. 4B, the number of pseudo gradations is greatly increased.

In the above-described embodiment, as a method of writing pixel data, all discharge cells are set as light emitting cells by forming wall charges in each discharge cell in advance, and then selective according to the pixel data. The case where a so-called selective erase address method of writing pixel data by erasing the wall charges, has been described. However,
The present invention can be similarly applied to a case where a so-called selective write address method in which wall charges are selectively formed according to pixel data as a method of writing pixel data.

FIG. 24 shows that each of the address driver 6, the first sustain driver 7 and the second sustain driver 8 uses the PDP when this selective write address method is adopted.
10 column electrodes D ₁ to D _m of a diagram showing an example of application timing of various drive pulses applied to the row electrodes X ₁ to X _n and Y ₁ to Y _n. FIG. 25 is a diagram showing a light emission drive sequence executed when a TV signal is designated as an input video signal when the selective write address method is adopted.
FIG. 6 is a diagram showing a light emission drive sequence performed when a PC video signal is designated. FIGS. 25A and 26A each show the display of an odd field (odd frame).
FIGS. 25 (B) and 26 (B) each show a light emission drive sequence which is performed when an even field (even frame) is displayed.

FIG. 27 shows a conversion table used in the second data conversion circuit 34 shown in FIG. 6 and a light emission drive performed within one field period when such a selective write address method is employed. It is a figure showing all patterns. Here, as shown in FIG. 24, when the selective write address method is adopted, first, in the simultaneous reset process Rc in the first subfield SF12, the first sustain driver 7 and the second sustain driver 8 are used. simultaneously applying a respective reset pulses RP _x and RP _Y to PDP10 the row electrodes X and Y. This allows
Reset discharge all the discharge cells in the PDP 10;
A wall charge is forcibly formed in each discharge cell (R ₁ ).
Immediately thereafter, the first sustain driver 7, by applying simultaneously the erase pulse EP to the PDP10 in the row electrode X ₁ to X _n, thereby erasing the wall charges formed in all the discharge cells (R ₂₎ . That is, according to the execution of the simultaneous reset process Rc as shown in FIG. 24, all the discharge cells in the PDP 10 are temporarily initialized to the state of “non-light emitting cell”.

Next, in the pixel data writing process Wc,
Driver 6 displays the display drive supplied from the memory 5.
The voltage corresponding to the logic level of the video element data bit DB
And generates a pixel data pulse having the
Next row electrode D_1-mTo be applied. That is, first,
In the pixel data writing process Wc of the field SF12,
Display drive pixel data bit DB12_11-nmFrom the
The amount corresponding to the first line, that is, DB12_11-1mExtract
These DB12_11-1mM corresponding to each logic level
Pixel data pulse group DP composed of pixel data pulses
12₁And the column electrode D_1-mIs applied. Then take
Display drive pixel data bit DB12_11-nm2nd row in
DB12 which corresponds to the eyes_21-2mExtract these
DB12_{twenty one- 2m}M images corresponding to each logic level
Pixel data pulse group DP12 composed of elementary data pulses_Two
And the column electrode D_1-mIs applied. The same applies to the following
The pixel data writing process Wc of the subfield SF12.
, The pixel data pulse group DP12 for each row_Three~ D
P12_nTo the column electrode D_1-mTo be applied. Continued
In the pixel data writing process Wc of the subfield SF11
First, the display drive pixel data bit DB11
_11-nm, The portion corresponding to the first line, that is, DB11
_{11- 1m}And extract these DB11_11-1mEach logical level
Pixel data consisting of m pixel data pulses corresponding to
Tapulse group DP11₁And the column electrode D_1-mApplied to
You. Next, the display drive pixel data bit DB11
_11-nmDB11 corresponding to the second row of_21-2m
And extract these DB11_21-2mFor each logical level
Pixel data pulse consisting of m pixel data pulses corresponding to
Luth group DP11_TwoAnd the column electrode D_1-mIs applied. Less than
Below, similarly, the pixel data of the subfield SF11
In the writing process Wc, the pixel data pulse group D for each row
P11_Three~ DP11_nTo the column electrode D_1-mApplied to the line
Good. Hereinafter, the image in each of the subfields SF10 to SF1 will be described.
Similarly, in the raw data writing process Wc, the address
The driver 6 has a display drive pixel data bit DB10_11-nm~
DB1_11-nmPixel data pulse generated based on each
Group DP10_1-n~ DP1_1-nEach subfield SF1
0 to SF1, each of which is assigned to a column electrode D_1-mMark on
Add them. The address driver 6 displays
When the logic level of the drive pixel data bit DB is "1"
In this case, a high-voltage pixel data pulse is generated and is "0".
In this case, a low voltage (0 volt) pixel data pulse is generated.
Shall be.

Further, in the pixel data writing process Wc, the second
The sustain driver 8 generates a negative-polarity scan pulse SP as shown in FIG. 246 at the same timing as each application timing of the pixel data pulse group DP as described above, and sends this to the row electrodes Y ₁ to Y _n . Are sequentially applied. At this time, discharge (selective write discharge) occurs only in the discharge cell at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and the discharge cell A wall charge is selectively formed in the inside. Due to the selective writing discharge, the discharge cells initialized to the “non-light emitting cell” state in the simultaneous reset process Rc change to the “light emitting cell”. On the other hand, the selective writing discharge is not generated in the discharge cells formed in the "column" to which the low-voltage pixel data pulse is applied, and the current state is maintained. In other words, the discharge cells of the “non-light-emitting cells” remain “non-light-emitting cells”, and the discharge cells of the “light-emitting cells” maintain the state of the “light-emitting cells”. As described above, by the pixel data writing process Wc for each subfield, the “light emitting cells” in which the sustain discharge is generated in the light emission sustaining process Ic immediately thereafter and the “non-light emitting cells” in which the sustain discharge is not generated. Is set.

Next, the light emission sustaining process I of each subfield
In c, a first sustain driver 7 and second sustain driver 8 each, the row electrodes X ₁ to X _n and Y ₁ to Y _n maintained alternately as shown in FIG. 24 positive with respect to the pulse I
Applying a P _X and IP _Y. At this time, the number of sustain pulses IP to be applied in the light emission sustaining process Ic of each subfield differs according to the type of the video signal selected as the input video signal, as shown in FIG. 25 or FIG.

Then, as shown in FIG. 24, when the selective writing address method is adopted, the erasing step E is executed only in the last subfield SF1. In the erase process E, the address driver 6 simultaneously applies the row electrodes Y ₁ to Y _n respectively which generates a but such negative erase pulse EP of shown in Figure 24. By the simultaneous application of the erasing pulse EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells disappear. That is, by such an erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.

Here, in the pixel data writing process Wc in each subfield shown in FIG. 25 or FIG.
Only the discharge cells set as "light-emitting cells" repeat the sustain discharge as many times as described in the figure in the light-emission sustaining step Ic performed immediately thereafter, and maintain the light-emitting state. Whether the cell is set to “light emitting cell” or “non-light emitting cell” in the data writing process Wc of each subfield is determined by the display drive pixel data GD as shown in FIG. Each of the first to twelfth bits of the drive pixel data GD corresponds to each of the subfields SF1 to SF12, and only when the logical level of the bit is, for example, the logical level “1”, the subbit corresponding to the bit digit is set. The selective write discharge as described above is generated in the pixel data write step Wc of the field, and the discharge cell is set to the "light emitting cell." Is a logical level "0", the selective writing discharge does not occur as described above, so that the current state is maintained, that is, the "non-light-emitting cell" discharge cell remains "non-light-emitting cell" and "light-emitting". The discharge cell "cell" maintains the state of the "light-emitting cell" as it is, in this case, in the subfields SF12 to SF1, the discharge cell is changed from the state of the "light-emitting cell" to the "non-light-emitting cell". Is possible only in the reset step Rc in the first sub-field SF12, and after the reset step Rc, any one of the sub-fields SF12 to SF1 is completed.
In the pixel data writing process Wc, the selective writing discharge is generated, and the discharge cell once changed to the “light emitting cell” does not change to the “non-light emitting cell” again in this field. Therefore, according to the display drive pixel data GD shown in FIG. 27, each discharge cell remains in the “non-light emitting cell” state until the selective write discharge occurs in the subfield indicated by the black circle in FIG. The sustain discharge is repeated by the number of times described in FIG. 25 or FIG. 26 in the light emission sustaining process Ic of each subfield after the black circle, and the discharge light emission state is maintained.

As a result, when the input video signal is a TV signal and in the luminance mode 1, as shown in FIG. 27, when an odd field (odd frame) is displayed,
｛0: 2: 4: 10: 18: 29: 46: 68: 96: 131: 174: 225:
A gradation drive having a luminance expression of 13 gradations of 255｝ is performed, and when an even field (even frame) is displayed,
｛0: 1: 3: 7: 13: 23: 37: 56: 81: 112: 151: 198: 2
A gradation drive having a luminance expression for 13 gradations of 55 ° is performed.

On the other hand, when the input video signal is a PC video signal, as shown in FIG.
At the time of (odd frame) display, ｛0: 1: 3: 7: 14: 25: 3
9: 59: 84: 117: 157: 205: 255, which is a gradation drive having a luminance expression for 13 gradations, and when displaying an even field (even frame), {0: 1: 3: 7: 13. : 23: 37: 5
6: 81: 112: 151: 198: 255, which is a gradation drive having a luminance expression for 13 gradations.

At this time, the luminance expression by the gradation driving is the same as that in the case where the above-described selective erase address method is employed as the pixel data writing method. Therefore, even when the selective write address method is employed, the number of pseudo gray levels is appropriately increased in accordance with the type of the input and designated video signal, as in the case where the selective erase address method is employed. .

In the above embodiment, in the pixel data writing process Wc of any one of the subfields SF1 to SF12, the selective erasing (writing) is performed by simultaneously applying the scanning pulse SP and the high voltage pixel data pulse. Discharge), but if the amount of charged particles remaining in the discharge cells is small, this selective erasing (writing) discharge will not be generated normally, and the wall charges in the discharge cells will not be generated normally. It may not be possible to erase (form). At this time, even if the pixel data D after the A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, and there is a problem that image quality is significantly reduced.

Therefore, the conversion table used in the second data conversion circuit 34 is changed from those shown in FIGS. 14 and 27 to those shown in FIGS. 28 and 29, and gradation driving is performed. FIG. 28 is a diagram showing a conversion table used in the second data conversion circuit 34 when the selective erasure address method is adopted, and a light emission driving pattern executed within one field period. FIG. FIG. 4 is a diagram showing the conversion table and the light emission drive pattern when the embedded address method is adopted. Here, “*” shown in FIGS. 28 and 29 indicates the logical level “1” or “1”.
0 "indicates that it is acceptable, and a triangle indicates such a"
* Selected erase (write) only when "" is logic level "1"
This indicates that a discharge occurs.

According to the display drive pixel data GD shown in FIGS. 28 and 29, at least two consecutive "selective erase (write) discharges" are performed. In short, since the writing of pixel data may fail in the first selective erasing (writing) discharge, the selective erasing (writing) discharge is performed again in at least one of the subfields existing thereafter. By doing so, the writing of pixel data is ensured, and an erroneous light emission operation is prevented.

[0076]

As described above in detail, in the driving method of the plasma display panel according to the present invention, the light emission performed in each of the light emission sustaining steps during one field (one frame) according to the type of the input video signal. The first and second light emission drive sequences having different numbers of times are performed in one field.
A first drive pattern that is alternately executed every (one frame) and a third and a fourth light emission drive sequence in which the ratio of the number of times of light emission performed in each of the light emission sustaining steps is different from each other for each field (one frame) One of the second drive patterns that are alternately switched and executed is selectively executed.

At this time, when the type of the input video signal is a TV signal, by selectively executing the first drive pattern, the gradation luminance point obtained by the first light emission drive sequence and At the time of execution of the second light emission driving sequence, the same luminance level is set to a gradation luminance point which is simulated by multi-gradation processing such as error diffusion and dither processing. On the other hand, when the type of the input video signal is a PC video signal, by selectively executing the second drive pattern, the gradation luminance point obtained by the third light emission drive sequence and the fourth light emission drive sequence are output. At the time of execution of the drive sequence, the luminance level is set to be different from the gray level luminance point which is obtained in a pseudo manner by the multi-gradation processing such as the error diffusion and the dither processing.

Therefore, in the case of performing display based on a video signal having a relatively low S / N such as a TV signal, it is necessary to suppress the occurrence of flicker and noise due to dither, and to perform various operations such as error diffusion and dither processing. The number of pseudo gradations can be increased by the gradation processing. On the other hand, in the case of performing display based on a video signal having a relatively good S / N such as a PC video signal, the number of gray levels obtained by the multiple gray level processing such as the error diffusion and dither processing is substantially reduced. It can be increased by a factor of two.

[Brief description of the drawings]

FIG. 1 is a diagram showing a light emission drive sequence for performing 64-tone halftone display.

FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.

FIG. 3 is a diagram showing an internal configuration of a data conversion circuit 30.

FIG. 4 is a diagram showing an internal configuration of an ABL circuit 31;

FIG. 5 is a diagram illustrating conversion characteristics in a data conversion circuit 312.

FIG. 6 is a diagram showing an internal configuration of a first data conversion circuit 32.

FIG. 7 is a diagram showing data conversion characteristics used in a first data conversion circuit 32 when a TV signal is input and designated;

FIG. 8 is a diagram showing data conversion characteristics used in a first data conversion circuit 32 when a PC video signal is designated to be input.

FIG. 9 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

FIG. 10 is a diagram for explaining the operation of the error diffusion processing circuit 330.

FIG. 11 is a diagram showing an internal configuration of a dither processing circuit 350.

FIG. 12 is a diagram illustrating values of dither coefficients a to d for each type of input video signal.

FIG. 13 is a diagram for explaining the operation of the dither processing circuit 350;

FIG. 14 is a diagram showing a conversion table of a second data conversion circuit, and a light emission drive pattern and display luminance based on display drive pixel data GD obtained by the conversion table.

FIG. 15 is a diagram showing application timings of various drive pulses applied to the PDP within one field display period when the selective erase address method is adopted.

FIG. 16 is a diagram showing a correspondence relationship between each luminance mode and the number of times of applying the sustain pulse IP in the light emission sustaining process Ic of each of the subfields SF1 to SF12 when a TV signal is input and designated.

FIG. 17 is a diagram showing a correspondence relationship between a luminance mode and the number of times of application of a sustain pulse IP in a light emission sustaining process Ic of each of subfields SF1 to SF12 when a PC video signal is designated to be input.

FIG. 18 is a diagram illustrating an example of a light emission drive sequence performed when a TV signal is designated to be input.

FIG. 19 is a diagram showing an example of a light emission drive sequence performed when a PC video signal is designated to be input.

FIG. 20 is a diagram illustrating a display luminance characteristic with respect to an input video signal when a TV signal is designated to be input;

FIG. 21 shows an area E1 in FIG.
FIG. 9 is a diagram showing a positional relationship between each gradation luminance point obtained by the light emission drive sequence shown in FIG. 8 and each gradation luminance point obtained by error diffusion processing and dither processing.

FIG. 22 is a diagram illustrating a display luminance characteristic with respect to an input video signal when a PC video signal is designated to be input.

FIG. 23 shows an area E2 in FIG.
FIG. 10 is a diagram showing a positional relationship between each gradation luminance point obtained by the light emission drive sequence shown in FIG. 9 and each gradation luminance point obtained by error diffusion processing and dither processing.

FIG. 24 is a diagram showing application timings of various drive pulses applied to the PDP within one field display period when the selective write address method is adopted.

FIG. 25 is a diagram showing a light emission driving sequence (selective writing address method is adopted) performed when the input designated video signal is a TV signal.

FIG. 26 is a diagram showing a light emission driving sequence (using a selective writing address method) performed when an input and designated video signal is a PC video signal.

FIG. 27 shows a conversion table of a second data conversion circuit used when the selective write address method is adopted, and display drive pixel data GD obtained by the conversion table.
FIG. 5 is a diagram showing a light emission drive pattern and display luminance according to the following.

FIG. 28 shows another example of the conversion table of the second data conversion circuit 34 used when the selective erase address method is adopted, and the light emission drive pattern and display corresponding to the display drive pixel data GD obtained by this conversion table. It is a figure which shows a brightness | luminance.

FIG. 29 shows another example of the conversion table of the second data conversion circuit used when the selective write address method is adopted, and the light emission drive pattern corresponding to the display drive pixel data GD obtained by the conversion table. It is a figure which shows display luminance.

[Explanation of Signs of Main Parts]

 REFERENCE SIGNS LIST 1 operation device 2 drive control circuit 3 input selector 6 address driver 7 first sustain driver 8 second sustain driver 10 PDP 30 data conversion circuit 31 ABL circuit 31 32 first data conversion circuit 33 multi-gradation processing circuit 34 second data Conversion circuit 330 Error diffusion processing circuit 350 Dither processing circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 101 H04N 5/66 101B F-term (Reference) 5C058 AA11 AB02 BA03 BA07 BB03 BB13 BB15 5C080 AA05 BB05 DD03 EE29 FF12 GG08 GG09 HH02 JJ02 JJ04 JJ05

Claims (23)

[Claims] 1. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a display panel, comprising: dividing a unit display period into N divided display periods, and performing N-bit display driving by performing multi-gradation processing on an input video signal in each of the divided display periods. A pixel data writing step of setting each of the discharge cells as a non-light-emitting cell or a light-emitting cell in accordance with pixel data, and light-emitting in which only the light-emitting cells emit light the number of times corresponding to the weight of each of the divided display periods And a light emission drive sequence for performing a sustain step. The light emission drive sequence includes first and second light emission driving ratios different from each other in the sustain light emission step in each of the N divided display periods. A first driving pattern in which each of the two light emission driving sequences is alternately switched for each unit display period and a third driving pattern in which the ratio of the number of times of light emission in the sustaining light emission process in each of the N divided display periods is different. And a second drive pattern that alternately switches and executes each of the fourth light emission drive sequences for each unit display period, and selects the first drive pattern and the second drive pattern according to the type of the input video signal. A method for driving a plasma display panel, wherein the method is performed integrally. 2. The method according to claim 1, wherein the input video signal is a video signal from a personal computer or a television signal. 3. The method according to claim 1, wherein the unit display period is one field or one frame display period of the input video signal. 4. A luminance level at each gradation luminance point obtained by executing the first light emission driving sequence, and a luminance at each gradation luminance point obtained by the multi-gradation processing when executing the second light emission driving sequence. The brightness level of each gradation luminance point obtained by executing the third light emission drive sequence, and the luminance level of each gradation luminance point obtained by performing the multi-gradation processing when executing the fourth light emission drive sequence. 2. The method according to claim 1, wherein the brightness levels are different from each other. 5. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a display panel, comprising: dividing a unit display period into N divided display periods, and performing N-bit display driving by performing multi-gradation processing on an input video signal in each of the divided display periods. A pixel data writing step of setting each of the discharge cells as a non-light-emitting cell or a light-emitting cell in accordance with pixel data, and light-emitting in which only the light-emitting cells emit light the number of times corresponding to the weight of each of the divided display periods And a light emission drive sequence for performing a sustain step. The light emission drive sequence includes first and second light emission driving ratios different from each other in the sustain light emission step in each of the N divided display periods. A two-light emission driving sequence, wherein a luminance level of each gradation luminance point obtained by performing the first light emission driving sequence and a gradation level obtained by the multi-gradation processing at the time of executing the second light emission driving sequence. And a brightness level of the same. 6. The method according to claim 5, wherein the input video signal is a television signal. 7. The method according to claim 5, wherein the unit display period is one field or one frame display period of the input video signal. 8. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a display panel, comprising: dividing a unit display period into N divided display periods, and performing N-bit display driving by performing multi-gradation processing on an input video signal in each of the divided display periods. A pixel data writing step of setting each of the discharge cells as a non-light-emitting cell or a light-emitting cell in accordance with pixel data, and light-emitting in which only the light-emitting cells emit light the number of times corresponding to the weight of each of the divided display periods And a light emission drive sequence for performing a sustain step. The light emission drive sequence includes first and second light emission driving ratios different from each other in the sustain light emission step in each of the N divided display periods. A two-light emission driving sequence, wherein a luminance level of each gradation luminance point obtained by performing the first light emission driving sequence and a gradation level obtained by the multi-gradation processing at the time of executing the second light emission driving sequence. And a luminance level of the plasma display panel. 9. The method according to claim 8, wherein the input video signal is a video signal from a personal computer. 10. The method according to claim 8, wherein the unit display period is one field or one frame display period of the input video signal. 11. The non-linear display characteristic of the input video signal is corrected by setting the ratio of the number of times of light emission in the light emission sustaining step in each of the divided display periods to be non-linear. Driving method of a plasma display panel. 12. The method according to claim 11, wherein the non-linear display characteristic is a gamma characteristic. 13. The method according to claim 11, wherein the multi-gradation processing is performed before correcting the non-linear display characteristic of the input video signal. 14. The plasma according to claim 1, wherein the multi-gradation processing includes error diffusion processing and / or dither processing, and a dither coefficient in the dither processing is changed for each unit display period. Display panel driving method. 15. A method for separating pixel data corresponding to the input video signal at a bit boundary between an upper bit group and a lower bit group required for the multi-gradation processing before performing the multi-gradation processing. The method of driving a plasma display panel according to claim 1, wherein: 16. A reset process for initializing all of the discharge cells to one of a light-emitting cell and a non-light-emitting cell only in the divided display period at the head of the unit display period, 2. The discharge cell is set to one of a non-light emitting cell and a light emitting cell according to the display drive pixel data only in any one of the pixel data writing processes in a display period. Driving method of a plasma display panel. 17. A reset process for initializing all of the discharge cells to one of a light emitting cell and a non-light emitting cell only in the divided display period at the head of the unit display period, First pixel data for generating a discharge for setting the discharge cells to one of the non-light-emitting cells or the light-emitting cells in accordance with the display drive pixel data in any one of the pixel data writing steps in a display period; A pulse is applied to the column electrode, and a second pixel data pulse identical to the first pixel data pulse is applied to the column electrode in the pixel data writing process in the divided display period immediately after the pulse. The method of driving a plasma display panel according to claim 1, wherein: 18. The erasing step according to claim 16, wherein an erasing step for setting all the discharge cells to the non-light emitting cells only in the last divided display period of the unit display period is provided. A method for driving a plasma display panel. 19. In the reset step, all the discharge cells are initialized to the state of the light emitting cells, and in the pixel data writing step, the discharge cells are selectively erased and discharged according to the display drive pixel data. 18. The method according to claim 1, wherein the discharge cell is set as the non-light emitting cell by the following. 20. In the reset step, all the discharge cells are initialized to the state of the non-light emitting cells, and in the pixel data writing step, the discharge cells are selectively written and discharged according to the display drive pixel data. 18. The method according to claim 1, wherein the discharge cell is set as the light-emitting cell by causing the light-emitting cell to emit light. 21. N + 1 gray scale driving by causing the light emitting cells to emit light only in the light emission sustaining step in each of n (n is 0 to N) continuous divided display periods from the beginning of the unit display period. 20. The method of driving a plasma display panel according to claim 1, wherein the driving is performed. 22. An N + 1 gray scale by causing the light emitting cells to emit light only in the light emission sustaining process in each of n (n is 0 to N) divided display periods continuing from the end of the unit display period. 21. The method of driving a plasma display panel according to claim 1, wherein the driving is performed. 23. In each of the divided display periods arranged in the unit display period, the number of divided display periods carrying low luminance light emission is larger than the number of divided display periods carrying high luminance light emission. The method for driving a plasma display panel according to claim 21 or 22.