JP4071382B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
[0002]
  The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).
[Prior art]
[0003]
  In recent years, with the increase in size of display devices, thin display devices are required, and various thin display devices have been put into practical use. An AC (alternating discharge) type PDP has attracted attention as one of such thin display devices.
[0004]
  The AC-type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs that are arranged orthogonally to the column electrodes and form one scan line as a pair. Each of these row electrode pairs and column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .
[0005]
  At this time, since the PDP uses a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, the subfield method is used in order to realize halftone luminance display by such PDP. In the subfield method, a display period of one field is divided into N subfields, and a light emission period having a period length corresponding to the weighting of each bit digit of pixel data (N bits) is assigned to each subfield. The light emission is driven.
[0006]
  FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus that performs halftone luminance display using such a subfield method.
[0007]
  In FIG. 1, a driving apparatus 100 converts an input video signal into digital pixel data corresponding to each pixel, and a pixel data pulse corresponding to this pixel data is converted to a column electrode D of the PDP 10.₁~ D_mAnd various drive pulses as described below are applied to the row electrode X.₁~ X_nAnd Y₁~ Y_nTo control the light emission drive. The row electrodes X and Y constitute one row of the PDP 10 as a pair, and the column electrode D₁~ D_mIt is formed to cross each other. These column electrode and row electrode pairs are formed with a dielectric (not shown) interposed therebetween, and one pixel cell is formed at a portion where one set of column electrode and row electrode pair intersects.
[0008]
  FIG. 2 is a diagram showing an example of a light emission driving format in one field period by the driving device 100. In FIG.
[0009]
  As shown in FIG. 2, the display period of one field is divided into four subfields, subfields SF1 to SF4. In each subfield, simultaneous reset process Rc, pixel data writing process Wc, and light emission maintenance are performed. The process Ic and the erase process E are executed.
[0010]
  FIG. 3 is a diagram showing application timings (within one subfield) of various drive pulses applied by the driving apparatus 100 to the column electrode and row electrode pairs of the PDP 10 in order to carry out these processes.
[0011]
  First, in the simultaneous reset process Rc, the driving device 100 performs a negative reset pulse RP as shown in FIG._xAnd positive reset pulse RP_YRow electrode X₁~ X_nAnd Y₁~ Y_nApply to each simultaneously. These reset pulses RP_xAnd RP_YIn response to the application, all the discharge cells in the PDP 10 are reset and discharged, and a predetermined amount of wall charges are uniformly formed in each discharge cell. Thereby, all the discharge cells are initially set to “light emitting cells”.
[0012]
  Next, in the pixel data writing process Wc, as shown in FIG. 3, the driving device 100 performs the pixel data pulse group DP for each row.₁~ DP_nSequentially column electrode D₁~ D_mApply to. For example, in the pixel data writing process Wc of the subfield SF1, only the first bit is extracted from each of the input pixel data corresponding to all the discharge cells of the PDP 10, and the pixel data corresponding to the logic level of the first bit The pulse group DP is sequentially switched to the column electrode D for each row.₁~ D_mApply to. In the subfield SF2, only the second bit is extracted from each input pixel data corresponding to each of all the discharge cells of the PDP 10, and the pixel data pulse group DP corresponding to the logic level of the second bit is set to one row. Sequential column electrode D every minute₁~ D_mIt is applied to. At this time, when the logical level of the pixel data is “1”, for example, the driving device 100 generates a high-voltage pixel data pulse and applies it to the column electrode D, while the logical level of the pixel data. When “0” is “0”, a pixel data pulse of a low voltage (for example, 0 volts) is applied to the column electrode D. Further, the driving device 100 generates a scanning pulse SP having a negative polarity as shown in FIG. 3 at the same timing as the application timing of the pixel data pulse group DP.₁~ Y_nApply sequentially to. Here, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining inside are selectively erased. Due to the selective erasing discharge, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc is changed to the “non-light emitting cell”. On the other hand, the selective erasure discharge is not generated in the discharge cells to which the low-voltage pixel data pulse is applied simultaneously with the scanning pulse SP, and is initialized in the simultaneous reset process Rc, that is, the “light emitting cell”. The state of is maintained.
[0013]
  Next, in the light emission sustaining step Ic, the driving device 100 performs the sustain pulse IP as shown in FIG._XAnd IP_YRow electrode X₁~ X_nAnd Y₁~ Y_nAre applied alternately. Here, in each subfield, sustain pulse IP_XAnd IP_YThe number of times (period) to apply is set corresponding to the weighting of each subfield.
[0014]
  For example, as shown in FIG.
            SF1: 1
            SF2: 2
            SF3: 4
            SF4: 8
  Sustain pulse IP at the number of times (period) ratio_XAnd IP_YIs continuously applied.
[0015]
  At this time, only the discharge cells in which the wall charges remain after the completion of the pixel data writing step Wc, that is, the “light emitting cells”, are supplied to these sustain pulses IP._XAnd IP_YEach time is alternately applied, discharge light is emitted, and the light emission state is maintained for the number of times (period) as described above.
[0016]
  Next, in the erasing step E, the driving device 100 applies an erasing pulse EP as shown in FIG.₁~ X_nBy applying the voltage to, all the discharge cells are erased and discharged all at once, and the wall charges remaining in each discharge cell are erased.
[0017]
  FIG. 4 is a diagram illustrating all patterns of light emission driving performed within one field period by driving using the subfield method described above.
[0018]
  For example, when a video signal (corresponding to pixel data “1110”) for displaying the discharge cell with luminance “8” is supplied, light emission is performed only in SF4 among the subfields SF1 to SF4. Specifically, in the pixel data writing process Wc of each of the subfields SF1 to SF3, a selective erasing discharge is generated by applying a high voltage pixel data pulse simultaneously with the scanning pulse SP, and is formed in the discharge cell. Eliminate wall charges. Thus, in the light emission sustaining process Ic of each of the subfields SF1 to SF3, the sustain pulse IP_XAnd IP_YHowever, sustain discharge is not generated. That is, the subfields SF1 to SF3 are in a non-light emitting state. On the other hand, in the pixel data writing process Wc of the subfield SF4, a low-voltage pixel data pulse is applied simultaneously with the scanning pulse SP. Thus, when the pixel data pulse is at a low voltage, even if the scanning pulse SP is applied at the same time, the selective erasing discharge does not occur, and the wall charge formed in the discharge cell remains. . Thus, in the light emission sustaining process Ic of the subfield SF4, the sustain pulse IP_XAnd IP_YEach time is applied, a sustain discharge accompanied by light emission is generated for the number of times of application (period), that is, “8” times (period). Accordingly, light emission occurs for the number of times (period) of “8” throughout the period of one field of subfields SF1 to SF4, and display corresponding to luminance “8” is performed.
[0019]
  However, the driving method as described above has a problem that the power consumption becomes high because various driving pulses as shown in FIG. 3 must be periodically applied regardless of the contents to be displayed. It was.
[Problems to be solved by the invention]
[0020]
  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a plasma display panel driving method capable of reducing power consumption.
[Means for Solving the Problems]
[0021]
  The plasma display panel driving method according to claim 1 forms a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes. A driving method of a plasma display panel, wherein a display period of one field is divided into N subfields, and in each of the subfields, a scan pulse is sequentially applied to each of the row electrodes and the scan pulse Each of the discharge cells is selected by applying each pixel data pulse having a voltage corresponding to the logic level of each row of pixel data to each of the column electrodes in synchronism with each application timing. Pixel data writing process in which each discharge cell is set to either a light-emitting cell or a non-light-emitting cell by being discharged, and in each of the subfields Perform a light emission sustain process for discharging only the light emitting cells by the amount of the number of times by only sustain pulse number of times response is applied to the row electrodes,A reset process for initializing each of the discharge cells to one of the light emitting cells and the non-light emitting cells by discharging all the discharge cells only in the first subfield of the N subfields. Run,In the pixel data writing process, for each row electrode, it is determined whether or not all the logic levels of the pixel data for one row corresponding to the row electrode match a predetermined level. The application of the scan pulse is stopped only in the row electrode where it is determined that all the logical levels of the pixel data match the predetermined level., By selectively discharging the discharge cells according to the pixel data in the pixel data writing process in any one of the N subfields, the discharge cells emit light. The selective discharge is caused to occur again in the pixel data writing process in the subfield immediately after the subfield in which the selective discharge is caused.The
  According to a second aspect of the present invention, there is provided a plasma display panel driving method in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes. A method for driving a plasma display panel, wherein a display period of one field is divided into N subfields, and a scan pulse is sequentially applied to each of the row electrodes in each of the subfields. By applying each pixel data pulse having a voltage corresponding to the logic level of each row of pixel data to each of the column electrodes in synchronization with the application timing of each scan pulse, each of the discharge cells. A pixel data writing step of selectively discharging each of the discharge cells to set either one of the light emitting cells or the non-light emitting cells, and each of the subfields M number of the only light emitting cells running, and light emission sustain process which amount corresponding discharging of the number of the N number of said sub-fields by applying only sustain pulse number corresponding to the row electrode ( 2 ≦ M ≦ N ) The subfields arranged continuously are defined as subfield groups, and all the discharge cells are discharged only in the first subfield of the subfield group, whereby each of the discharge cells is changed to the light emitting cell or the non-light emitting cell. A reset process that is initialized to one of the states is executed, and in the pixel data writing process, for each row electrode, all of the logical levels of the pixel data for one row corresponding to the row electrode are set to a predetermined level. And the application of the scan pulse is stopped only for the row electrodes determined that all of the logical levels of the pixel data for one row match the predetermined level, In the pixel data writing process in any one of the subfields in the subfield group, the pixel data is selectively selected according to the pixel data. By selectively discharging the discharge cells, each of the discharge cells is set to either the light emitting cell or the non-light emitting cell, and the pixel data document in the subfield immediately after the subfield in which the selective discharge is generated The selective discharge is caused again in the charging process.
  According to a third aspect of the present invention, there is provided a plasma display panel driving method in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes. A method for driving a plasma display panel, wherein a display period of one field is divided into N subfields, and a scan pulse is sequentially applied to each of the row electrodes in each of the subfields. Synchronized with the application timing of each scan pulse Then, each of the discharge cells is selectively discharged by applying each pixel data pulse having a voltage corresponding to the logic level of each row of pixel data to each of the column electrodes for each row. A pixel data writing process in which each cell is set to either a light emitting cell or a non-light emitting cell, and a sustain pulse is applied to the row electrode for the number of times corresponding to each of the subfields, whereby only the light emitting cell is set to the number of times. A light emission sustaining step of discharging only the amount of N, and dividing the N sub-fields into sub-field groups each consisting of a plurality of sub-fields, each of which is continuously arranged. By discharging all the discharge cells only in the subfield, each of the discharge cells is changed to either the light emitting cell or the non-light emitting cell. A reset process that initializes to one state is executed, and in the pixel data writing process, for each row electrode, all the logical levels of the pixel data for one row corresponding to the row electrode are equal to a predetermined level. And the application of the scan pulse is stopped only for the row electrodes for which it is determined that all the logical levels of the pixel data for one row match the predetermined level, In the pixel data writing process in any one of the subfields in a field group, the discharge cells are selectively discharged according to the pixel data, thereby causing each of the discharge cells to be the light emitting cell or the non-emitting cell. In the pixel data writing process in the subfield immediately after the subfield in which the selective discharge is caused, the light emitting cell is set to one of the states. Again it allowed to rise to the selective discharge.
[0022]
  Embodiments of the present invention will be described below with reference to the drawings.
[0023]
  FIG. 5 is a diagram showing a schematic configuration of a plasma display apparatus that drives a plasma display panel to emit light based on the driving method according to the present invention.
[0024]
  As shown in FIG. 5, the plasma display device is composed of a PDP 10 as a plasma display panel and various functional modules that drive the plasma display panel.
[0025]
  The PDP 10 includes m column electrodes D as address electrodes.₁~ D_mAnd n number of row electrodes X arranged crossing each of these column electrodes.₁~ X_nAnd row electrode Y₁~ Y_nIt has. A pair of the row electrode X and the row electrode Y forms a row electrode corresponding to one row in the PDP 10. The column electrode D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode. Yes.
[0026]
  The A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from the drive control circuit 2 and converts it into, for example, 8-bit pixel data (input pixel data) D for each pixel. The data is converted and supplied to the data conversion circuit 30. The data conversion circuit 30 converts the 8-bit pixel data D into 14-bit conversion pixel data HD, which is converted into each of the memory 4, the non-selected row determination circuit 51, and the non-light emitting SF (subfield) determination circuit 52. Supply. The detailed operations of the data conversion circuit 30, the non-selected row determination circuit 51, and the non-light emitting SF determination circuit 52 will be described later.
[0027]
  The memory 4 sequentially writes the converted pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When writing for one screen (n rows, m columns) in the PDP 10 is completed by such a writing operation, the memory 4 stores the converted pixel data HD for one screen in accordance with the read signal supplied from the drive control circuit 2._11-nmFor each bit digit, i.e.
          DB1_11-nm: Conversion pixel data HD_11-nm1st bit of
          DB2_11-nm: Conversion pixel data HD_11-nm2nd bit of
          DB3_11-nm: Conversion pixel data HD_11-nmThe third bit of
          DB4_11-nm: Conversion pixel data HD_11-nm4th bit of
          DB5_11-nm: Conversion pixel data HD_11-nm5th bit of
          DB6_11-nm: Conversion pixel data HD_11-nm6th bit of
          DB7_11-nm: Conversion pixel data HD_11-nm7th bit of
          DB8_11-nm: Conversion pixel data HD_11-nm8th bit of
          DB9_11-nm: Conversion pixel data HD_11-nm9th bit of
          DB10_11-nm: Conversion pixel data HD_11-nm10th bit of
          DB11_11-nm: Conversion pixel data HD_11-nm11th bit of
          DB12_11-nm: Conversion pixel data HD_11-nm12th bit of
          DB13_11-nm: Conversion pixel data HD_11-nm13th bit of
          DB14_11-nm: Conversion pixel data HD_11-nm14th bit of
  These DB1 are divided_11-nm, DB2_11-nm..., DB14_11-nmEach of them is sequentially read for each row and supplied to the address driver 6.
[0028]
  The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the video signal input as described above. Further, the drive control circuit 2 addresses various timing signals to drive and control the PDP 10 in accordance with the light emission drive format shown in FIG. 6 in consideration of various determination signals from the non-selected row determination circuit 51 and the non-light emission SF determination circuit 52. This is supplied to the driver 6, the first sustain driver 7 and the second sustain driver 8, respectively. As shown in FIG. 6, the drive control circuit 2 controls the drive of the PDP 10 by dividing the display period of one field into 14 subfields SF1 to SF14. At this time, in each subfield, pixel data writing process Wc in which pixel data is written to each discharge cell of the PDP 10 to set “light emitting cell” and non-light emitting cell, and the above “light emitting cell”. 6 is performed for the number of times (periods) shown in Fig. 6 to perform a light emission sustaining step Ic for maintaining the light emission state, and in only the first subfield SF1, the discharge in all the discharge cells of the PDP 10 is performed. The simultaneous reset process Rc for initializing the wall charge amount is executed, and the erase process E for erasing the wall charges in all the discharge cells at the same time is executed only in the last subfield SF14.
[0029]
  The address driver 6, the first sustain driver 7, and the second sustain driver 8 each of the PDP 10 in order to realize the above-described operations in the simultaneous reset process Rc, the pixel data write process Wc, the light emission sustain process Ic, and the erase process E. Column electrode D₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nVarious drive pulses are applied to each.
[0030]
  FIG. 7 is a diagram illustrating an example of the application timing of such drive pulses.
[0031]
  First, in the simultaneous reset process Rc of the subfield SF1, the first sustain driver 7 and the second sustain driver 8 perform a negative reset pulse RP._xAnd positive reset pulse RP_YRow electrode X₁~ X_nAnd Y₁~ Y_nAre applied simultaneously. These reset pulses RP_xAnd RP_YAs a result, all discharge cells in the PDP 10 are reset and discharged, and predetermined wall charges are uniformly formed in each discharge cell. As a result, all discharge cells in the PDP 10 are temporarily set to “light emitting cells” once.
[0032]
  Next, in the pixel data writing process Wc of the subfield SF1, the address driver 6 receives the DB1 supplied from the memory as described above._11-nmA pixel data pulse having a voltage corresponding to each logic level is generated, and this is sequentially applied to the column electrode D for each row._1-mApply to. That is, first, the DB1_11-nmThe portion corresponding to the first line from that, that is, DB1_11-1mAnd extract these DB1_11-1mPixel data pulse group DP1 consisting of m pixel data pulses corresponding to each logic level₁And the column electrode D as shown in FIG._1-mAre applied simultaneously. Next, DB1_11-nmDB1 corresponding to the second row of_21-2mAnd extract these DB1_21-2mPixel data pulse group DP1 consisting of m pixel data pulses corresponding to each logic level₂To generate a column electrode D_1-mAre applied simultaneously. Hereinafter, similarly, pixel data pulse group DP1 for each row_Three~ DP1_nSequentially column electrode D_1-mApply to. The address driver 6 generates a high-voltage pixel data pulse when the logical level of DB1 is “1”, for example, and low voltage (0 volts) when the logical level of DB1 is “0”. It is assumed that the pixel data pulse is generated.
[0033]
  In the pixel data writing process Wc of the subfield SF2, the address driver 6 receives the DB2 supplied from the memory as described above._11-nmFrom each, a pixel data pulse having a voltage corresponding to the logic level is generated, and this is sequentially applied to the column electrode D every row._1-mApply to. That is, first, the DB2_11-nmThe amount corresponding to the first line from the inside, that is, DB2_11-1mAnd extract these DB2_11-1mPixel data pulse group DP2 consisting of m pixel data pulses corresponding to each logic level₁And these are converted into column electrodes D as shown in FIG._1-mAre applied simultaneously. Next, DB2_11-nmDB2 corresponding to the second row of_21-2mAnd extract these DB2_21-2mPixel data pulse group DP2 consisting of m pixel data pulses corresponding to each logic level₂Are generated and the column electrodes D_1-mAre applied simultaneously. Hereinafter, similarly, pixel data pulse group DP2 for each row_Three~ DP2_nSequentially column electrode D_1-mApply to.
[0034]
  In the pixel data writing process Wc in each of the subfields SF3 to SF14, the address driver 6 also applies DB3 in the same manner as described above._11-nm~ DB14_11-nmPixel data pulse group DP3 from each_1-n~ DP14_1-nAre generated, and these are sequentially applied to the column electrode D for each row._1-mApply to.
[0035]
  Here, the second sustain driver 8 generates a scanning pulse SP having a negative polarity as shown in FIG. 7 at the same timing as each application timing of the pixel data pulse group DP as described above, and outputs this to the row electrode Y.₁~ Y_nApply sequentially to. At this time, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining in are selectively erased. That is, the logic level of each bit (first bit to 14th bit) in the converted pixel data HD determines whether or not to perform selective erasure discharge in the pixel data writing process Wc in each of the subfields SF1 to SF14. It is doing. Due to the selective erasing discharge, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc is changed to the “non-light emitting cell”. Note that no discharge is generated in the discharge cells formed in the “column” to which the high-voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the “light emitting cell”. The state of is maintained.
[0036]
  That is, when each pixel data writing process Wc is executed, in the light emission sustaining process cI immediately after that, a “light emitting cell” in which a sustain discharge accompanied by light emission occurs as described later, and no sustain discharge occurs and no light emission occurs. The remaining “non-light emitting cells” are alternatively set according to the pixel data, and so-called pixel data is written to each discharge cell.
[0037]
  In the light emission sustaining process Ic executed in each of the subfields SF1 to SF14, the first sustain driver 7 and the second sustain driver 8 are connected to the row electrode X.₁~ X_nAnd Y₁~ Y_nIn contrast, as shown in FIG._XAnd IP_YApply. Here, the number of sustain pulses IP applied in the light emission sustain process Ic of each subfield is:
                SF1: 1
                SF2: 3
                SF3: 5
                SF4: 8
                SF5: 10
                SF6: 13
                SF7: 16
                SF8: 19
                SF9: 22
                SF10: 25
                SF11: 28
                SF12: 32
                SF13: 35
                SF14: 39
  It is.
[0038]
  By applying the sustain pulse, a discharge cell in which wall charges remain in the pixel data writing process Wc, that is, a “light emitting cell”_XAnd IP_YEach time is applied, sustain discharge is performed, and the discharge light emission state is maintained for the number of times (period). At this time, the ratio of the number of sustain discharges to be executed in each of the subfields SF1 to SF14 is set to a non-linear (that is, inverse gamma ratio, Y = X^2.2Thus, the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
[0039]
  Further, as shown in FIG. 4, in the erasing step E in the last subfield, the address driver 6 generates an erasing pulse AP and supplies it to the column electrode D._1-mTo each of the above. The second sustain driver 8 generates an erase pulse EP simultaneously with the application timing of the erase pulse AP, and generates the erase pulse EP.₁~ Y_nApply to each. By simultaneously applying these erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, by this erasing discharge, all the discharge cells in the PDP 10 become non- “light emitting cells”.
[0040]
  Here, the non-selected row discriminating circuit 51 in FIG. 5 performs the conversion pixel data HD for one screen._11-nmBased on the above, a “row” (hereinafter referred to as a non-selected row) in which no selective erasing discharge is generated is discriminated, and a non-selected row discriminating signal NS indicating each non-selected row is supplied to the drive control circuit 2. For example, the non-selected row discriminating circuit 51 generates the converted pixel data HD._11-nmDB1 for each bit digit_11-nm, DB2_11-nm, DB3_11-nm..., DB14_11-nmAs shown in FIG. 14, the sub-fields SF1 to SF14 are assigned to the respective subfields SF1 to SF14. For each subfield, the logical levels of the data bits for one row corresponding to the first to mth columns in the DB are all "0". The “row” is a non-selected row. Note that, when this non-selected row does not exist, the non-selected row determination circuit 51 supplies the drive control circuit 2 with a non-selected row determination signal NS of level “0”. When the non-selected row determination signal NS is at level “0”, the drive control circuit 2 applies a negative scan pulse SP to the row electrode Y as shown in FIG.₁~ Y_nScan pulse timing signals to be sequentially applied to the second sustain driver 8 are supplied. On the other hand, when the non-selected row determination signal NS indicates the presence of the non-selected row, the scan pulse timing signal for stopping the application of the scan pulse SP is applied only to the non-selected row. Supply to the driver 8.
[0041]
  FIG. 8 is a diagram illustrating an example of application timings of various drive pulses in one field when such non-selected rows exist.
[0042]
  In FIG. 8, the converted pixel data HD_11-nmDB1 consisting of the first bit of_11-nmThe amount corresponding to the second line in the middle, that is, DB1_21-2mAll the bits of the signal are at the logic level “0”, and the converted pixel data HD_11-nmDB2 consisting of the second bit of_11-nmThe portion corresponding to the nth row in the middle, that is, DB2_n1-nmThis shows a case where all the bits of are at logic level “0”.
[0043]
  Thus, DB1_21-2mWhen all the bits in FIG. 5 are at the logic level “0”, the address driver 6 causes the pixel data pulse group in which all of them become low voltage (0 volts) in the pixel data writing process Wc in the subfield SF1 shown in FIG. DP1₂Column electrode D_1-mWill be applied. DB2_n1-nmWhen all the bits of are at the logic level “0”, the address driver 6 causes the pixel data pulse group DP2 to be all at a low voltage (0 volt) in the pixel data writing process Wc in the subfield SF2._nColumn electrode D_1-mWill be applied. At this time, if the pixel data pulse group DP is at a low voltage as described above, even if the scan pulse SP is applied, the selective erasing discharge is not generated.
[0044]
  Therefore, in the non-selected row discriminating circuit 51, the “row” in which no selective erasing discharge is generated in any of the first column to the m-th column, that is, the non-selected row is converted into the converted pixel data HD._11-nmIn this case, the application of the scan pulse SP is stopped for this non-selected row, as shown in the second row of SF1 and the nth row of SF2 in FIG. It was.
[0045]
  Therefore, the power consumption can be suppressed by the amount that the application of the scan pulse SP is stopped.
[0046]
  Further, the non-light emitting SF discriminating circuit 52 of FIG._11-nmBased on the above, in the light emission sustaining process Ic for each subfield, a subfield in which all the discharge cells for one screen are in a non-light emission state (hereinafter referred to as non-light emission SF) is determined, and the non-light emission SF indicating the non-light emission SF is determined. The light emission SF discrimination signal NL is supplied to the drive control circuit 2. When the non-light-emitting SF does not exist, the non-light-emitting SF determination circuit 52 supplies a non-light-emitting SF determination signal NL of level “0” to the drive control circuit 2. When the non-light emitting SF discriminating signal NL is at the level “0”, the drive control circuit 2 performs positive sustain pulse IP as shown in FIGS._XAnd IP_YAre supplied to the first sustain driver 7 and the second sustain driver 8 as sustain pulse timing signals to be applied to the row electrodes X and Y alternately. On the other hand, when the non-light emitting SF determination signal NL indicates the presence of the non-light emitting SF, the sustain pulse IP is applied only to the light emission sustaining process Ic of the subfield indicated by the non-light emitting SF._XAnd IP_YIs supplied to the first sustain driver 7 and the second sustain driver 8.
[0047]
  FIG. 9 is a diagram illustrating an example of application timings of various drive pulses when the non-light-emitting SF is the subfield SF14.
[0048]
  As described above, when the non-light emitting SF discriminating circuit 52 determines that the subfield in which all the discharge cells do not emit light is SF 14, the first sustain driver 7 and the second sustain driver 8 are shown in FIG. As shown in the figure, the sustain pulse IP is applied only to the light emission sustain process Ic of the subfield SF14._XAnd IP_YThe application of is stopped.
[0049]
  Therefore, sustain pulse IP_XAnd IP_YTherefore, the power consumption can be suppressed by the amount not applied.
[0050]
  FIG. 10 is a diagram showing all the patterns of light emission driving performed based on the light emission driving format as shown in FIG.
[0051]
  As shown in FIG. 10, selective erasing discharge is performed on each discharge cell only in the pixel data writing process Wc in one of the subfields SF1 to SF14 (indicated by black circles). . That is, the wall charges formed in all the discharge cells of the PDP 10 by performing the simultaneous reset process Rc remain until the selective erasing discharge is performed, and the light emission sustaining process in each subfield SF existing in the meantime. In Ic, the sustain discharge accompanied by light emission is promoted (indicated by white circles). That is, each discharge cell becomes a “light emitting cell” until the selective erasing discharge is performed within one field period, and the light emission sustaining process Ic in each subfield existing between them is shown in FIG. The light emission is repeated for the number of times.
[0052]
  At this time, as shown in FIG. 10, the number of times each discharge cell transitions from the “light emitting cell” to the “non-light emitting cell” is always less than or equal to one within one field period. That is, a light emission drive pattern that once resets a discharge cell set to a non- “light emitting cell” to a “light emitting cell” again within one field period is prohibited.
[0053]
  Therefore, the above-described simultaneous reset operation accompanied by strong light emission regardless of image display need only be performed once within one field period as shown in FIGS. Can be suppressed.
[0054]
  In addition, since the selective erasing discharge performed in one field period is one time as shown by the black circles in FIG. 10, each subfield in which this selective erasing discharge is performed and each subfield existing thereafter In the light emission sustaining step Ic, the discharge cell is in a non-light emitting state.
[0055]
  Therefore, the non-light emitting SF discriminating circuit 52 performs the conversion pixel data HD for one screen._11-nmWhen a non-light-emitting SF in which all discharge cells for one screen are in a non-light-emitting state is detected based on the above, a subfield indicated by the non-light-emitting SF and all subfields existing thereafter are The non-light emitting SF discrimination signal NL indicating the above may be supplied to the drive control circuit 2.
[0056]
  Here, according to the light emission drive pattern as shown in FIG.
    {0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 256}
  This makes it possible to express halftones in 15 levels
[0057]
  However, the pixel data D supplied from the A / D converter 1 expresses 8 bits, that is, 256 halftones.
[0058]
  Therefore, data conversion is performed by the data conversion circuit 30 shown in FIG. 2 in order to realize halftone display close to 256 levels even by the 15 levels of gradation driving.
[0059]
  FIG. 11 is a diagram showing an internal configuration of the data conversion circuit 30. As shown in FIG.
[0060]
  In FIG. 11, an ABL (automatic brightness control) circuit 31 is sequentially supplied from the A / D converter 1 so that the average brightness of the image displayed on the screen of the PDP 10 is within a predetermined brightness range. The brightness level is adjusted for the pixel data D for each pixel, and the brightness adjustment pixel data D obtained at this time is adjusted._BLIs supplied to the first data conversion circuit 32.
[0061]
  The luminance level is adjusted before the inverse gamma correction is performed by setting the ratio of the number of times of light emission in each subfield to be nonlinear as will be described later. Therefore, the ABL circuit 31 is configured to perform inverse gamma correction on the pixel data D and automatically adjust the luminance level of the pixel data D according to the average luminance of the inverse gamma conversion pixel data obtained at this time. . As a result, display quality deterioration due to brightness adjustment is prevented.
[0062]
  FIG. 12 is a diagram showing an internal configuration of the ABL circuit 31. As shown in FIG.
[0063]
  In FIG. 12, the level adjustment circuit 310 adjusts the brightness adjustment pixel data D obtained by adjusting the level of the pixel data D according to the average brightness obtained by the average brightness detection circuit 311 described later._BLIs output. The data conversion circuit 312 receives the brightness adjustment pixel data D_BLAs shown in FIG. 13, the inverse gamma characteristic (Y = X^2.2) Is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, in the data conversion circuit 312, the brightness adjustment pixel data D_BLBy applying inverse gamma correction to the pixel data, pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal for which the gamma correction has been canceled is restored.
[0064]
  The average luminance detection circuit 311 designates the light emission period in each subfield. For example, as shown in FIG. 14, the average luminance detection circuit 311 emits the PDP 10 with luminance according to the average luminance obtained as described above. A luminance mode that can be driven is selected, and a luminance mode signal LC indicating the selected luminance mode is supplied to the drive control circuit 2. At this time, the drive control circuit 2 shows the number of sustain discharges in the light emission sustaining process Ic of each of the subfields SF1 to SF14 shown in FIG. 6, that is, the number of sustain pulses to be applied in each light emission sustaining process Ic. 14 is set according to the mode specified by the luminance mode signal LC. That is, the number of times of light emission in each subfield shown in FIG. 6 indicates the number of times of light emission when the luminance mode 1 is set. If the luminance mode 2 is set,
                SF1: 2
                SF2: 6
                SF3: 10
                SF4: 16
                SF5: 20
                SF6: 26
                SF7: 32
                SF8: 38
                SF9: 44
                SF10: 50
                SF11: 56
                SF12: 64
                SF13: 70
                SF14: 78
  At a certain number of times, the sustain discharge is performed in the light emission sustain process Ic of each subfield.
[0065]
  Even in such light emission driving, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2Thus, the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
[0066]
  The average luminance detection circuit 311 obtains the average luminance from the inverse gamma conversion pixel data Dr and supplies it to the level adjustment circuit 310.
[0067]
  Here, the first data conversion circuit 32 in FIG. 11 has 256 gradation (8 bits) luminance adjustment pixel data D based on the conversion characteristics as shown in FIG._BLIs converted to 14 × 16/255 (224/255) 8-bit (0-224) conversion pixel data HD_pAnd converted to the multi-gradation processing circuit 33. Specifically, 8-bit (0 to 255) luminance adjustment pixel data D_BL16 and 17 based on such conversion characteristics are converted in accordance with a conversion table as shown in FIGS. That is, this conversion characteristic is set according to the number of bits of input pixel data, the number of compression bits by multi-gradation, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit 33 to be described later, and the conversion is performed according to the display gradation number and the compression bit number by the multi-gradation, thereby adjusting the luminance. Pixel data D_BLThe upper bit group (corresponding to multi-gradation pixel data) and the lower bit group (data to be discarded: error data) are separated at bit boundaries, and multi-gradation processing is performed based on this signal. As a result, it is possible to prevent the occurrence of luminance saturation due to the multi-gradation processing and the occurrence of a flat portion of display characteristics (that is, the occurrence of gradation distortion) that occurs when the display gradation is not at the bit boundary.
[0068]
  Since the lower bit group is discarded, the number of gradations decreases. However, the decrease in the number of gradations can be obtained in a pseudo manner by the operation of the multi-gradation processing circuit 33 described below. ing.
[0069]
  FIG. 18 is a diagram showing an internal configuration of the multi-gradation processing circuit 33. As shown in FIG.
[0070]
  As shown in FIG. 18, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.
[0071]
  First, the data separation circuit 331 in the error diffusion processing circuit 330 receives the 8-bit converted pixel data HD supplied from the first data conversion circuit 32._PThe lower 2 bits are separated as error data, and the upper 6 bits are separated as display data.
[0072]
  The adder 332 converts the converted pixel data HD as the error data._PAn addition value obtained by adding the lower two bits in the middle, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 is supplied to the delay circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and delays the addition value AD.₁Are supplied to the coefficient multiplier 335 and the delay circuit 337, respectively.
[0073]
  The coefficient multiplier 335 receives the delay addition signal AD.₁The predetermined coefficient value K₁A multiplication result obtained by multiplying (for example, “7/16”) is supplied to the adder 332.
[0074]
  The delay circuit 337 receives the delay addition signal AD.₁Is further delayed by a time of (1 horizontal scanning period−the delay time D × 4).₂To the delay circuit 338. The delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D to obtain a delayed addition signal AD_ThreeAs a coefficient multiplier 339. In addition, the delay circuit 338 receives the delayed addition signal AD.₂Is further delayed by the delay time D × 2 to obtain a delayed addition signal AD_FourIs supplied to the coefficient multiplier 340. Further, the delay circuit 338 receives the delayed addition signal AD.₂Is obtained by delaying the delay time D × 3 by the delay time signal D × 3._FiveIs supplied to the coefficient multiplier 341.
[0075]
  The coefficient multiplier 339 outputs the delayed addition signal AD_ThreeThe predetermined coefficient value K₂The multiplication result obtained by multiplying (for example, “3/16”) is supplied to the adder 342. The coefficient multiplier 340 receives the delayed addition signal AD._FourThe predetermined coefficient value K_ThreeThe multiplication result obtained by multiplying (for example, “5/16”) is supplied to the adder 342. The coefficient multiplier 341 receives the delayed addition signal AD._FiveThe predetermined coefficient value K_FourThe multiplication result obtained by multiplying (for example, “1/16”) is supplied to the adder 342.
[0076]
  The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 outputs the error data (converted pixel data HD)._P(The lower two bits in the middle), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335 are added. At this time, when there is no carry, there is a logic level "0" and a carry. In this case, a carry-out signal C with a logic level "1"_OIs generated and supplied to the adder 333.
[0077]
  The adder 333 receives the display data (converted pixel data HD)._PIn the upper 6 bits), the above carry-out signal C_OIs added as 6-bit error diffusion processed pixel data ED.
[0078]
  The operation of the error diffusion processing circuit 330 having such a configuration will be described below.
[0079]
  For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 19, first, the pixel G (j, k) on the left side of the pixel G (j, k) is first obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Each error data corresponding to each, that is,
        Error data corresponding to pixel G (j, k-1): delayed addition signal AD₁
         Error data corresponding to pixel G (j-1, k + 1): delayed addition signal AD_Three
         Error data corresponding to pixel G (j-1, k): delayed addition signal AD_Four
        Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD_Five
  Each is represented by a predetermined coefficient value K as described above.₁~ K_FourIs weighted and added. Next, the conversion pixel data HD is added to the addition result._PThe error data corresponding to the lower 2 bits of the pixel, that is, the pixel G (j, k) is added, and the carrier-out signal C for 1 bit obtained at this time is added._OConvert pixel data HD_PThe upper 6 bits, that is, the display data corresponding to the pixel G (j, k) is added to the display data corresponding to the pixel G (j, k) as error diffusion processing pixel data ED.
[0080]
  With this configuration, the error diffusion processing circuit 330 converts the converted pixel data HD._PThe upper 6 bits are displayed as display data, and the remaining lower 2 bits are regarded as error data. The peripheral pixels {G (j, k-1), G (j-1, k + 1), G (j-1 , k) and G (j−1, k−1)} are weighted and added to the display data. By this operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is expressed in a pseudo manner by the peripheral pixels, and therefore the number of bits is smaller than 8 bits, that is, the display data is 6 bits. Thus, luminance gradation equivalent to the 8-bit pixel data can be expressed.
[0081]
  If this error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Therefore, the error diffusion coefficient K to be assigned to each of the four pixels as in the case of the dither coefficient described later.₁~ K_FourMay be changed for each field.
[0082]
  The dither processing circuit 350 performs a dither process on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to the 6-bit error diffusion processing pixel data ED. Multi-gradation processing pixel data D with the number of bits further reduced to 4 bits_SIs generated. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.
[0083]
  However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.
[0084]
  Therefore, in the dither processing circuit 350, the dither coefficients a to d to be assigned to each of the four pixels are changed for each field.
[0085]
  FIG. 20 is a diagram showing an internal configuration of the dither processing circuit 350. As shown in FIG.
[0086]
  In FIG. 20, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351.
[0087]
  For example, as shown in FIG. 21, the pixel G (j, k) and pixel G (j, k + 1) corresponding to the jth row and the pixel G (j + 1, k) corresponding to the (j + 1) th row ) And four dither coefficients a, b, c and d corresponding to the four pixels G (j + 1, k + 1), respectively. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.
[0088]
  That is, in the first first field,
              Pixel G (j, k): Dither coefficient a
              Pixel G (j, k + 1): Dither coefficient b
              Pixel G (j + 1, k): Dither coefficient c
              Pixel G (j + 1, k + 1): Dither coefficient d
  In the next second field,
              Pixel G (j, k): Dither coefficient b
              Pixel G (j, k + 1): Dither coefficient a
              Pixel G (j + 1, k): Dither coefficient d
              Pixel G (j + 1, k + 1): Dither coefficient c
  In the next third field,
              Pixel G (j, k): Dither coefficient d
              Pixel G (j, k + 1): Dither coefficient c
              Pixel G (j + 1, k): Dither coefficient b
              Pixel G (j + 1, k + 1): Dither coefficient a
  And in the fourth field,
              Pixel G (j, k): Dither coefficient c
              Pixel G (j, k + 1): Dither coefficient d
              Pixel G (j + 1, k): Dither coefficient a
              Pixel G (j + 1, k + 1): Dither coefficient b
  The dither coefficients a to d are repeatedly generated by the assignment as described above and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.
[0089]
  The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each, and the dither coefficients a to d assigned to each field as described above are added, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.
[0090]
  For example, in the first field shown in FIG.
       Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
       Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
       Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
       Each of the error diffusion processing pixel data ED + dither coefficient d corresponding to the pixel G (j + 1, k + 1) is sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data.
[0091]
  The upper bit extraction circuit 353 extracts up to the upper 4 bits of the dither addition pixel data, and converts this to the multi-gradation pixel data D_STo the second data conversion circuit 34 shown in FIG.
Supply.
[0092]
  The second data conversion circuit 34 provides the multi-gradation pixel data D_SIs converted into converted pixel data HD composed of first to fourteenth bits corresponding to each of the subfields SF1 to SF14 in accordance with a conversion table as shown in FIG. Multi-gradation pixel data D_SConverts the 8-bit (256 gradations) input pixel data D into 224/225 according to the first data conversion (conversion tables in FIGS. 16 and 17), and further, for example, multi-gradation such as error diffusion processing and dither processing. By the conversion process, 2 bits are compressed and converted into data of a total of 4 bits (15 gradations). Here, among the first to 14th bits in the converted pixel data HD, the bit having the logic level “1” causes the selective erasure discharge in the pixel data writing process Wc in the subfield SF corresponding to the bit. Is shown.
[0093]
  According to the operation of the data conversion circuit 30 as described above, as shown in FIG. 10, even with 15 levels of gradation driving, the actual visual gradation expression approaches 256 gradations.
[0094]
  As described above, in the present invention, the non-selected row discriminating circuit 51 and the non-light emitting SF discriminating circuit 52 use the pixel data (conversion pixel data) as the “row” that does not cause the selective erasing discharge and the subfield that does not cause the sustain discharge. HD). Here, the application of the scan pulse SP is stopped for the “row” determined not to cause the selective erasure discharge, and the sustain pulse IP is applied to the subfield determined not to generate the sustain discharge. By stopping, power consumption is reduced.
[0095]
  In the above embodiment, as a pixel data writing method, wall charges are forcibly formed in advance in each discharge cell at the beginning of one field, and all discharge cells are set to “light emitting cells”. The case where the so-called selective erasure address method is adopted, in which pixel data is written by selectively erasing the wall charges according to data, has been described.
[0096]
  However, the present invention can be similarly applied to a case where a so-called selective write addressing method in which wall charges are selectively formed according to pixel data as a pixel data writing method.
[0097]
  FIG. 22 is a diagram showing a light emission drive format when such a selective write address method is employed.
[0098]
  FIG. 23 is a diagram showing a conversion table used in the second data conversion circuit 34 when the selective write address method is adopted, and all the patterns of light emission driving performed within one field period.
[0099]
  In FIG. 22, in the simultaneous reset process Rc in the first subfield SF14, the first sustain driver 7 and the second sustain driver 8 are reset pulses RP similar to those shown in FIG._xAnd RP_YAre simultaneously applied to the row electrodes X and Y of the PDP 10, respectively. As a result, all discharge cells in the PDP 10 are reset and discharged, and wall charges are forcibly formed in each discharge cell. Immediately thereafter, the first sustain driver 7 applies a negative erase pulse with a short pulse width to the row electrode X of the PDP 10.₁~ X_nAre simultaneously applied to erase the wall charges formed in all the discharge cells. That is, according to the execution of the simultaneous reset process Rc shown in FIG. 22, all the discharge cells in the PDP 10 are initialized to a non-light emitting cell state.
[0100]
  On the other hand, in the pixel data write process Wc, only the discharge cells (selective write discharge) are discharged at the intersections between the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. ), And wall charges are selectively formed in the discharge cells. Due to the selective write discharge, the discharge cell initialized to the “non-light emitting cell” state in the simultaneous reset process Rc changes to “light emitting cell”. The selective write discharge as described above does not occur in the discharge cells formed in the “column” to which the low-voltage pixel data pulse is applied, and is initialized in the simultaneous reset process Rc. That is, the “non-light emitting cell” state is maintained.
[0101]
  That is, by executing the pixel data writing process Wc, a “light emitting cell” that maintains a light emitting state in a sustain light emitting process, which will be described later, and a “non-light emitting cell” that remains in a non-light emitting state are selected according to the pixel data. The pixel data is uniquely set and pixel data is written to each discharge cell.
[0102]
  Here, when the light emission driving by the selective writing address method is performed, as shown in FIG. 23, the selective writing is performed only in the subfield SF corresponding to the bit of the logical level “1” in the converted pixel data HD. Burst discharge is performed (indicated by black circles). At this time, no sustain discharge occurs in the light emission sustaining process Ic of each subfield existing between the first subfield SF14 and the execution of this selective write discharge, and the subfield in which this selective write discharge has been executed. In the light emission sustaining process Ic of each subfield existing thereafter, a sustain discharge is generated and the light emission state is maintained (indicated by a white circle).
[0103]
  Therefore, when such a selective write address method is adopted, the non-selected row discriminating circuit 51 and the non-light emitting SF discriminating circuit 52 are sub-rows that do not cause a selective write discharge and a sustain discharge. The field is determined at the stage of pixel data (converted pixel data HD). Here, the application of the scan pulse SP is stopped for the “row” determined not to cause the selective write discharge, and the sustain pulse IP is applied to the subfield determined not to generate the sustain discharge. By stopping the operation, power consumption is reduced.
[0104]
  In the above embodiment, the halftone drive of 15 gradations is performed by setting the simultaneous reset process Rc to be performed once in one field period. However, the simultaneous reset process Rc is performed in one field period. It is also possible to increase the number of gradation drives by executing twice in step.
[0105]
  FIG. 24 and FIG. 25 are diagrams showing a light emission drive format made in view of this point.
[0106]
  24 shows a light emission drive format applied when the selective erasure address method as described above is adopted as the pixel data writing method, and FIG. 25 shows a light emission drive format applied when the selective write address method is adopted. .
[0107]
  In these light emission drive formats shown in FIGS. 24 and 25, one field period is divided into 14 subfields SF1 to SF14. In each subfield, pixel data writing process Wc in which pixel data is written to set “light emitting cells” and non- “light emitting cells”, and a light emission sustaining process in which the light emitting state is maintained only for “light emitting cells”. Ic. At this time, the number of times of light emission in each light emission sustaining step Ic is as follows when the light emission period in the subfield SF1 is “1”:
                SF1: 1
                SF2: 1
                SF3: 1
                SF4: 3
                SF5: 3
                SF6: 8
                SF7: 13
                SF8: 15
                SF9: 20
                SF10: 25
                SF11: 31
                SF12: 37
                SF13: 48
                SF14: 50
  Is set.
[0108]
  That is, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2In this way, the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
[0109]
  Further, among these subfields, the simultaneous reset process Rc is executed in the first subfield and the intermediate subfield.
[0110]
  That is, as shown in FIG. 24, when the selective erase address method is employed, the simultaneous reset process Rc is executed in the subfields SF1 and SF7, and the selective write address method as shown in FIG. In the drive when employed, the simultaneous reset process Rc is executed in the subfields SF14 and SF6. Further, as shown in FIGS. 24 and 25, the wall charges remaining in all the discharge cells in the last subfield of one field period and the subfield immediately before the simultaneous reset process Rc are executed. An erasing process E is executed to eliminate the.
[0111]
  26 and 27 are diagrams illustrating an example of a conversion table used in the first data conversion circuit 32 illustrated in FIG. 11 when performing light emission driving based on the light emission driving format illustrated in FIGS. 24 and 25. is there.
[0112]
  The first data conversion circuit 32, based on the conversion tables of FIG. 26 and FIG. 27, input luminance adjustment pixel data D of 256 gradations (8 pits)._BL9-bit (0 to 352) conversion pixel data HD in which is 22 × 16/255 (352/255)_pAnd converted to the multi-gradation processing circuit 33. The multi-gradation processing circuit 33 performs, for example, 4-bit compression processing as described above, and outputs 5-bit (0 to 22) multi-gradation pixel data Ds.
[0113]
  At this time, the second data conversion circuit 34 shown in FIG. 11 performs the 5-bit multi-gradation pixel data D._SAre converted into 14-bit converted pixel data HD in accordance with a conversion table as shown in FIG.
[0114]
  At this time, FIG. 28 shows a case where the selective erasure address method is adopted as the pixel data writing method, and FIG. 29 shows a conversion table and light emission used in the second data conversion circuit 34 when the selective write address method is adopted. It is a figure which shows all the patterns of a drive, respectively.
[0115]
  When driving as shown in FIGS. 24 to 29 is performed, the emission luminance ratio is
[0, 1, 2, 3, 6, 9, 17, 22, 30, 37, 45, 57, 65, 82, 90, 113, 121, 150, 158, 195, 206, 245, 256}
  This makes it possible to perform half-tone driving in 23 stages.
[0116]
  As described above, in the driving shown in FIGS. 24 to 29, the subfields in one field period are divided into two subfield groups including a plurality of subfields arranged continuously. For example, when the selective erasure address method is adopted, as shown in FIG. 24, it is divided into a subfield group consisting of subfields SF1 to SF6 and a subfield group consisting of SF7 to SF14. At this time, the simultaneous reset process Rc is executed only in the first subfield of each subfield group, and all discharge cells are changed to “light emitting cells” (when the selective erasing address method is adopted) or “non-light emitting cells”. The discharge is initialized to the state (when the selective write address method is adopted). Here, in each subfield group, only in the pixel data writing process Wc of any one of the subfields, the discharge cells are set to “non-light emitting cells” or “light emitting cells” according to the pixel data. Further, in the light emission sustaining process Ic in each subfield, only the “light emitting cell” is caused to emit light for the number of times of light emission corresponding to the weighting of the subfield. Therefore, in each subfield group, the simultaneous reset operation and the selective erase operation (selective write operation) are performed once. According to such a driving method, in the case of the selective erasure address method, the light emission state is started in order from the first subfield in each subfield group as the luminance to be displayed increases. On the other hand, in the case of the selective erasure address method, the light emission state is started in order from the last subfield in each subfield group as the luminance to be displayed increases.
[0117]
  In the light emission drive pattern shown in FIGS. 10 and 23, the scanning pulse SP and the high-voltage pixel data pulse are simultaneously applied in any one pixel data writing process Wc of the subfields SF1 to SF14. Thus, selective erasing (writing) discharge is generated.
[0118]
  However, if the amount of charged particles remaining in the discharge cell is small, even if the scan pulse SP and the high-voltage pixel data pulse are applied at the same time, selective erasing (writing) discharge does not occur normally, and the discharge cell In some cases, the wall charges of the film cannot be erased (formed). At this time, even if the pixel data D after A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, which causes a problem that the image quality is remarkably deteriorated.
[0119]
  Therefore, a light emission drive pattern as shown in FIGS. 30 and 31 may be employed to prevent such an erroneous light emission operation. 30 shows the conversion table used in the second data conversion circuit 34 and all the patterns of light emission drive when the selective erasure address method is adopted, and FIG. 31 shows the conversion table used in the second data conversion circuit 34 when the selective write address method is adopted. ing.
[0120]
  In the light emission drive patterns shown in FIGS. 30 and 31, as shown by the black circles in the figure, selective erasure is continuously performed in the pixel data writing process Wc of each of two consecutive subfields. Addressing) discharge.
[0121]
  According to such an operation, even if the wall charge in the discharge cell cannot be normally eliminated (formed) by the first selective erase (write) discharge, the second selective erase (write) discharge is performed. As a result, the disappearance (formation) of the wall charges is normally performed, so that the erroneous sustain light emission as described above is prevented.
[0122]
  These two selective erasing (writing) discharges need not be performed in consecutive subfields. In short, the second selective erasing (writing) discharge may be performed in any subfield after the first selective erasing (writing) discharge is completed.
【The invention's effect】
[0123]
  As described above in detail, in the present invention, each non-selected row in which no selective erasing (writing) discharge is generated and each subfield in which no sustain discharge is generated are determined in advance based on pixel data, and such non-selection is performed. The application of the scan pulse is stopped for the row, and the application of the sustain pulse is stopped for the subfield where no sustain discharge is generated.
[0124]
  Therefore, according to the present invention, power consumption can be reduced by the amount of application of the scan pulse and sustain pulse to the plasma display panel.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a plasma display device.
FIG. 2 is a diagram illustrating an example of a light emission drive format for realizing halftone display of 16 gradations.
FIG. 3 is a diagram illustrating an example of application timing of a driving pulse applied to the PDP 10;
FIG. 4 is a diagram illustrating an example of a light emission driving pattern by a subfield method.
FIG. 5 is a diagram illustrating a configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to the present invention.
6 is a diagram showing a light emission drive format in the plasma display device shown in FIG.
FIG. 7 is a diagram illustrating an example of application timings of various drive pulses applied to the PDP 10 in accordance with the drive method according to the present invention.
FIG. 8 is a diagram illustrating an example of application timings of various drive pulses applied to the PDP 10 according to the drive method according to the present invention.
FIG. 9 is a diagram showing an example of application timings of various drive pulses applied to the PDP 10 according to the drive method according to the present invention.
FIG. 10 is a diagram showing an example of a light emission drive pattern when pixel data is written using the selective erasure address method and a conversion table used by the second data conversion circuit 34 when this light emission drive is performed. is there.
11 is a diagram showing an internal configuration of a data conversion circuit 30. FIG.
12 is a diagram showing an internal configuration of an ABL circuit 31. FIG.
13 is a diagram showing conversion characteristics in the data conversion circuit 312. FIG.
FIG. 14 is a diagram illustrating a correspondence relationship between a luminance mode and the number of times of light emission maintenance for each subfield.
15 is a diagram showing conversion characteristics in the first data conversion circuit 32. FIG.
16 is a diagram showing an example of a conversion table based on the conversion characteristics shown in FIG.
FIG. 17 is a diagram showing an example of a conversion table based on the conversion characteristics shown in FIG.
18 is a diagram showing an internal configuration of a multi-gradation processing circuit 33. FIG.
FIG. 19 is a diagram for explaining the operation of the error diffusion processing circuit 330;
20 is a diagram showing an internal configuration of a dither processing circuit 350. FIG.
FIG. 21 is a diagram for explaining the operation of the dither processing circuit 350;
FIG. 22 is a diagram showing a light emission drive format when the selective write address method is employed.
FIG. 23 is a diagram showing an example of a light emission drive pattern when the selective write address method is employed and a conversion table used by the second data conversion circuit 34 when the light emission drive is performed.
FIG. 24 is a diagram showing an example of a light emission drive format in which a simultaneous reset process Rc is executed twice in one field when the selective erase address method is adopted.
FIG. 25 is a diagram showing an example of a light emission drive format in which a simultaneous reset process Rc is executed twice in one field when the selective write address method is adopted.
26 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission driving format shown in FIGS. 24 and 25. FIG.
27 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission driving format shown in FIGS. 24 and 25. FIG.
28 is a diagram showing an example of a light emission driving pattern when performing light emission driving based on the light emission driving format shown in FIG. 24, and a conversion table used by the second data conversion circuit 34 when performing this light emission driving. is there.
29 is a diagram showing an example of a light emission drive pattern when performing light emission drive based on the light emission drive format shown in FIG. 25, and a conversion table used by the second data conversion circuit 34 when performing this light emission drive. is there.
30 is a diagram showing another example of the light emission drive pattern when the selective erasure address method is adopted and a conversion table used in the second data conversion circuit 34 when the light emission drive is performed. FIG.
FIG. 31 is a diagram showing another example of the light emission drive pattern when the selective write address method is employed and a conversion table used by the second data conversion circuit 34 when the light emission drive is performed.
[Explanation of symbols]
2 Drive control circuit
6 Address driver
7 First Sustain Driver
8 Second Sustain Driver
10 PDP
51 Non-selected row discrimination circuit
52 Non-light emitting SF discriminating circuit

Claims (7)

A driving method of a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes,
A display period of one field is divided into N subfields, and in each of the subfields, a scan pulse is sequentially applied to each of the row electrodes, and one row is synchronized with the application timing of each of the scan pulses. Each pixel data pulse having a voltage corresponding to the logic level of each pixel data is applied to each of the column electrodes for each row, thereby selectively discharging each of the discharge cells, thereby causing each of the discharge cells to be discharged. The pixel data writing process to be set in one of the light emitting cell and the non-light emitting cell, and applying the sustain pulse to the row electrode for the number of times corresponding to each of the subfields, so that only the light emitting cell is applied for the number of times. Performing a light emission sustaining step for discharging,
A reset process for initializing each of the discharge cells to one of the light emitting cells and the non-light emitting cells by discharging all the discharge cells only in the first subfield of the N subfields. Run,
In the pixel data writing process, for each row electrode, it is determined whether or not all the logic levels of the pixel data for one row corresponding to the row electrode match a predetermined level. The application of the scan pulse is stopped only for the row electrodes determined that all of the logic levels of the pixel data match the predetermined level ,
The discharge cells are selectively discharged according to the pixel data in the pixel data writing process in any one of the N subfields, thereby causing each of the discharge cells to be the light emitting cell. or the allowed set to any one state of non-light emitting cells, plasma, characterized in Rukoto allowed again rise to the selective discharge in the pixel data writing process in the subfield immediately after the subfield that rise to the selective discharge Display panel drive method. A driving method of a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes,
A display period of one field is divided into N subfields, and in each of the subfields, a scan pulse is sequentially applied to each of the row electrodes, and one row is synchronized with the application timing of each of the scan pulses. Each pixel data pulse having a voltage corresponding to the logic level of each pixel data is applied to each of the column electrodes for each row, thereby selectively discharging each of the discharge cells, thereby causing each of the discharge cells to be discharged. The pixel data writing process to be set in one of the light emitting cell and the non-light emitting cell, and applying the sustain pulse to the row electrode for the number of times corresponding to each of the subfields, so that only the light emitting cell is applied for the number of times. Performing a light emission sustaining step for discharging,
Of the N subfields, M ( 2 ≦ M ≦ N ) consecutively arranged subfields are defined as a subfield group, and all the discharge cells are set in only the first subfield in the subfield group. Performing a reset process for initializing each of the discharge cells to either one of the light-emitting cells or the non-light-emitting cells by discharging;
In the pixel data writing process, for each row electrode, it is determined whether or not all the logic levels of the pixel data for one row corresponding to the row electrode match a predetermined level. The application of the scan pulse is stopped only for the row electrodes determined that all of the logic levels of the pixel data match the predetermined level,
In the pixel data writing process in any one of the subfields in the subfield group, the discharge cells are selectively discharged according to the pixel data, whereby each of the discharge cells is changed to the light emitting cell or the light emitting cell. the non either light emitting cells allowed set to one state, the pixel data writing, characterized in that allowed to again rise to the selective discharge in the process and to pulp plasma in the subfield immediately after the subfield that rise to the selective discharge Display panel drive method. A driving method of a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes and a plurality of column electrodes arranged to cross the row electrodes,
A display period of one field is divided into N subfields, and in each of the subfields, a scan pulse is sequentially applied to each of the row electrodes, and one row is synchronized with the application timing of each of the scan pulses. Each pixel data pulse having a voltage corresponding to the logic level of each pixel data is applied to each of the column electrodes for each row, thereby selectively discharging each of the discharge cells, thereby causing each of the discharge cells to be discharged. The pixel data writing process to be set in one of the light emitting cell and the non-light emitting cell, and applying the sustain pulse to the row electrode for the number of times corresponding to each of the subfields, so that only the light emitting cell is applied for the number of times. Performing a light emission sustaining step for discharging,
N subfields are divided into subfield groups each consisting of a plurality of subfields, each of which is continuously arranged, and all the discharge cells are discharged only in the first subfield of the subfield group. Performing a reset process to initialize each of the discharge cells to the state of either the light emitting cell or the non-light emitting cell;
In the pixel data writing process, for each row electrode, it is determined whether or not all the logic levels of the pixel data for one row corresponding to the row electrode match a predetermined level. The application of the scan pulse is stopped only for the row electrodes determined that all of the logic levels of the pixel data match the predetermined level,
In the pixel data writing process in any one of the subfields in the subfield group, the discharge cells are selectively discharged according to the pixel data, whereby each of the discharge cells is changed to the light emitting cell or the light emitting cell. the non either light emitting cells allowed set to one state, the pixel data writing, characterized in that allowed to again rise to the selective discharge in the process and to pulp plasma in the subfield immediately after the subfield that rise to the selective discharge Display panel drive method. The subfield in which all the discharge cells become the non-light emitting cells is determined based on the logic level of the pixel data, and the application of the sustain pulse is stopped in the light emission sustaining process in the determined subfield. The method for driving a plasma display panel according to any one of claims 1 to 3 . According to any one of claims 2 or 3, characterized in that a deletion process to generate discharge to all the discharge cells in the non-light emitting cell state in only the sub-field of the last of the sub-field group Driving method of the plasma display panel. In the reset process, each discharge cell is reset and discharged to form wall charges in all the discharge cells, thereby initializing all the discharge cells to the state of the light emitting cells. In the pixel data writing process, , the plasma display panel according to any one of claims 1 to 3, characterized in that to occur the selective erasure discharge allowed to set selectively the discharge cells in accordance with the pixel data on the state of the non-light emitting cells Driving method. In the reset process, each of the discharge cells is reset and discharged to form wall charges in all of the discharge cells, and immediately after that, an erasing discharge is caused to cause the wall charges formed in each of the discharge cells to Erase and initialize all the discharge cells to the non-light emitting cell state, and in the pixel data writing step, a selection form for selectively setting the discharge cells to the light emitting cell state according to the pixel data the driving method of a plasma display panel according to any one of claims 1 to 3, characterized in that to rise to write discharge.

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