JP3578323B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving method of a matrix display type plasma display panel (hereinafter, referred to as PDP).
[0002]
[Prior art]
As one of such matrix display type PDPs, an AC (AC discharge) type PDP is known.
The AC type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs arranged orthogonal to the column electrodes and forming one scan line as a pair. Each row electrode pair and column electrode is covered with a dielectric layer with respect to the discharge space, and has a structure in which a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .
[0003]
At this time, since the PDP utilizes a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, a subfield method is used to realize halftone luminance display in such a PDP. In the subfield method, one field period is divided into N subfields, and a light emission period (number of times of light emission) corresponding to weighting of each bit digit of pixel data (N bits) is assigned to each subfield, and light emission driving is performed. I do.
[0004]
For example, when one field period is divided into six subfields SF1 to SF6 as shown in FIG.
SF1: 1
SF2: 2
SF3: 4
SF4: 8
SF5: 16
SF6: 32
The light emission drive is performed at a light emission period ratio of:
[0005]
For example, when the discharge cell emits light at the luminance "32", light emission is performed only in SF6 of the subfields SF1 to SF6, and when the discharge cell emits light at the luminance "31", other light except the subfield SF6 is used. Light emission is performed in the subfields SF1 to SF5. As a result, halftone luminance expression in 64 steps is possible.
Here, the light emission driving pattern in one field period is inverted between the case where the discharge cell emits light at the luminance “32” as described above and the case where light emission occurs at the luminance “31”. That is, in one field period, while the discharge cells to emit light at the luminance "32" emit light, the discharge cells to emit light at the luminance "31" are in a non-light emitting state, and emit light at this luminance "31". During the period in which the discharge cells to be lit emit light, the discharge cells to be lit at luminance "32" are in a non-light emitting state.
[0006]
Therefore, if a discharge cell to emit light at the luminance “32” and a discharge cell to emit light at the luminance “31” are adjacent to each other, a false contour may be visually recognized in this area. In other words, if the eyes of the discharge cells to emit light at luminance "31" are shifted to the discharge cells to emit light at luminance "31" immediately before the discharge cells to emit light at luminance "32" change from the non-light-emitting state to the light-emitting state, both of these discharge cells become Since only the light emission state is continuously viewed, a dark line is visually recognized on the boundary between the two. Therefore, this appears on the screen as a false contour having nothing to do with the pixel data, thereby deteriorating the display quality.
[0007]
Further, as described above, since the PDP utilizes a discharge phenomenon, it is necessary to perform a discharge (with light emission) irrelevant to the display content, which causes a problem of lowering the contrast of an image. there were.
Further, at present, when commercializing such a PDP, realizing low power consumption is a general problem.
[0008]
[Problems to be solved by the invention]
The present invention has been made to solve the above problem, and has as its object to provide a method of driving a plasma display panel that can improve display quality.
[0009]
[Means for Solving the Problems]
A driving method of a plasma display panel according to the present invention includes a row electrode pair arranged for each scanning line and a plurality of column electrodes arranged to cross each of the row electrode pairs. A driving method for performing gradation display on a plasma display panel in which a discharge cell corresponding to one pixel is formed at each intersection with a plurality of column electrodes, wherein a display period of one field is divided into N subfields, The M (2 ≦ M ≦ N) consecutively located subfields of the N subfields constitute a subfield group, and all the discharge cells are light emitting cells only in the first subfield in the subfield group. And a reset process for generating a discharge for setting the discharge cell to a non-light emitting cell in any one of the subfields within one field. A pixel data pulse in which a pixel data pulse is applied to a column electrode and a scanning pulse is sequentially applied to one of the row electrode pairs in synchronization with the pixel data pulse, and only the light emitting cells in each subfield in the subfield group And performing a sustaining light emitting step of causing a discharge to emit light only during the light emitting period corresponding to the weighting of the subfields, and dividing each subfield in the subfield group into a plurality of groups by the pulse waveform of the scanning pulse in each subfield. At least one of the pulse width and the pulse voltage of the scan pulse in the sub-group belonging to the first group including at least the first sub-field in the sub-field group is scanned in the sub-field belonging to another group. It is characterized in that it is set to be larger than each value in the pulse.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a diagram showing a schematic configuration of a plasma display device that drives a plasma display panel (hereinafter, referred to as a PDP) to emit light based on a driving method according to the present invention.
[0011]
In FIG. 2, an A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from a drive control circuit 2 and converts the analog input video signal into, for example, 8-bit pixel data (input pixel data) for each pixel. Data) D and supplies this to the data conversion circuit 30.
The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates various timing signals for controlling the drive of each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 in synchronization with the horizontal and vertical synchronization signals.
[0012]
The data conversion circuit 30 converts the 8-bit pixel data D into 14-bit converted pixel data (display pixel data) HD and supplies the converted data to the memory 4. The conversion operation of the data conversion circuit 30 will be described later.
The memory 4 sequentially writes the converted pixel data HD according to a write signal supplied from the drive control circuit 2. When writing for one screen (n rows and m columns) is completed by such a writing operation, the memory 4 stores the converted pixel data HD for one screen._11-nmIs read for each bit digit, and is sequentially supplied to the address driver 6 for each row.
[0013]
The address driver 6 responds to the timing signal supplied from the drive control circuit 2 by reading m pieces of pixel data having a voltage corresponding to the logical level of each converted pixel data bit for one row read from the memory 4. A pulse is generated and these are applied to the column electrode D of the PDP 10.₁~ D_mRespectively.
The PDP 10 has the column electrode D as an address electrode.₁~ D_mAnd row electrodes X arranged orthogonally to these column electrodes₁~ X_nAnd row electrode Y₁~ Y_nIt has. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y. That is, the row electrode pair of the first row in the PDP 10 is the row electrode X₁And Y₁And the row electrode pair in the n-th row is a row electrode X_nAnd Y_nIt is. The row electrode pairs and the column electrodes are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode.
[0014]
Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with the timing signal supplied from the drive control circuit 2, and supplies these to the row electrodes X of the PDP 10.₁~ X_nAnd Y₁~ Y_nIs applied.
FIG. 3 is a diagram showing a light emission drive format based on a drive method according to the present invention.
FIG. 4 shows that the address driver 6, the first sustain driver 7, and the second sustain driver 8 each correspond to the column electrode D of the PDP 10 according to the light emission drive format.₁~ D_m, Row electrode X₁~ X_nAnd Y₁~ Y_nFIG. 5 is a diagram showing application timings of various drive pulses applied to the oscilloscope.
[0015]
In the examples shown in FIGS. 3 and 4, the display period of one field is divided into 14 subfields SF1 to SF14 to drive the PDP 10. In each subfield, a pixel data writing process Wc for writing pixel data to each discharge cell of the PDP 10 to set a light emitting cell and a non-light emitting cell, and a sustaining light emitting process for keeping only the light emitting cells emit light Ic. Further, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and the erase process E is executed only in the last subfield SF14.
[0016]
Here, in the above-mentioned simultaneous resetting process Rc, the first sustain driver 7 and the second sustain driver 8₁~ X_nAnd Y₁~ Y_nReset pulse RP as shown in FIG. 4 for each_xAnd RP_YAre applied simultaneously. As a result, all the discharge cells in the PDP 10 are reset-discharged, and a predetermined wall charge is uniformly formed in each discharge cell. As a result, all the discharge cells in the PDP 10 become light emitting cells whose light emitting state is maintained in a sustain light emitting process described later.
[0017]
In each pixel data writing step Wc, the address driver 6 sets the pixel data pulse group DP1 for each row._1-n, DP2_1-n, DP3_1-n, ..., DP14_1-nAre sequentially applied to the column electrodes D as shown in FIG.₁~ D_mTo be applied. That is, in the subfield SF1, the address driver 6 outputs the converted pixel data HD._11-nmA pixel data pulse group DP1 corresponding to each of the first to n-th rows generated based on each first bit_1-nAre sequentially applied to the column electrodes D every one row as shown in FIG.₁~ D_mTo be applied. In the subfield SF2, the conversion pixel data HD_11-nmPixel data pulse group DP2 generated based on each second bit_1-nAre sequentially applied to the column electrodes D every one row as shown in FIG.₁~ D_mIs applied. At this time, the address driver 6 generates a high-voltage pixel data pulse and applies it to the column electrode D only when the bit logic of the converted pixel data is, for example, a logical level “1”. The second sustain driver 8 generates a scanning pulse SP as shown in FIG. 4 at the same timing as the application timing of each pixel data pulse group DP, and sends it to the row electrode Y.₁~ Y_nAre sequentially applied. At this time, discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and the discharge cell in the discharge cell Are selectively erased. Due to the selective erasure discharge, the discharge cells initialized to the state of the light emitting cells in the simultaneous reset process Rc change to non-light emitting cells. No discharge is generated in the discharge cells formed in the "column" where the high-voltage pixel data pulse is not applied, and the discharge cells are initialized in the simultaneous reset process Rc, that is, the state of the light emitting cells To maintain.
[0018]
That is, by performing the pixel data writing process Wc, a light emitting cell in which a light emitting state is maintained in a sustain light emitting process to be described later and a non-light emitting cell which remains in a light-off state are selectively set according to pixel data. That is, the so-called pixel data is written into each discharge cell.
The scanning pulse SP is applied to the row electrode Y for each of the subfields SF1 to SF14.₁~ Y_nThe pulse width of the scan pulse SP is the largest in the subfield SF1, becomes smaller in the later subfield, and becomes the smallest in the subfield SF14. That is, as shown in FIG. 4, when the pulse widths of the scan pulses SP corresponding to the subfields SF1 to SF14 are Ta1 to Ta14,
Ta1> Ta2> Ta3> Ta4>...> Ta12> Ta13> Ta14
There is such a relationship.
[0019]
In other words, if SF1 is a first group of subfields, SF2 is a second group of subfields, SF3 is a third group of subfields,..., SF14 is a fourteenth group of subfields, The pulse width of the scan pulse SP in a certain first group of subfields SF1 is set to be larger than the pulse width of the scan pulse in another group of subfields SF2 to SF14.
[0020]
In each sustain emission step Ic, the first sustain driver 7 and the second sustain driver 8 apply the row electrode X₁~ X_nAnd Y₁~ Y_nSustain pulse IP alternately as shown in FIG._XAnd IP_YIs applied. At this time, the discharge cells in which the wall charges remain due to the pixel data writing process Wc, that is, the light emitting cells are charged with the sustain pulse IP._XAnd IP_YAre alternately applied, discharge light emission is repeated and the light emission state is maintained. Note that the sustain period of light emission performed in the sustain light emission process Ic differs for each subfield as shown in FIG.
[0021]
That is, when the light emission period in the sustain light emission process Ic in the subfield SF1 is “1”,
SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF 10:25
SF11: 28
SF12: 32
SF13: 35
SF 14:39
Is set to
[0022]
That is, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2), Whereby the non-linear characteristic (gamma characteristic) of the input pixel data D is corrected.
As shown in FIG. 4, in the erasing step E in the last subfield, the address driver 6 generates an erasing pulse AP and sends it to the column electrode D._1-mTo each of. The second sustain driver 8 generates an erasing pulse EP simultaneously with the application timing of the erasing pulse AP, and outputs this to the row electrode Y.₁~ Y_nApply to each. By the simultaneous application of the erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells disappear. That is, by such an erasing discharge, all the discharge cells in the PDP 10 become non-light emitting cells.
[0023]
FIG. 5 is a diagram showing all the patterns of the light emission drive performed based on the light emission drive format as shown in FIGS.
As shown in FIG. 5, a selective erase discharge is performed on each discharge cell only in the pixel data writing process Wc in one of the subfields SF1 to SF14 (indicated by black circles). . That is, the wall charges formed in all the discharge cells of the PDP 10 by the execution of the simultaneous reset process Rc remain until the selective erasing discharge is performed, and the sustain emission process in each of the subfields SF existing therebetween is performed. In Ic, discharge light emission is promoted (shown by a white circle). That is, each discharge cell becomes a light-emitting cell until the above-described selective erasure discharge is performed within one field period, and in the sustain light-emitting step Ic in each of the sub-fields existing between the cells, as shown in FIG. Light emission is continued at the light emission period ratio.
[0024]
At this time, as shown in FIG. 5, the number of times each discharge cell changes from a light emitting cell to a non-light emitting cell is always set to one or less in one field period. That is, a light emission driving pattern in which a discharge cell once set as a non-light emitting cell is returned to a light emitting cell once within one field period is prohibited.
Therefore, as shown in FIGS. 3 and 4, the simultaneous resetting operation involving strong light emission, which is not involved in image display, need be performed only once in one field period. Can be suppressed.
[0025]
In addition, since the selective erasure discharge performed within one field period is at most one time as shown by the black circle in FIG. 5, the power consumption can be suppressed.
Further, as shown in FIG. 5, there is no light emission pattern in which the light emitting state and the light emitting state are not reversed in one field period, so that a false contour can be suppressed.
[0026]
The pulse width of the above-described scanning pulse SP is set larger in a subfield located earlier in time in the order of the subfields SF1 to SF14. This is for the following reasons. When the sustain discharge light emission is sufficiently repeated in the subfield before the subfield where the selective erase operation is performed (in the case of high luminance), sufficient priming particles are present in the discharge space and the selection is performed. Erase discharge is performed reliably. On the other hand, when there is no light emitting subfield before the subfield where the selective erasing operation is performed, or when there are few light emitting subfields (low luminance where the selective erasing discharge is performed in subfield SF1 or SF2) In the case of (1), the number of times of sustain discharge light emission is small, and sufficient priming particles do not exist in the discharge space. As described above, when the subfield of the selective erasing operation is started in a state where sufficient priming particles do not exist in the discharge space, a time delay occurs from the application of the scanning pulse SP to the actual occurrence of the selective erasing discharge. As a result, the selective erase discharge becomes unstable, and as a result, erroneous discharge occurs during the sustain discharge period, and the display quality deteriorates. Therefore, the pulse width of the scan pulse SP is set to be larger in the subfield positioned earlier in time in the order of the subfields SF1 to SF14 so that the selective erase discharge always occurs during the application of the scan pulse SP. Therefore, the stability of the selective erase operation can be ensured. Instead of changing the pulse width of the scan pulse SP, the pulse voltage of the scan pulse SP may be set to be larger in a subfield located earlier in time in the order of the subfields SF1 to SF14. . In this case, as shown in FIG. 6, assuming that the pulse voltages of the scan pulses SP corresponding to the respective subfields SF1 to SF14 are Va1 to Va14,
Va1> Va2> Va3> Va4>...> Va12> Va13> Va14
There is such a relationship.
[0027]
In other words, if SF1 is a first group of subfields, SF2 is a second group of subfields, SF3 is a third group of subfields,..., SF14 is a fourteenth group of subfields, The value of the pulse voltage of the scan pulse SP in a certain first group of subfields SF1 is set to be larger than the value of the pulse voltage of the scan pulse in another group of subfields SF2 to SF14. . As a result, even in the subfields SF1 and SF2, the voltage level of the scan pulse SP becomes temporally higher than the voltage level of the subsequent subfield, so that the selective erasing discharge can always occur.
[0028]
Furthermore, both the pulse width and the pulse voltage of the scan pulse SP may be set to be larger in the subfield located earlier in time in the order of the subfields SF1 to SF14.
Further, the pulse width and pulse voltage of the scan pulse of each subfield in the subfield group composed of the subfields SF1 to SF14 are, for example,
Ta1 = Ta2 = Ta3 = Ta4> Ta5 = Ta6 = Ta7 = Ta8> Ta9 = Ta10 = Ta11 = Ta12 = Ta13 = Ta14,
Va1 = Va2 = Va3 = Va4> Va5 = Va6 = Va7 = Va8> Va9 = Va10 = Va11 = Va12 = Va13 = Va14
It may be set as follows.
[0029]
In this case, each subfield in the subfield group composed of SF1 to SF14 has at least a plurality of groups, that is, the first subfield composed of SF1 to SF4 according to the pulse waveform of the scan pulse SP in each subfield. A first group, a second group including SF5 to SF8, and a third group including SF9 to SF14. The pulse width and pulse voltage value of the scan pulse SP in the subfield belonging to the first group Is set to be larger than each value in the scan pulse in the subfield belonging to the second and third groups.
[0030]
By the way, according to the light emission drive pattern as shown in FIG.
{0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 256}
It is possible to achieve the following fifteen levels of halftone expression. However, the pixel data D supplied from the A / D converter 1 expresses 8 bits, that is, 256 levels of halftones.
[0031]
Therefore, the data conversion is performed by the data conversion circuit 30 shown in FIG. 2 so that the halftone display of 256 steps is performed in a pseudo manner even by the 15-step gradation drive.
FIG. 7 is a diagram showing an internal configuration of the data conversion circuit 30.
In FIG. 7, an ABL (automatic brightness control) circuit 31 sequentially supplies the ABL from the A / D converter 1 so that the average brightness of an image displayed on the screen of the PDP 10 falls within a predetermined brightness range. The luminance level is adjusted for the pixel data D for each pixel, and the luminance adjustment pixel data D obtained at this time is adjusted._BLIs supplied to the first data conversion circuit 32.
[0032]
The adjustment of the luminance level is performed before performing the inverse gamma correction by setting the ratio of the number of times of light emission of the subfield to non-linear as described above. Therefore, the ABL circuit 31 performs inverse gamma correction on the pixel data (input pixel data) D, and automatically adjusts the luminance level of the pixel data D according to the average luminance of the inverse gamma-converted pixel data obtained at this time. Is configured. This prevents the display quality from deteriorating due to the luminance adjustment.
[0033]
FIG. 8 is a diagram showing the internal configuration of the ABL circuit 31.
8, the level adjustment circuit 310 adjusts the level of the pixel data D in accordance with the average luminance obtained by the average luminance detection circuit 311 described later._BLIs output. The data conversion circuit 312 calculates the brightness adjustment pixel data D_BLTo the inverse gamma characteristic (Y = X) having a non-linear characteristic as shown in FIG.^2.2) Is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, in the data conversion circuit 312, the brightness adjustment pixel data D_BLIs subjected to inverse gamma correction to restore pixel data (inverse gamma converted pixel data Dr) corresponding to the original video signal from which gamma correction has been canceled.
The average luminance detection circuit 311 emits the PDP 10 at a luminance according to the average luminance obtained as described above from among the luminance modes 1 to 4 as shown in FIG. 10 for specifying the light emission period in each subfield. A driveable luminance mode is selected, and a luminance mode signal LC indicating the selected luminance mode is supplied to the drive control circuit 2. At this time, the drive control circuit 2 determines the period during which light emission is maintained in the sustain emission process Ic of each of the subfields SF1 to SF14 shown in FIG. 3, that is, the number of sustain pulses applied in each sustain emission process Ic. The setting is made according to the mode designated by the luminance mode signal LC as shown in FIG. That is, the light emission period in each subfield shown in FIG. 3 indicates the light emission period when the brightness mode 1 is set, and if the brightness mode 2 is set,
SF1: 2
SF2: 6
SF3: 10
SF4: 16
SF5: 20
SF6: 26
SF7: 32
SF8: 38
SF9: 44
SF10: 50
SF11: 56
SF12: 64
SF13: 70
SF 14:78
Light emission driving in each subfield is performed in a light emission period.
[0034]
In this light emission drive, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is non-linear (that is, the inverse gamma ratio, Y = X^2.2), Whereby the nonlinear characteristic (gamma characteristic) of the input pixel data D is corrected.
The average luminance detection circuit 311 calculates the average luminance from the inverse gamma conversion pixel data Dr and supplies the average luminance to the level adjustment circuit 310.
[0035]
The first data conversion circuit 32 shown in FIG. 7 performs the luminance adjustment pixel data D of 256 gradations (8 bits) based on the conversion characteristics as shown in FIG._BLIs converted to 14 × 16/255 (224/255) 8-bit (0-224) converted pixel data HD_pAnd supplies it to the multi-gradation processing circuit 33. Specifically, 8-bit (0-255) luminance adjustment pixel data D_BLAre converted according to a conversion table as shown in FIGS. 12 and 13 based on the conversion characteristics. That is, the conversion characteristics are set according to the number of bits of the input pixel data, the number of compressed bits by multi-gradation, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in a stage preceding the multi-gradation processing circuit 33 to be described later, and performs conversion in accordance with the number of display gradations and the number of compression bits by multi-gradation, thereby adjusting the brightness. Pixel data D_BLIs divided at a bit boundary into a high-order bit group (corresponding to multi-gradation pixel data) and a low-order bit group (truncated data: error data), and multi-gradation processing is performed based on this signal. As a result, it is possible to prevent the occurrence of luminance saturation due to the multi-gradation processing and the occurrence of a flat portion of the display characteristics (that is, the occurrence of gradation distortion) that occurs when the display gradation is not at a bit boundary.
[0036]
Since the lower bit group is discarded, the number of gradations is reduced, and the decrease in the number of gradations is made pseudo by the operation of the multiple gradation processing circuit 33 described below. ing.
FIG. 14 is a diagram showing an internal configuration of the multi-gradation processing circuit 33.
As shown in FIG. 14, the multiple gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.
[0037]
First, the data separation circuit 331 in the error diffusion processing circuit 330 converts the 8-bit converted pixel data HD supplied from the first data conversion circuit 32._PThe lower 2 bits are separated as error data and the upper 6 bits are separated as display data.
The adder 332 outputs the converted pixel data HD as the error data._PAn addition value obtained by adding the lower two bits in the middle, the delay output from the delay circuit 334, and the multiplication output from the coefficient multiplier 335 is supplied to the delay circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and delays the addition value by the delay addition signal AD.₁Are supplied to the coefficient multiplier 335 and the delay circuit 337, respectively.
[0038]
The coefficient multiplier 335 outputs the delayed addition signal AD₁Given coefficient value K₁(For example, “7/16”) is supplied to the adder 332.
The delay circuit 337 outputs the delay addition signal AD.₁Is further delayed by a time equal to (1 horizontal scanning period-the above-mentioned delay time D × 4) to obtain a delayed addition signal AD.₂Is supplied to the delay circuit 338. The delay circuit 338 provides the delay addition signal AD₂Is further delayed by the above-described delay time D to obtain a delayed addition signal AD.₃Is supplied to the coefficient multiplier 339. Further, the delay circuit 338 controls the delay addition signal AD.₂Is further delayed by the above-described delay time D × 2 to obtain a delayed addition signal AD.₄To the coefficient multiplier 340. Further, the delay circuit 338 controls the delay addition signal AD.₂Is delayed by an amount equal to the delay time D × 3 to obtain a delayed addition signal AD.₅Is supplied to the coefficient multiplier 341.
[0039]
The coefficient multiplier 339 outputs the delayed addition signal AD₃Given coefficient value K₂(For example, “3/16”) is supplied to the adder 342. The coefficient multiplier 340 outputs the delayed addition signal AD₄Given coefficient value K₃(For example, “5/16”) is supplied to the adder 342. The coefficient multiplier 341 outputs the delayed addition signal AD₅Given coefficient value K₄(For example, “1/16”) is supplied to the adder 342.
[0040]
The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340 and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the delay time D and supplies the delayed signal to the adder 332. The adder 332 outputs the error data (converted pixel data HD_P(The lower 2 bits in the middle), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. At this time, if there is no carry, the logical level is "0" and there is carry. In this case, the carry-out signal C of the logical level "1"_OIs generated and supplied to the adder 333.
[0041]
The adder 333 outputs the display data (converted pixel data HD_PThe upper 6 bits in the middle) have the carry-out signal C_OAre output as 6-bit error diffusion processed pixel data ED.
Hereinafter, the operation of the error diffusion processing circuit 330 having such a configuration will be described.
[0042]
For example, when obtaining the error diffusion processed pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 15, first, the pixel G (j, k-1), an upper left pixel G (j-1, k-1), an upper right pixel G (j-1, k), and an upper right pixel G (j-1, k + 1) Each corresponding error data, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD₁
Error data corresponding to pixel G (j−1, k + 1): delayed addition signal AD₃
Error data corresponding to pixel G (j−1, k): delay addition signal AD₄
Error data corresponding to pixel G (j-1, k-1): delay addition signal AD₅
Each has a predetermined coefficient value K as described above.₁~ K₄And weighted addition. Next, the addition result is added to the conversion pixel data HD._P, The error data corresponding to the pixel G (j, k) are added, and the 1-bit carry-out signal C obtained at this time is added._OConvert pixel data HD_PThe upper 6 bits in the middle, that is, the data added to the display data corresponding to the pixel G (j, k) are referred to as error diffusion processed pixel data ED.
[0043]
The error diffusion processing circuit 330 is configured to convert the converted pixel data HD_PThe upper 6 bits of the middle are regarded as display data, and the remaining lower 2 bits are regarded as error data, and the peripheral pixels ｛G (j, k−1), G (j−1, k + 1), G (j−1, k) ), G (j−1, k−1)}, and the weighted sum of the error data is reflected on the display data. By this operation, the luminance of the lower two bits in the original pixel {G (j, k)} is pseudo-expressed by the peripheral pixels, and therefore the number of bits less than 8 bits, that is, the display data of 6 bits Thus, the same brightness gradation expression as that of the 8-bit pixel data can be achieved.
[0044]
If the error diffusion coefficient value is constantly added to each pixel, noise due to the error diffusion pattern may be visually recognized, resulting in deterioration of image quality. Therefore, the error diffusion coefficient K to be assigned to each of the four pixels as in the case of the dither coefficient described later.₁~ K₄May be changed for each field.
The dither processing circuit 350 performs dither processing on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to that of the 6-bit error diffusion processing pixel data ED. Pixel data D in which the number of bits is further reduced to 4 bits_SGenerate In the dither processing, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when gradation display corresponding to 8 bits is performed using upper 6 bits of pixel data of 8 bits of pixel data, four pixels adjacent to each other in the left, right, up, and down are set as one set, and each of the one set Four dither coefficients a to d each having a different coefficient value are assigned to each piece of pixel data corresponding to each pixel and added. According to such dither processing, combinations of four different intermediate display levels occur in four pixels. Therefore, even if the number of bits of the pixel data is 6, the luminance gradation level that can be expressed is four times, that is, halftone display equivalent to 8 bits is possible.
[0045]
However, if the dither patterns having the dither coefficients a to d are constantly added to each pixel, noise due to the dither patterns may be visually recognized, and the image quality is impaired.
Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to each of the four pixels for each field.
[0046]
FIG. 16 is a diagram showing an internal configuration of the dither processing circuit 350.
In FIG. 16, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four pixels adjacent to each other, and sequentially supplies these to an adder 351.
For example, as shown in FIG. 17, the pixels G (j, k) and G (j, k + 1) corresponding to the j-th row, and the pixels G (j + 1, k) and G corresponding to the (j + 1) -th row Four dither coefficients a, b, c, and d corresponding to four pixels (j + 1, k + 1) are generated. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.
[0047]
That is, in the first first field,
Pixel G (j, k): dither coefficient a
Pixel G (j, k + 1): dither coefficient b
Pixel G (j + 1, k): dither coefficient c
Pixel G (j + 1, k + 1): dither coefficient d
In the second field,
Pixel G (j, k): dither coefficient b
Pixel G (j, k + 1): dither coefficient a
Pixel G (j + 1, k): dither coefficient d
Pixel G (j + 1, k + 1): dither coefficient c
In the next third field,
Pixel G (j, k): dither coefficient d
Pixel G (j, k + 1): dither coefficient c
Pixel G (j + 1, k): dither coefficient b
Pixel G (j + 1, k + 1): dither coefficient a
And in the fourth field,
Pixel G (j, k): dither coefficient c
Pixel G (j, k + 1): dither coefficient d
Pixel G (j + 1, k): dither coefficient a
Pixel G (j + 1, k + 1): dither coefficient b
The dither coefficients a to d are repeatedly circulated by the assignment as described above, and are supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly executes the operations of the first to fourth fields as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.
[0048]
The adder 351 is provided for each of the pixels G (j, k), G (j, k + 1), G (j + 1, k), and G (j + 1, k + 1) supplied from the error diffusion processing circuit 330. Is added to each of the error diffusion processing pixel data ED corresponding to the respective fields as described above, and the dither added pixel data obtained at this time is supplied to the upper bit extraction circuit 353. .
[0049]
For example, in the first field shown in FIG.
Error diffusion pixel data ED + dither coefficient a corresponding to pixel G (j, k),
Error diffusion processing pixel data ED + dither coefficient b corresponding to pixel G (j, k + 1),
Error diffusion processing pixel data ED + dither coefficient c corresponding to pixel G (j + 1, k),
Error diffusion processing pixel data ED + dither coefficient d corresponding to pixel G (j + 1, k + 1)
Are sequentially supplied to the upper bit extraction circuit 353 as dither added pixel data.
[0050]
The upper bit extraction circuit 353 extracts up to the upper 4 bits of the dither-added pixel data, and outputs the extracted data to the multi-gradation pixel data D._SIs supplied to the second data conversion circuit 34 shown in FIG.
The second data conversion circuit 34 generates the multi-gradation pixel data D_SIs converted into converted pixel data (display pixel data) HD consisting of the 1st to 14th bits corresponding to each of the subfields SF1 to SF14 according to a conversion table as shown in FIG. The multi-gradation pixel data D_SConverts the input pixel data D of 8 bits (256 gradations) to 224/225 according to the first data conversion (conversion tables in FIGS. 12 and 13), and further performs multi-gradation processing such as error diffusion processing and dither processing. By the conversion process, 2 bits are each compressed and converted into data of a total of 4 bits (15 gradations).
[0051]
Here, among the first to fourteenth bits in the converted pixel data HD, the bit of the logic level “1” is to cause the selective erasing discharge to be performed in the pixel data writing process Wc in the subfield SF corresponding to the bit. It is shown.
Here, the conversion pixel data HD corresponding to each discharge cell of the PDP 10 is supplied to the address driver 6 via the memory 4. At this time, the form of the converted pixel data HD corresponding to one discharge cell is always one of 15 patterns as shown in FIG. The address driver 6 assigns each of the first to fourteenth bits in the converted pixel data HD to each of the subfields SF1 to SF14, and only when the bit logic is at the logic level "1", A high-voltage pixel data pulse is generated in the pixel data writing process Wc and applied to the column electrode D of the PDP 10. As a result, the selective erasing discharge is generated.
[0052]
As described above, the 8-bit pixel data D is converted into the 14-bit converted pixel data HD by the data conversion circuit 30, and the 15-step gradation display as shown in FIG. 18 is performed. By the operation of the multi-gradation processing circuit 33 as described above, the actual visual gradation expression becomes 256 gradations.
As described above, in the driving method shown in FIGS. 3 to 18, first, all the discharge cells are set to the light emitting cells (when the selective erase address method is employed) or to the non-light emitting only in the first subfield in one field period. A discharge is generated to initialize the state of the cell (when the selective write address method is employed). Next, only in the pixel data writing process in any one of the subfields, each discharge cell is set to a non-light emitting cell or a light emitting cell according to the pixel data. Further, in the light emission sustaining process in each subfield, only the light emitting cells emit light only during the light emission period corresponding to the weight of the subfield. According to such a driving method, in the case of the selective erasing address method, light emission is performed in order from the first subfield of one field as the luminance to be displayed increases, while in the case of the selective erasing address method, the display is performed. As the luminance increases, the light emission state is set in order from the last subfield of one field.
[0053]
In the above-described embodiment, the simultaneous reset operation performed within one field period is performed once to perform the halftone expression of 15 gradations. However, the simultaneous reset operation is performed twice. It is also possible to increase the number of gradations.
FIG. 19 is a diagram showing a light emission drive format made in view of the above point.
[0054]
FIG. 19 shows a light emission drive format applied when the above-described selective erase address method is employed as the pixel data writing method.
In the light emission drive format shown in FIG. 19 as well, one field period is divided into 14 subfields, that is, subfields SF1 to SF14. In each subfield, a pixel data writing process Wc for writing the pixel data to set the light emitting cells and the non-light emitting cells, and a sustain light emitting process Ic for maintaining the light emitting state only for the light emitting cells are performed. At this time, the light emitting period (the number of times of light emission) in each sustain light emitting step Ic is as follows when the light emitting period in the subfield SF1 is “1”.
SF1: 1
SF2: 1
SF3: 1
SF4: 3
SF5: 3
SF6: 8
SF7: 13
SF8: 15
SF9: 20
SF 10:25
SF11: 31
SF12: 37
SF13: 48
SF14: 50
Is set to
[0055]
That is, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is nonlinear (that is, the inverse gamma ratio, Y = X^2.2), Whereby the non-linear characteristic (gamma characteristic) of the input pixel data D is corrected.
Further, the simultaneous resetting process Rc is executed in the head subfield and the middle subfield among these subfields.
[0056]
That is, as shown in FIG. 19, in the light emission driving when the selective erase address method is adopted, the simultaneous reset process Rc is performed in the subfields SF1 and SF7. Further, as shown in FIG. 19, in the last subfield of one field period and the subfield immediately before executing the simultaneous reset process Rc, the wall charges remaining in all the discharge cells are eliminated. The erasing process E is performed.
[0057]
In the light emission drive format shown in FIG. 19 as well, the pulse width of the scan pulse SP is set to be larger in the subfield positioned earlier in time in the order of the subfields SF1 to SF14, or the pulse voltage of the scan pulse SP is increased. In the order of the subfields SF <b> 1 to SF <b> 14, the setting is made so that the subfield located earlier in time becomes larger.
[0058]
FIGS. 20 and 21 are diagrams showing an example of a conversion table used in the first data conversion circuit 32 shown in FIG. 7 when performing light emission driving based on the light emission drive format shown in FIG.
The first data conversion circuit 32 converts the input luminance adjustment pixel data DBL of 256 gradations (8 pits) into 22 × 16/255 (352/255) based on the conversion tables of FIGS. 0-352) converted pixel data HD_pAnd supplies it to the multi-gradation processing circuit 33. The multi-gradation processing circuit 33 performs, for example, 4-bit compression processing in the same manner as described above, and performs 5-bit (0 to 22) multi-gradation pixel data D._sIs output.
[0059]
At this time, the second data conversion circuit 34 shown in FIG._SIs converted in accordance with a conversion table as shown in FIG. 22 to obtain 14-bit converted pixel data (display pixel data) HD.
At this time, FIG. 22 is a diagram showing a conversion table of the second data conversion circuit 34 and all the patterns of the light emission driving used when the above-described selective erasing address method is employed as the pixel data writing method.
[0060]
In this manner, by performing the driving as shown in FIGS. 19 to 22, as shown in FIG. 22, the emission luminance ratio becomes
{0, 1, 2, 3, 6, 9, 17, 22, 30, 37, 45, 57, 65, 82, 90, 113, 121, 150, 158, 195, 206, 245, 256}
23 halftone expressions are possible.
[0061]
As described above, in the driving method shown in FIGS. 19 to 22, the subfields in one field period are divided into two subfield groups including a plurality of subfields arranged consecutively. In the case where the selective erase address method is adopted, as shown in FIG. 19, a subfield group including subfields SF1 to SF6 and a subfield group including SF7 to SF14 are provided. At this time, the simultaneous resetting process Rc is performed only in the first subfield of each subfield group to generate a discharge for initializing all the discharge cells to the state of the light emitting cells. Here, in each subfield group, the discharge cells are set as non-light emitting cells or light emitting cells in accordance with the pixel data only in the writing process of the pixel data of any one of the subfields. Further, in the light emission sustaining process in each subfield, only the light emitting cells emit light only during the light emission period corresponding to the weight of the subfield. Therefore, in each subfield group, the simultaneous reset operation and the selective erase operation are each performed once. According to this driving method, in the case of the selective erasing address method, the light emission state is sequentially set from the head subfield in each subfield group as the luminance to be displayed increases.
[0062]
In the light emission driving patterns shown in FIGS. 18 and 22 as described above, the scan pulse SP and the high-voltage pixel data pulse are generated in any one of the pixel data writing steps Wc in the subfields SF1 to SF14. At the same time, a selective erase discharge is generated.
However, if the amount of charged particles remaining in the discharge cell is small, the selective erasure discharge is not normally generated even when the scan pulse SP and the high-voltage pixel data pulse are applied at the same time, and the wall charge in the discharge cell is reduced. May not be erased. At this time, even if the pixel data D after the A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, which causes a problem that image quality is remarkably reduced.
[0063]
For example, when the selective erasure address method is adopted as the pixel data writing method, the converted pixel data HD
[0100000000000000]
In the case of, as shown by the black circle in FIG. 18, the selective erase discharge is performed only in the subfield SF2, and at this time, the discharge cell changes to a non-light emitting cell. As a result, sustain emission should be performed only in SF1 of the subfields SF1 to SF14. However, if the selective erasure in the subfield SF2 fails and the wall charges remain in the discharge cells, sustain emission is performed not only in the subfield SF1, but also in the subsequent subfields SF2 to SF14. As a result, the highest brightness is displayed.
[0064]
Therefore, in the present invention, such an erroneous light emission operation is prevented by employing a light emission drive pattern as shown in FIGS.
FIGS. 23 to 26 are diagrams showing an example of a light emission drive pattern designed to prevent such an erroneous light emission operation and a conversion table used by the second data conversion circuit 34 when performing this light emission drive. It is.
[0065]
At this time, in FIGS. 23 to 25, all the patterns of the light emission drive executed based on the light emission drive format as shown in FIG. 3, in which the simultaneous reset step Rc is provided only once in one field period, and this Each of the conversion tables used in the second data conversion circuit 34 when performing the light emission drive is shown. FIGS. 23 to 25 show light emission drive patterns executed based on the light emission drive format when the selective erase address method as shown in FIG. 3 is employed.
[0066]
Further, in FIG. 26, all the patterns of the light emission drive executed based on the light emission drive format as shown in FIG. 19 in which the simultaneous reset process Rc is provided twice in one field period, and this light emission drive is performed. In this case, an example of a conversion table used in the second data conversion circuit 34 is shown.
Here, in the light emission drive pattern shown in FIG. 23 or FIG. 26 as described above, as shown by the black circles in the figure, the pixel data writing process Wc of each of two consecutive subfields is continuously performed. A selective erase discharge is performed.
[0067]
According to such an operation, even if the wall charges in the discharge cells cannot be normally eliminated by the first selective erase discharge, the wall charges are normally eliminated by the second selective erase discharge. In addition, erroneous sustain light emission as described above is prevented.
Note that these two selective erase discharges do not need to be performed in successive subfields. In short, after the first selective erase discharge is completed, the second selective erase discharge may be performed in any of the subfields.
[0068]
FIG. 24 is a diagram showing an example of a light emission drive pattern and a conversion table of the second data conversion circuit 34 made in view of this point.
In the example shown in FIG. 24, as shown by the black circle in the figure, after the first selective erasing discharge is performed, the second selective erasing discharge is performed after one subfield is left.
[0069]
In addition, the number of times of the selective erase discharge performed in one field period is not limited to two.
FIG. 25 is a diagram showing an example of a light emission drive pattern and a conversion table of the second data conversion circuit 34 made in view of the above point.
Note that “*” shown in FIG. 25 indicates that the logic level may be either “1” or “0”, and a triangular mark indicates selective erasing only when such “*” is at logic level “1”. This indicates that discharging is performed.
[0070]
In short, since the writing of pixel data may fail in the first selective erasing discharge, the selective erasing discharge is performed again in at least one of the subfields existing thereafter, thereby writing the pixel data. It is sure that it is included.
[0071]
【The invention's effect】
As described above in detail, in the driving method of the plasma display of the present invention, the display quality can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional light emission drive format for performing 64-tone halftone display.
FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.
FIG. 3 is a diagram showing a light emission drive format when a selective erase address method is adopted.
FIG. 4 is a diagram illustrating an example of application timings of various drive pulses applied to the PDP 10.
FIG. 5 is a diagram showing an example of a light emission drive pattern performed based on the light emission drive format shown in FIG. 3;
FIG. 6 is a diagram showing another example of the application timing of various drive pulses applied to the PDP 10.
FIG. 7 is a diagram showing an internal configuration of a data conversion circuit 30.
FIG. 8 is a diagram showing an internal configuration of an ABL circuit 31;
FIG. 9 is a diagram showing conversion characteristics in a data conversion circuit 312.
FIG. 10 is a diagram showing a correspondence relationship between a luminance mode and a light emission period performed in a sustain light emission process of each subfield.
FIG. 11 is a diagram showing conversion characteristics in a first data conversion circuit 32;
FIG. 12 is a diagram showing an example of a conversion table in the first data conversion circuit 32.
13 is a diagram illustrating an example of a conversion table in the first data conversion circuit 32. FIG.
FIG. 14 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.
15 is a diagram for explaining the operation of the error diffusion processing circuit 330. FIG.
FIG. 16 is a diagram showing an internal configuration of a dither processing circuit 350.
FIG. 17 is a diagram for explaining the operation of the dither processing circuit 350;
18 is a diagram illustrating an example of all patterns of light emission driving performed based on the light emission driving format shown in FIG. 3 and an example of a conversion table used in the second data conversion circuit 34 when performing the light emission driving. is there.
FIG. 19 is a diagram showing another example of a light emission drive format when a selective erase address method is adopted.
20 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission drive format shown in FIG.
21 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission drive format shown in FIG.
22 is a diagram illustrating an example of all patterns of light emission drive performed based on the light emission drive format shown in FIG. 19 and an example of a conversion table used in the second data conversion circuit 34 when performing the light emission drive. .
FIG. 23 is a diagram showing a light emission drive pattern according to the drive method of the present invention.
FIG. 24 is a diagram showing another example of the light emission drive pattern according to the drive method of the present invention.
FIG. 25 is a diagram showing another example of a light emission drive pattern according to the drive method of the present invention.
FIG. 26 is a diagram showing another example of a light emission drive pattern according to the drive method of the present invention.
[Description of Signs of Main Parts]
2 Drive control circuit
6 Address driver
7 First Sustain Driver
8 Second sustain driver
10 PDP
30 Data conversion circuit
31 ABL circuit
32 1st data conversion circuit
33 Multi-tone processing circuit
34 Second data conversion circuit
330 Error diffusion processing circuit
350 Dither processing circuit

Claims (7)

A row electrode pair arranged for each scanning line and a plurality of column electrodes arranged to cross each of the row electrode pairs; each of the row electrode pair and the plurality of column electrodes for each scanning line; A driving method for performing gradation display on a plasma display panel in which discharge cells corresponding to one pixel are formed at intersections,
A display period of one field is divided into N subfields, and M (2 ≦ M ≦ N) consecutively located subfields of the N subfields are defined as a subfield group;
A reset step for generating a discharge for initializing all the discharge cells to the state of the light emitting cells only in the subfield at the head of the subfield group;
A pixel data pulse is applied to the column electrode to generate a discharge for setting the discharge cell to a non-light emitting cell in any one of the subfields in the one field, and the row electrode pair is synchronized with the pixel data pulse. A pixel data writing step of sequentially applying a scanning pulse to one of the
Performing a sustain emission step of causing a discharge that causes only the emission cells to emit light during the emission period corresponding to the weight of the subfield in each subfield in the subfield group,
Each subfield in the subfield group is divided into a plurality of groups by the pulse waveform of the scan pulse in each subfield, and the subfields belonging to the first group including at least the first subfield in the subfield group Wherein at least one of the pulse width and the pulse voltage value of the scan pulse is set to be larger than each value of the scan pulse in a subfield belonging to another group. A method for driving a plasma display panel. The pixel data writing process is performed in the same operation in any one of the subfields in the subfield group and at least one subfield temporally subsequent to the one subfield. A method for driving a plasma display panel according to claim 1. 3. The pixel data writing step is executed by the same operation in any one of the subfields in the subfield group and a subfield temporally immediately after the one subfield. The driving method of the plasma display panel described in the above. 2. The method according to claim 1, wherein the subfield group includes the N subfields. After execution of the sustaining light emission step in the temporally last subfield in the subfield group, erasure is performed on one of the row electrodes to generate a discharge that sets all of the discharge cells to non-light emitting cells. 2. The method of driving a plasma display panel according to claim 1, wherein a step of applying a pulse is performed. The method according to claim 1, wherein wall charges are formed on all of the discharge cells in the reset step, and the wall charges are selectively erased by applying the pixel data pulse and the scan pulse in the pixel data writing step. A method for driving a plasma display panel according to claim 1. The N + 1 gradation driving is performed by maintaining the light emitting cells in each of n (n is 0 to N) subfields continuous from the head of the N subfields in the subfield group. A method for driving a plasma display panel according to claim 4.

Images