JP3868462B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).

  As one of such matrix display type display panels, an AC (alternating discharge) type PDP is known.

  The AC-type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs that are arranged orthogonally to the column electrodes and form one scan line as a pair. Each of these row electrode pairs and column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .

  Here, as one method for performing halftone display on such a PDP, one field period is divided into N subfields that emit light for a time corresponding to the weighting of each bit digit of N-bit pixel data. A so-called subfield method has been proposed (see, for example, Patent Document 1).

  FIG. 1 is a diagram showing a light emission drive format in one field period according to the subfield method.

  In the example shown in FIG. 1, assuming that the supplied pixel data is 6 bits, light emission driving is performed by dividing one field period into six subfields SF1, SF2,. . By executing one light emission by these six subfields, it is possible to express 64 gradations for an image for one field.

  Each subfield includes a simultaneous reset process Rc, a pixel data writing process Wc, and a sustain light emission process Ic. In the simultaneous reset process Rc, all the discharge cells of the PDP are simultaneously discharged and excited (reset discharge), so that wall charges are uniformly formed in all the discharge cells. In the next pixel data writing step Wc, selective erasing discharge corresponding to the pixel data is excited for each discharge cell. At this time, the wall charges in the discharge cell in which such erasing discharge has been performed disappear and become a “non-light emitting cell”. On the other hand, the discharge cells that have not been subjected to the erasure discharge remain “light emitting cells” because the wall charges remain. In the sustain light emission process Ic, the discharge light emission state is continued only for the light emitting cells for a time corresponding to the weighting of each subfield. Thus, in each of the subfields SF1 to SF6, the sustain light emission is performed in the light emission period ratio of 1: 2: 4: 8: 16: 32 in order.

  Here, in the pixel data writing step Wc, when the selective erasure address method for selectively erasing the wall charges formed in each discharge cell as described above is employed, the head portion of each subfield is used. In FIG. 1, it is essential to perform the simultaneous reset process Rc indicated by the hatched portion in FIG.

  However, the reset discharge performed on all the discharge cells in the simultaneous reset process Rc involves a relatively strong discharge, that is, light emission with a high luminance level. Therefore, there is a problem that the contrast of the image is lowered because light emission which is not related to the pixel data occurs at the six positions indicated by the oblique lines in FIG.

  Further, in the driving form as shown in FIG. 1, for example, the light emission patterns of the discharge cells that emit light at the luminance level 31 and the discharge cells that emit light at the luminance level 32 are reversed from each other, that is, one of them emits light. Since the other is in a non-light-emitting state, there arises a problem that a false contour is generated on the boundary between both discharge cells.

Furthermore, at the present time, it is a general problem to realize low power consumption when commercializing such a PDP.
JP-A-4-195087

The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a plasma display panel driving method capable of improving contrast with low power consumption while suppressing false contours. And

The method for driving a plasma display panel according to claim 1 corresponds to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A method of driving a plasma display panel forming discharge cells, wherein all discharge cells are initialized to light emitting cells at the same time only in the first subfield of each of a plurality of subfields in a display period of one field. A reset process, a pixel data writing process in which the discharge cell is set as a non- light emitting cell in accordance with display pixel data in any one of the subfields within the display period of the one field, and the subfield in each of the subfields the discharge cell only the sustain light emission to emit light by the light emitting period corresponding to the weighting of the subfield in the state of the light emitting cells Extent and, possess a multi-gradation processing step of generating said display pixel data by performing multi-gradation processing to the input video signal, first the one field in the sub-field of the display period of the one field of is assigned the shortest light emission period of the total sub-fields in the display period, Rukoto the subfields subsequent to the subfield of the first assigned a long light emitting period than the light emitting period of the shortest A method for driving a plasma display panel.

  All discharge cells are initialized simultaneously only in the first subfield of each of a plurality of subfields within a display period of one field, and then the discharge cells emit light in accordance with display pixel data in any one subfield. While setting the cell or non-light emitting cell, only the light emitting cell emits light in each subfield. At this time, the display pixel data is acquired by performing multi-gradation processing on the input video signal.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a diagram showing a schematic configuration of a plasma display device including a driving device for driving a plasma display panel (hereinafter referred to as PDP) based on the driving method according to the present invention.

  In FIG. 2, the A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from the drive control circuit 2 and, for example, 6-bit pixel data D (input) for each pixel. Pixel data), and this is used as the data conversion circuit 3.

  The data conversion circuit 3 converts the pixel data into 9-bit conversion pixel data HD (display pixel data) according to a conversion table as shown in FIGS. 3 and 4, and supplies this to the memory 4. The conversion table as shown in FIG. 3 and FIG. 4 shows an example when a halftone display of 64 gradations is performed.

The memory 4 sequentially writes the converted pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When writing for one screen (n rows, m columns) is completed by such a writing operation, the memory 4 stores the converted pixel data HD _{11-nm for} one screen for each bit digit (from the 0th bit to the first bit). (8th bit) is divided and read, and this is sequentially supplied to the address driver 6 for each row.

For example, the memory 4 first reads only the 0th bit data in each of the m pieces of converted pixel data HD _{11 to 1m} corresponding to the first row on the screen. Next, the memory 4 reads only the 0th bit data in each of the m pieces of converted pixel data HD _{21 to 2m} corresponding to the second row. Similarly, the memory 4 sequentially reads only the 0th bit data in the converted pixel data HD up to the nth row. When this is completed, the memory 4 reads only the first bit data in each of the m pieces of converted pixel data HD _{11 to 1m} corresponding to the first row on the screen. Next, the memory 4 reads only the data of the first bit in each of the m pieces of converted pixel data HD _{21 to 2m} corresponding to the second row. Similarly, the memory 4 sequentially reads only the first bit data in the converted pixel data HD up to the nth row. Thereafter, the memory 4 divides and reads data from the second bit to the eighth bit in the converted pixel data HD in the same procedure.

  As described above, the memory 4 divides the 9-bit converted pixel data HD converted according to the conversion table as shown in FIGS. 3 and 4 into each bit digit, and changes from the 0th bit to the 8th bit. The data are sequentially read and supplied to the address driver 6 within one field period.

The address driver 6 generates pixel data pulses DP _{1 to} DP _m having voltages corresponding to the logical levels of the pixel data bit groups for each row read from the memory 4, and outputs them to the column electrodes of the PDP 10. D respectively applied to the ₁ to D _m.

  The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates a pixel data timing signal, a reset timing signal, a scanning timing signal, and a maintenance timing signal in synchronization with the horizontal and vertical synchronization signals.

The first sustain driver 7 includes a reset pulse RP _X for initializing the residual charge amount and a sustain pulse IP _X for maintaining the discharge light emission state according to various timing signals supplied from the drive control circuit 2. Are applied to the row electrodes X _{1 to} X _n of the PDP 10.

The second sustain driver 8 receives a reset pulse RP _Y for initializing the residual charge amount, a scan pulse SP for writing pixel data, and pixel data writing in accordance with various timing signals supplied from the drive control circuit 2. the well conducted to the priming pulse PP for, and generates a pulse IP _Y each maintenance for maintaining a discharge light emitting state, and applies them to the PDP10 in the row electrodes Y ₁ to Y _n.

The PDP 10 forms a row electrode corresponding to one row of the screen by a pair of the row electrode X and the row electrode Y. For example, a row electrode pair row electrodes _{X 1} and _{Y 1} in the first row in the PDP 10, the n-th row of the row electrode pair row electrodes _{X n} and _{Y n.} Further, in the PDP 10, one discharge cell is formed at the intersection between the row electrode pair and each column electrode.

  Next, the driving operation of the PDP 10 performed by the plasma display apparatus as shown in FIG. 2 will be described.

  FIG. 5 is a diagram showing a light emission drive format within one field period that is implemented when the data conversion table used in the data conversion circuit 3 is as shown in FIGS. 3 and 4.

  In the light emission drive format shown in FIG. 5, one field period is divided into nine parts composed of first to ninth divided periods. At this time, discharge light emission by the subfields SF1a to SF1c (first reset cycle) in the first to third divided periods, and discharge light emission by the subfields SF2a to SF2c in the fourth to sixth divided periods (second reset cycle). In the seventh to ninth divided periods, discharge light emission (third reset cycle) is performed by the subfields SF3a to SF3c.

  In each of these subfields SF1a to SF1c, SF2a to SF2c, and SF3a to SF3c, the pixel data writing process Wc for writing the converted pixel data HD to set the light emitting cell and the non-light emitting cell, The sustain light emission process Ic for maintaining the discharge light emission state only is performed. That is, only the discharge cells set as the light emitting cells in the pixel data writing process Wc perform discharge light emission in the sustain light emitting process Ic.

The light emission time of discharge light emission performed in the sustain light emission process Ic is as follows when the light emission time in each of the subfields SF1a to SF1c is “1”:
SF1a to SF1c: 1
SF2a to SF2c: 4
SF3a to SF3c: 16
It is.

  At this time, the logic levels of the 0th to 8th bits of the converted pixel data HD determine the light emission / non-light emission in each of the nine subfields SF1a to SF3c as shown in FIG.

That is, each of the 0th to 8th bits of the converted pixel data HD is
0th bit: Subfield SF1a
1st bit: Subfield SF1b
Second bit: Subfield SF1c
Third bit: subfield SF2a
4th bit: Subfield SF2b
5th bit: Subfield SF2c
6th bit: Subfield SF3a
7th bit: Subfield SF3b
8th bit: Subfield SF3c
The light emission / non-light emission in each subfield is determined based on the correspondence relationship as described above.

  Note that the selective erasure discharge is executed only in the subfield corresponding to the logical level “1” in the converted pixel data HD. Accordingly, in each of the first to third reset cycles, the light emission state and the logic level “1” are set in the subfield corresponding to the logic level “0” arranged temporally ahead of the subfield corresponding to the logic level “1”. The sub-field corresponding to the logic level “0” arranged behind the corresponding sub-field is non-light-emitting.

  For example, according to the converted pixel data HD [1,0,0,1,0,0,0,0,1] corresponding to the luminance level “32” as shown in FIG. 4, 9 in FIG. Light emission by the sustain discharge is performed only in the subfield SF3a and the subfield SF3b among the two subfields.

  On the other hand, as shown by the hatched lines in FIG. 5, with respect to the simultaneous reset process Rc in which the reset discharge is excited for all the discharge cells to form wall charges in each discharge cell, each of the first to third reset cycles. It is executed only in the subfields SF1a, SF2a, and SF3a which are the head part.

  That is, the simultaneous reset operation as described above is performed only at the head position of each of the first to third reset cycles shown in FIG.

  FIG. 6 is a diagram showing application timings of various drive pulses that are actually applied to the electrodes of the PDP 10 in each subfield shown in FIG. In FIG. 6, only the first reset cycle is extracted from the first to third reset cycles shown in FIG.

In FIG. 6, first, the first sustain driver 7 and the second sustain driver 8 reset discharge all the discharge cells in the PDP 10 by simultaneously applying the reset pulses RP _x and RP _Y to the row electrodes X and Y of the PDP 10 respectively. In this way, wall charges are forcibly formed in each discharge cell (simultaneous reset process Rc).

Next, the address driver 6 sequentially applies the data pulses DP0 _{1 to} DP0 _m corresponding to each row to the column electrodes D _{1 to} D _m . At this time, the data pulses DP0 _{1 to} DP0 _m applied to the column electrodes D _{1 to} D _m each correspond to the 0th bit in the converted pixel data HD as shown in FIG. The second sustain driver 8 sequentially applies the scan pulse SP to the row electrodes Y ₁ to Y _n at the same timing as the application timing of each data pulse DP. At this time, discharge occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and remains in the discharge cell. The wall charges are selectively erased. By this selective erasure, a light emitting discharge cell in which discharge light emission is performed in the sustain light emission process as described later and a non-light emitting discharge cell in which no discharge light emission is performed are set.

Immediately before each scan pulse SP is applied to each row electrode Y, a positive priming pulse PP is sequentially applied to the row electrodes Y _{1 to} Y _n . Due to the priming discharge excited in response to the application of the priming pulse PP, charged particles that have been formed in the simultaneous reset process Rc but have decreased with the passage of time are re-formed in the discharge space of the PDP 10. Therefore, pixel data is written by applying the scan pulse SP while the charged particles are present (pixel data writing process Wc1).

Next, the first sustain driver 7 and the second sustain driver 8 apply sustain pulses IP _X and IP _Y to the row electrodes X and Y alternately. At this time, the discharge cells in which the wall charges by the pixel data writing process Wc1 is remain, i.e. light emitting discharge cell, during the period in which such sustain pulses IP _X and IP _Y are alternately applied, discharge light emission Is repeatedly maintained to maintain the light emission state (sustain light emission process Ic1).

When the discharge light emission operation in the subfield SF1a composed of the simultaneous reset process Rc, the pixel data writing process Wc1, and the sustain light emission process Ic1 is completed, the address driver 6 next selects the data pulse DP1 _1- corresponding to each line. the DP1 _m sequentially applies the column electrodes _D 1 to D _m. The data pulses _DP1 1 _{~DP1 m} respectively applied to the column electrodes _D 1 to D _m at this time are those corresponding to the first bit in the but such converted pixel data HD shown in FIG. The second sustain driver 8 sequentially applies the scan pulse SP to the row electrodes Y ₁ to Y _n at the same timing as the application timing of each data pulse DP. At this time, discharge occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and remains in the discharge cell. The wall charges are selectively erased. By selectively erasing, a light emitting discharge cell capable of performing discharge light emission in a sustain light emission step Ic2 described later and a non-light emitting discharge cell that does not emit discharge light are obtained. Immediately before each scan pulse SP is applied to each row electrode Y, a positive priming pulse PP is sequentially applied to the row electrodes Y _{1 to} Y _n . By applying the priming pulse PP, charged particles are re-formed in the discharge space of the PDP 10. Therefore, while the charged particles are present, pixel data is written by applying the scan pulse SP (pixel data writing step Wc2).

Next, the first sustain driver 7 and the second sustain driver 8 apply sustain pulses IP _X and IP _Y to the row electrodes X and Y alternately. At this time, the discharge cells in which the wall charges by the pixel data writing process Wc2 is remain, i.e. light emitting discharge cell, during the period in which such sustain pulses IP _X and IP _Y are alternately applied, discharge light emission Is repeatedly maintained to maintain the light emission state (sustain light emission process Ic2).

When the discharge light emission operation in the subfield SF1b composed of the pixel data writing process Wc2 and the sustain light emission process Ic2 is completed, the address driver 6 sequentially applies the data pulses DP2 _{1 to} DP2 _m corresponding to the respective rows to the column electrode D. _{1 to} D _m are applied. The data pulses _DP2 1 _{~DP2 m} respectively applied to the column electrodes _D 1 to D _m at this time are those corresponding to the second bit of but such converted pixel in data HD as shown in FIG. The second sustain driver 8 sequentially applies the scan pulse SP to the row electrodes Y ₁ to Y _n at the same timing as the application timing of the data pulses DP. At this time, discharge occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and remains in the discharge cell. The wall charges are selectively erased. By such selective erasure, a light emitting discharge cell that can perform discharge light emission in a sustain light emission process described later and a non-light emitting discharge cell that does not perform discharge light emission are obtained. Immediately before each scanning pulse SP is applied to each row electrode Y, a positive priming pulse PP is sequentially applied to the row electrodes Y _{1 to} Y _n . By applying the priming pulse PP, charged particles are re-formed in the discharge space of the PDP 10. Therefore, pixel data is written by applying the scan pulse SP while the charged particles are present (pixel data writing step Wc3).

  The priming discharge due to the application of the priming pulse PP in the pixel data writing processes Wc2 and Wc3 occurs only in the light emitting discharge cells in which the sustain discharge light emission is repeated in the immediately preceding sustain light emission processes Ic1 and Ic2.

After completion of the pixel data writing process Wc3, then the first sustain driver 7 and second sustain driver 8 applies the sustain pulses IP _X and IP _Y alternately to the row electrodes X and Y. At this time, the discharge cells in which the wall charges by the pixel data writing process Wc2 is remain, i.e. light emitting discharge cell, during the period in which such sustain pulses IP _X and IP _Y are alternately applied, discharge light emission Is repeated to maintain the light emission state (sustain light emission step Ic3).

  The operation shown in FIG. 6 is similarly executed in the second and third reset cycles of FIG. 5 to perform discharge light emission for one field.

  Therefore, as shown in FIG. 5, the simultaneous reset operation executed in one field period is three times only at the head position of each of the first to third reset cycles.

  This is in accordance with FIG. 3 and FIG. 4 so that the transition from the light emitting discharge cell to the non-light emitting discharge cell for each of all discharge cells is always less than once in one reset cycle as shown in FIG. This is possible because the pixel data conversion is performed.

For example, the arrangement of the 0th to 2nd bits in the converted pixel data HD that controls light emission / non-light emission in each of the subfields SF1a to SF1c (first reset cycle) is as shown in FIGS.
[1,0,0]
[0,1,0]
[0,0,1]
[0,0,0]
There are limited to 4 ways.

  Note that “1” and “0” after that designate no light emission, and “0” before “1” designates light emission.

  That is, a data pattern that once sets a non-light emitting discharge cell in one reset cycle to return to the light emitting discharge cell is prohibited.

  Therefore, the simultaneous reset operation for forming wall charges for all the discharge cells need only be performed once at the beginning of the reset cycle.

  Accordingly, the simultaneous reset operation executed within one field period is only three times at the head of each of the first to third reset cycles, so that it is different from the case where the simultaneous reset operation is performed six times as shown in FIG. Thus, the contrast can be increased.

  Furthermore, the selective erasing discharge (transition from the light emitting discharge cell to the non-light emitting discharge cell) to be performed in each of the first to third reset cycles shown in FIG. The number of executions of selective erasing discharge in the memory is at most three.

  Therefore, as shown in FIG. 1, it is possible to suppress the power consumption as compared with the case where selective erasing discharge is performed six times at maximum in one field period.

  Further, a subfield having a long light emission period is divided into a plurality of parts, and when a luminance display of a predetermined level or more is performed, at least one of the divided subfields is always in a light emitting state. For example, as shown in FIG. 3, when high luminance display with a luminance level of “16” or higher is performed, SF3a of subfields SF3a to 3c having the longest light emission period in FIG. Thus, the pixel data is converted.

  Therefore, even in the case of performing display with a small change in luminance gradation, the light emission patterns of the two are not reversed between the adjacent discharge cells, so that the false contour can be suppressed.

  In the above embodiment, FIGS. 3 and 4 are used as the conversion table of the data conversion circuit 3, and the PDP 10 is driven according to the light emission drive format as shown in FIG. The configuration is not limited.

  For example, when the data conversion circuit 3 uses the conversion tables as shown in FIGS. 7 and 8 to drive the PDP 10 in the light emission drive format as shown in FIG. The number of times can be reduced.

  In the light emission drive format shown in FIG. 9, one field period is divided into first to tenth divided periods, discharge light emission (first reset cycle) by subfield SF1 in the first divided period, and subfield in the second divided period. Discharge light emission by the field SF2 (second reset cycle), discharge light emission by the subfield SF3 in the third divided period (third reset cycle), discharge light emission by each of the subfields SF4a to SF4g in the fourth to tenth divided periods ( (4th reset cycle) is performed.

When the light emission time in the subfield SF1 is “1”, the discharge light emission execution time in each of the subfields SF1 to SF4 is
SF1: 1
SF2: 2
SF3: 4
SF4a-4c: 8
It is.

  At this time, the logic levels of the 0th to 9th bits of the converted pixel data HD as shown in FIG. 7 and FIG. 8 are respectively the subfields SF1, SF2, SF3, SF4a to SF4g as shown in FIG. This determines light emission / non-light emission at.

That is, each of the 0th to 9th bits of the converted pixel data HD is
0th bit: Subfield SF1
1st bit: Subfield SF2
2nd bit: Subfield SF3
Third bit: Subfield SF4a
4th bit: Subfield SF4b
5th bit: Subfield SF4c
6th bit: Subfield SF4d
7th bit: Subfield SF4e
8th bit: Subfield SF4f
9th bit: Subfield SF4g
The light emission / non-light emission in each subfield is determined based on the correspondence relationship as described above.

  In the light emission drive format shown in FIG. 9, the simultaneous reset process Rc as shown by the hatched portion is provided only at the head in each reset cycle.

  In particular, in the fourth reset cycle, data conversion based on FIGS. 7 and 8 is performed so that the transition from the light emitting discharge cell to the non-light emitting discharge cell for all the discharge cells is always less than once. It is.

For example, the arrangement of the third to ninth bits in the converted pixel data HD that controls light emission / non-light emission in each of the subfields SF4a to SF4g is as shown in FIGS.
[1, 0, 0, 0, 0, 0, 0]
[0, 1, 0, 0, 0, 0, 0]
[0,0,1,0,0,0,0]
[0,0,0,1,0,0,0]
[0,0,0,0,1,0,0]
[0,0,0,0,0,1,0]
[0,0,0,0,0,0,1]
[0,0,0,0,0,0,0]
There are limited to 8 ways.

  That is, in the fourth reset cycle, a data pattern that once sets a non-light emitting discharge cell to return to the light emitting discharge cell is prohibited.

  Therefore, the simultaneous reset operation for forming wall charges for all the discharge cells need only be performed once at the beginning of the fourth reset cycle.

  Therefore, according to this embodiment, the simultaneous reset operation executed within one field period is only four times at the head part of each of the first to fourth reset cycles, so that the simultaneous reset operation as shown in FIG. The contrast can be increased as compared with the case where the process is performed six times.

  Further, as shown in FIG. 9, the selective erasing discharge (transition from the light emitting discharge cell to the non-light emitting discharge cell) executed in each of the first to fourth reset cycles is one time at most, so that one field The total number of selective erasing discharges performed during the period is four at the maximum.

  Therefore, as shown in FIG. 1, the power consumption can be suppressed as compared with the case where the selective erasing discharge is performed up to six times within one field period.

  In the driving method shown in FIGS. 7, 8, and 9, when the luminance level of the pixel data changes from “7” to “8”, for example, a false contour is generated on the screen. There is a fear.

That is, as shown in FIG. 7, the converted pixel data HD corresponding to the luminance level “7” is
[0,0,0,1,0,0,0,0,0,0]
On the other hand, the converted pixel data HD corresponding to the luminance level “8” is
[1,1,1,0,1,0,0,0,0,0]
It is.

  Therefore, although the luminance level changes in one step, all the light emission patterns in the subfields SF1, 2, 3, 4a are inverted, and this may be visually recognized as an erroneous contour.

  FIG. 10 is a diagram showing another embodiment of the light emission drive format made in view of such false contour generation. FIGS. 11 and 12 show conversions used when driving the PDP 10 according to this light emission drive format. It is a figure which shows a table.

  In the light emission drive format shown in FIG. 10, the light emission period ratio “8” in the subfield SF4a shown in FIG. 9 is reduced to “4”, which is the same as the subfield SF3 existing immediately before, and this reduced amount is This is compensated by increasing the light emission period ratio of the subfield SF4g to “12”.

According to such a light emission drive format, as shown in FIG. 11, the converted pixel data HD corresponding to the luminance level “7”
[0,0,0,1,0,0,0,0,0,0]
age,
Conversion pixel data HD corresponding to the luminance level “8”
[1,1,0,0,1,0,0,0,0,0]
It can be.

  Therefore, although the light emission pattern in each of the subfields SF1, 2 and 4a is inverted, the inversion does not occur in the subfield SF3. Therefore, even if the luminance level of the pixel data changes from “7” to “8”, the occurrence of false contours is suppressed.

  In short, first, the light emission maintenance time performed in the first subfield SF4a of the plurality of subfield groups (fourth cycle) is the light emission maintenance time performed in the subfield SF3 immediately before the subfield group. Same as

Here, when the luminance level of the pixel data has changed by only one level, one of the first subfields SF4a and SF3 in the subfield group always keeps the light emission state before the change. As shown in FIGS. 11 and 12, the pixel data is converted. That is, as shown in FIGS. 11 and 12, when the luminance level changes by one step, the light emission pattern in the subfields SF4a and SF3 is
[0, 1] to [0, 0] when the luminance level changes from "7" to "8"
[0,0] to [1,0] in the case of transition from luminance level "11" to "12"
Therefore, either one always continues the light emission state before the transition. In the above embodiment, the simultaneous reset operation performed within one field period is three times (FIG. 5) or four times (FIGS. 9 and 10), but the light emission drive format as shown in FIG. May be used twice.

  Furthermore, by adopting a light emission drive format as shown in FIGS. 14 and 15, it is possible to perform the simultaneous reset operation performed once within one field period. 14 shows a case where pixel data is written by the selective erasure address method as described above in the pixel data writing step Wc, and FIG. 15 shows a case where pixel data is written by the selective write address method. The light emission drive format is shown.

In the light emission drive format shown in FIGS. 14 and 15, one field period is divided into 14 subfields, which are subfields SF1 to SF14. In each of these subfields SF1 to SF14, pixel data writing process Wc in which pixel data is written to set a light emitting cell and a non-light emitting cell, and a sustain light emission process Ic in which only the light emitting cell is maintained in a discharge light emitting state. And carry out. At this time, the light emission time (number of times of light emission) in each sustain light emission process Ic is as follows:
SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF10: 25
SF11: 28
SF12: 32
SF13: 35
SF14: 39
Is set.

That is, the ratio of the number of times of light emission of each of the subfields SF1 to SF14 is set to be nonlinear (that is, the inverse gamma ratio: Y = X ^2,2 ), and thereby the nonlinear characteristic (gamma characteristic) of the input pixel data D is set. I am trying to correct it.

  Further, the simultaneous reset process Rc is executed only in the first subfield among these subfields. That is, the subfield SF1 is used in the light emission drive format when the selective erasure address method is used as shown in FIG. 14, and only the subfield SF14 is used in the light emission drive format when the selective write method is used as shown in FIG. Thus, the simultaneous reset process Rc is executed. Further, as shown in FIG. 14 and FIG. 15, in the last subfield of one field period, an erasing process E is performed to extinguish wall charges remaining in all the discharge cells.

  FIG. 16 is a diagram showing a configuration of a plasma display device that performs the light emission driving operation based on FIGS. 14 and 15.

  The plasma display device shown in FIG. 16 is obtained by changing the data conversion circuit 3 in the configuration shown in FIG. 2 to a data conversion circuit 30, and other functional modules other than this are shown in FIG. Is the same. Therefore, only the operation of the data conversion circuit 30 shown in FIG. 16 will be described below.

  FIG. 17 is a diagram showing an internal configuration of the data conversion circuit 30. As shown in FIG.

In FIG. 17, an ABL (automatic brightness control) circuit 31 is sequentially supplied from the A / D converter 1 so that the average brightness of an image displayed on the screen of the PDP 10 is within a predetermined brightness range. It adjusts the brightness level for pixel data D for each pixel, and supplies the time resulting luminance adjusted pixel data D _BL to the first data conversion circuit 32.

  Since the luminance level is adjusted before the inverse gamma correction is performed by setting the ratio of the number of times of light emission in the subfield as described above to be non-linear, the ABL circuit 31 converts the pixel data D (input pixel data) into the inverse gamma. Correction is performed, and the luminance level of the pixel data D (input pixel data) is automatically adjusted according to the average luminance of the inverse gamma conversion pixel data obtained at this time. Thereby, deterioration of display quality due to brightness adjustment can be prevented.

  FIG. 18 is a diagram showing an internal configuration of the ABL circuit 31. As shown in FIG.

18, the level adjustment circuit 310 outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average luminance obtained by the average luminance detecting circuit 311 which will be described later. The data conversion circuit 312 converts the luminance adjustment pixel data _DBL using inverse gamma characteristics (Y = ^X2.2 ) having non-linear characteristics as shown in FIG. This is supplied to the detection circuit 311. That is, restored by the data conversion circuit 312 performs inverse gamma correction on the luminance adjusted pixel data D _BL, a pixel corresponding to the release by the original video signal of the gamma correction data (inverse gamma converted pixel data Dr) To do. The average luminance detection circuit 311 obtains the average luminance from the inverse gamma conversion pixel data Dr and supplies it to the level adjustment circuit 310. Further, the average luminance detection circuit 311 has a luminance according to the average luminance obtained as described above from the luminance modes 1 to 4 for designating the light emission time in each subfield as shown in FIG. 20, for example. Is selected, and a luminance mode signal LC indicating the selected luminance mode is supplied to the drive control circuit 2.

Here, the first data conversion circuit 32, the input luminance adjusted pixel data _{D BL} of 14 × 16/255 (224/255) of 256 gradations (8 bits) on the basis of but such conversion characteristics as shown in FIG. 21 The converted 8-bit (0 to 224) converted pixel data HD _p is supplied to the multi-gradation processing circuit 33. Specifically, it is converted according although such a conversion table shown in FIGS. 22 and 23 based on the conversion characteristics according the input luminance adjusted pixel data D _BL of 8 bits (0 to 255). That is, this conversion characteristic is set according to the number of bits of the input pixel data, the number of compression bits by multi-gradation, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit to be described later, and the conversion is performed according to the display gradation number and the compression bit number by the multi-gradation, thereby adjusting the luminance. the pixel data D _BL, upper bit group (multi-level gray scale corresponding to the pixel data) and low-order bit group (truncated data: error data) cut at the bit boundaries, performs multi-gradation processing based on the signal It is like that. As a result, it is possible to prevent the occurrence of luminance saturation due to the multi-gradation processing and the occurrence of a flat portion of display characteristics (that is, the occurrence of gradation distortion) that occurs when the display gradation is not at the bit boundary.

  FIG. 24 is a diagram showing an internal configuration of the multi-gradation processing circuit 33. As shown in FIG.

  As shown in FIG. 24, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.

First, the data separation circuit 331 in the error diffusion processing circuit 330 converts the lower i bits in the m-bit conversion pixel data HD _P supplied from the first data conversion circuit 32 shown in FIG. -i) Separate the bits as display data.

The adder 332 delays the addition value obtained by adding the lower i bits in the converted pixel data HD _P as the error data, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. Supply to circuit 336. The delay circuit 336 uses the coefficient multiplier 335 and the delay circuit 337 as a delayed addition signal AD ₁ as a signal obtained by delaying the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data. Respectively.

The coefficient multiplier 335 supplies a multiplication result obtained by multiplying the delayed addition signal AD ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) to the adder 332.

Delay circuit 337, further the delay addition signal AD ₁ - supplied to the delay circuit 338 which is delayed by (1 horizontal scanning period the delay time D × 4) comprising time as a delay addition signal AD _2. The delay circuit 338 supplies the delayed addition signal AD ₂ further delayed by the delay time D to the coefficient multiplier 339 as the delayed addition signal AD ₃ . Further, the delay circuit 338 supplies the delayed multiplier signal AD ₂ further delayed by the delay time D × 2 to the coefficient multiplier 340 as a delayed add signal AD ₄ . Further, the delay circuit 338 is supplied to the coefficient multiplier 341 and a delayed such delay addition signal AD ₂ by further the delay time D × 3 becomes time period as a delay addition signal AD _5.

The coefficient multiplier 339 supplies the multiplication result obtained by multiplying the delay addition signal AD ₃ by a predetermined coefficient value K ₂ (for example, “3/16”) to the adder 342. The coefficient multiplier 340 supplies a multiplication result obtained by multiplying the delayed addition signal AD ₄ by a predetermined coefficient value K ₃ (for example, “5/16”) to the adder 342. The coefficient multiplier 341 supplies a multiplication result obtained by multiplying the delay addition signal AD ₅ by a predetermined coefficient value K ₄ (for example, “1/16”) to the adder 342.

The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 adds a logical level when there is no carry when adding the lower i bits in the converted pixel data HD _P , the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. If there is a carry, “0”, a carry-out signal _CO of logical level “1” is generated and supplied to the adder 333.

The adder 333, the display data consisting of the upper (m-i) bits of the converted pixel data HD in _P, the error diffusion processed pixel with those obtained by adding the carry-out signal C _O a (m-i) bits Output as data ED. That is, the bit number of such error diffusion processing pixel data ED is becoming smaller than the converted pixel data HD _P.

  The operation of the error diffusion processing circuit 330 having such a configuration will be described below.

For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 25, first, the left side pixel G (j, k) of the pixel G (j, k) is obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Each error data corresponding to each, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD ₁
Error data corresponding to pixel G (j−1, k + 1): delayed addition signal AD ₃
Error data corresponding to pixel G (j−1, k): delayed addition signal AD ₄
Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD ₅
Each is weighted and added with predetermined coefficient values K _{1 to} K ₄ as described above. Then, the addition result, the lower i bits of the converted pixel data HD _P, i.e. pixel G (j, k) by adding the error data corresponding to the carry-out signal C _O of 1 bit obtained when the the upper in the converted pixel data HD _P (m-i) bits, that is, pixel G (j, k) error diffusion processing pixel data ED those obtained by adding the display data corresponding to the.

With this configuration, the error diffusion processing circuit 330 regards the upper (m−i) bits in the converted pixel data HD _P as display data, and the remaining lower i bits as error data, and the surrounding pixels {G (j, k -1), G (j-1, k + 1), G (j-1, k), G (j-1, k-1)} are weighted and added to the display data It is made to reflect in. With this operation, the luminance of the lower i bits in the original pixel {G (j, k)} is expressed in a pseudo manner by the peripheral pixels, and therefore, the number of bits smaller than m bits, that is, (m−i) bits. In this display data, luminance gradation expression equivalent to the m-bit pixel data can be achieved.

If this error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field as in the case of the dither coefficient described later.

The dither processing circuit 350 performs a dither process on the (m−i) -bit error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby obtaining a luminance gradation level equivalent to that of the error diffusion processing pixel data ED. also generates a multi-gradation processing pixel data D _S with a reduced number of bits (m-i-j) bits while maintaining. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.

  However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.

  Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to the four pixels for each field.

  FIG. 26 is a diagram showing an internal configuration of the dither processing circuit 350.

  In FIG. 26, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351. For example, as shown in FIG. 27, the pixel G (j, k) and pixel G (j, k + 1) corresponding to the jth row, and the pixel G (j + 1, k) corresponding to the (j + 1) th row. ) And four dither coefficients a, b, c and d corresponding to the four pixels G (j + 1, k + 1), respectively. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field,
Pixel G (j, k): Dither coefficient a
Pixel G (j, k + 1): Dither coefficient b
Pixel G (j + 1, k): Dither coefficient c
Pixel G (j + 1, k + 1): Dither coefficient d
In the next second field,
Pixel G (j, k): Dither coefficient b
Pixel G (j, k + 1): Dither coefficient a
Pixel G (j + 1, k): Dither coefficient d
Pixel G (j + 1, k + 1): Dither coefficient c
In the next third field,
Pixel G (j, k): Dither coefficient d
Pixel G (j, k + 1): Dither coefficient c
Pixel G (j + 1, k): Dither coefficient b
Pixel G (j + 1, k + 1): Dither coefficient a
And in the fourth field,
Pixel G (j, k): Dither coefficient c
Pixel G (j, k + 1): Dither coefficient d
Pixel G (j + 1, k): Dither coefficient a
Pixel G (j + 1, k + 1): Dither coefficient b
In such an assignment, the dither coefficients a to d are repeatedly generated by being circulated and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.

  The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each, and the dither coefficients a to d assigned to each field as described above are added, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.

For example, in the first field shown in FIG.
Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
Each of the error diffusion processing pixel data ED + dither coefficient d corresponding to the pixel G (j + 1, k + 1) is sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data.

Upper bit extracting circuit 353 extracts until the upper (m-i-j) bits of such dither-added pixel data, the second data converting circuit 34 shown in FIG. 17 as the multi-gradation pixel data D _S To supply.

The second data conversion circuit 34, according to which it such a conversion table shown in FIG. 28 or FIG. 29 such multi-gradation pixel data _{D S,} the corresponding subfield SF1~SF14 each shown in FIG. 14 or 15 Conversion into converted pixel data HD (display pixel data) consisting of 1st to 14th bits.

  28 and 29, the multi-gradation pixel data Ds is converted into 8-bit (256 gradations) input pixel data D to 224/225 according to the first data conversion (conversion tables of FIGS. 22 and 23). Further, it is converted into 4 bits (0 to 14:15 gradations) by multi-gradation processing (for example, compression by 2 bits in each of error diffusion and dither processing and compression of a total of 4 bits).

28 shows a conversion table used when light emission driving by the selective erasure address method as shown in FIG. 14 is performed. On the other hand, FIG. 29 shows light emission driving by the selective writing method as shown in FIG. The conversion table used in a case is shown. At this time, the bit of the logic level “1” in the converted pixel data HD including the first to the 14th bits is selectively erased (selective write) in the pixel data writing process Wc in the subfield SF corresponding to the bit. Discharge) is performed. The memory 4 shown in FIG. 16 sequentially writes the converted pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When writing for one screen (n rows, m columns) is completed by such writing operation, the memory 4 stores the converted pixel data HD _{11-nm for} one screen for each bit digit (first bit to 14th). The data is divided into bits and read out, and this is sequentially supplied to the address driver 6 for each row.

  For example, when performing the light emission driving by the selective erasing address method as shown in FIG. 14, the memory 4 stores the 14-bit converted pixel data HD converted according to the conversion table as shown in FIG. The data is divided for each digit, sequentially read from the first bit to the 14th bit, and these are supplied to the address driver 6 within one field period.

The address driver 6 erases the pixel data pulses DP _{1 to} DP _m having voltages corresponding to the logical levels of the pixel data bit groups for each row read from the memory 4 and the residual charge amount. Pulses AP are generated and applied to the column electrodes D _{1 to} D _m of the PDP 10 at timing as shown in FIG. 30 or FIG.

  The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates a pixel data timing signal, a reset timing signal, a scanning timing signal, and a maintenance timing signal in synchronization with the horizontal and vertical synchronization signals. At this time, the drive control circuit 2 performs the number (period) of sustain timing signals supplied in each sustain light emission stroke Ic shown in FIG. 14 or FIG. 15, that is, the sustain pulse applied in each sustain light emission stroke Ic. The number is set according to the mode specified by the luminance mode signal LC as shown in FIG. For example, in the sustain light emission process Ic of the subfield SF1 shown in FIG. 14 or FIG. 15, when the mode designated by the luminance mode signal LC is mode 1, “1”, and when the mode is mode 2, “2”, “3” when in mode 3, and “4” when in mode 4.

The first sustain driver 7 includes a reset pulse RP _X for initializing the residual charge amount and a sustain pulse IP _X for maintaining the discharge light emission state according to various timing signals supplied from the drive control circuit 2. the generated and applied them in FIG. 30 or PDP10 in the row electrodes _X 1 to X _n in which although such timing shown in FIG. 31. The second sustain driver 8 receives a reset pulse RP _Y for initializing the residual charge amount, a scan pulse SP for writing pixel data, and pixel data writing in accordance with various timing signals supplied from the drive control circuit 2. , A sustaining pulse IP _Y for maintaining the discharge light emission state, and an erasing pulse EP for erasing the residual wall charge are generated, and these are shown in FIG. 30 or FIG. However, it is applied to the row electrodes Y _{1 to} Y _n of the PDP 10 at such timing.

30 is a diagram showing the application timing of each drive pulse within one field period during light emission driving by the selective erasure address method, and FIG. 31 is one field period during light emission driving by the selective write address method. It is a figure which shows the application timing of each drive pulse in the inside. At this time, in the light emission driving by the selective write address method shown in FIG. 31, first, the first sustain driver 7 and the second sustain driver 8 apply reset pulses RP _x and RP to the row electrodes X and Y of the PDP 10 respectively. By simultaneously applying _Y to cause all the discharge cells in the PDP 10 to perform a reset discharge, wall charges are forcibly formed in each discharge cell (R ₁ ). Immediately after that, the first sustain driver 7 erases the wall charges formed in all the discharge cells by simultaneously applying the erase pulse EP to the row electrodes X _{1 to} X _n of the PDP 10 (R ₂ ). The simultaneous reset process Rc is performed by a series of operations of R ₁ and R ₂ described above. In the pixel data writing step Wc in FIG. 31, a discharge occurs only in the discharge cells at the intersections between the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. Wall charges are selectively formed in the discharge cells. By such selective writing, a light emitting discharge cell in which discharge light emission is performed in the sustain light emission process Ic and a non-light emitting discharge cell in which no discharge light emission is performed are set.

  Here, as shown in FIG. 28, when light emission driving by the selective erasure address method is performed, the selective erasure discharge is generated only in the subfield SF corresponding to the bit of the logical level “1” in the conversion pixel data HD. Implemented (indicated by black circles). At this time, the lighting state is maintained in the subfield SF existing from the first subfield SF1 to the time when the selective erasing discharge is performed (indicated by a white circle), and the light-off state is maintained after the selective erasing discharge.

  When light emission driving by the selective write address method is performed, as shown in FIG. 29, selective write discharge is performed only in the subfield SF corresponding to the bit of the logical level “1” in the converted pixel data HD. Is carried out (indicated by black circles). At this time, in the subfield SF existing between the first subfield SF14 and the execution of the selective write discharge, the light-off state is maintained, and the subfields existing after the subfield SF in which the selective write discharge is executed are maintained. The lighting state is maintained in the field SF (indicated by a white circle).

Therefore, according to such a configuration, as shown in FIG. 28 and FIG.
{0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 256}
The light emission drive for the PDP 10 is performed at the 15 gradations described above, but due to the operation of the multi-gradation processing circuit 33, the actual visual gradation expression is larger than the 15 gradations.

  The actual light emission luminance varies depending on the mode designated by the luminance mode signal LC as shown in FIG. That is, the light emission period in each light emission sustaining process Ic shown in FIGS. 14 and 15 shows the mode 1 in FIG. 20, but the mode specified by the luminance mode signal LC is mode 2. In the case of the mode 1, the luminance is twice as high as that of the mode 1, in the case of the mode 3, the luminance is 3 times, and in the mode 4, the luminance is 4 times.

  As described above, in the driving method shown in FIGS. 14 to 31, the simultaneous reset process Rc is executed only in the subfield arranged at the head in one field period while ensuring the desired luminance. Only in the writing process of the pixel data of the subfield, each discharge cell is configured to be set to one of the light emitting cell and the non-light emitting cell according to the pixel data. At this time, in order to increase the luminance, when the selective erasing address method is adopted, the lighting state is sequentially turned on from the first subfield of one field, and when the selective writing address method is adopted, from the last subfield of one field. Turn them on in order.

  Therefore, as shown in FIG. 13, the contrast can be improved as compared with the case where the simultaneous reset process Rc is executed twice within one field period. In addition, since the number of centroid movements during bit carry within one field period, that is, the number of transitions from the lit state to the unlit state (or from the unlit state to the lit state) within one field period is small, pseudo contour It can be reduced sufficiently. Further, since the selective erasing operation (selective writing operation) for writing the pixel data is performed only once in one field period, the address power is greatly reduced.

  32 and 33 are diagrams showing another light emission drive format implemented by the configuration shown in FIGS. 16 to 18.

  In the light emission drive format as shown in FIG. 32 and FIG. 33, subfields in one field period are divided into two subfield groups composed of a plurality of subfields arranged in succession, and each subfield group is divided into two subfield groups. The simultaneous reset process Rc is executed only in the subfield arranged at the head, and each discharge cell is one of the light emitting cell and the non-light emitting cell according to the pixel data only in the pixel data writing process of any one subfield. It is comprised so that it may be in the state set to. Accordingly, in each subfield group, the simultaneous reset operation and the selective erase operation (selective write operation) are performed once. At this time, in order to increase the luminance, when the selective erasing address method is adopted, the lighting state is sequentially turned on from the first subfield of one field, and when the selective writing address method is adopted, from the last subfield of one field. Turn them on in order.

  32 shows a case where pixel data is written by the selective erasure address method as described above in the pixel data writing step Wc, and FIG. 33 shows a case where pixel data is written by the selective write address method. The light emission drive format is shown.

In the light emission drive format shown in FIGS. 32 and 33, one field period is divided into 14 subfields of subfields SF1 to SF14. In each of these subfields SF1 to SF14, pixel data writing process Wc in which pixel data is written to set a light emitting cell and a non-light emitting cell, and a sustain light emission process Ic in which only the light emitting cell is maintained in a discharge light emitting state. And carry out. At this time, the light emission time (number of times of light emission) in each sustain light emission process Ic is as follows:
SF1: 1
SF2: 1
SF3: 1
SF4: 3
SF5: 3
SF6: 8
SF7: 13
SF8: 15
SF9: 20
SF10: 25
SF11: 31
SF12: 37
SF13: 48
SF14: 50
Is set.

That is, the ratio of the number of times of light emission of each of the subfields SF1 to SF14 is set to be nonlinear (that is, the inverse gamma ratio: Y = X ^2,2 ), and thereby the nonlinear characteristic (gamma characteristic) of the input pixel data D is set. I am trying to correct it.

  Further, among these subfields, the simultaneous reset process Rc is executed in the first subfield and the intermediate subfield.

  That is, in the light emission drive format when the selective erase address method as shown in FIG. 32 is adopted, the simultaneous reset process Rc is executed in the subfields SF1 and SF7, and the selective writing method as shown in FIG. 33 is adopted. In the light emission drive format at this time, the simultaneous reset process Rc is executed in the subfields SF14 and SF6. Further, as shown in FIGS. 32 and 33, wall charges remaining in all the discharge cells in the last subfield of one field period and the subfield immediately before the simultaneous reset process Rc is executed. An erasing process E is executed to eliminate the.

  FIG. 34 is a diagram showing the conversion characteristics of the first data conversion circuit 32 in FIG. 17 applied when the light emission drive based on the light emission drive format shown in FIGS. 32 and 33 is performed. These are figures which show an example of the conversion table based on this conversion characteristic.

Here, the first data conversion circuit 32, based on the conversion table of FIG. 35 and FIG. 36, the input luminance adjusted pixel data _{D BL} of 22 × 16/255 (352/255) of 256 gradations (8 bits) and supplies the multi-gradation processing circuit 33 converts the converted pixel data HD _p of the 9 bits (0 to 352). The multi-gradation processing circuit 33 performs, for example, 4-bit compression processing as described above, and outputs 5-bit (0 to 22) multi-gradation pixel data Ds.

  37 and 38 are diagrams showing a conversion table in the second data conversion circuit 34 shown in FIG. 17 and a driving state in one field. At this time, FIG. 37 shows a conversion table used when light emission driving by the selective erasure address method as shown in FIG. 32, while FIG. 38 shows light emission driving by the selective writing method as shown in FIG. The conversion table used when performing is shown.

  In FIG. 37 and FIG. 38, the multi-gradation pixel data Ds is set to 352/255 according to the first data conversion (conversion tables of FIG. 22 and FIG. 23) of 8-bit (256 gradations) input pixel data D. Further, it is converted into 5 bits (0 to 22:23 gradations) by multi-gradation processing (for example, compression processing of a total of 4 bits compressed by 2 bits each by error diffusion processing and dither processing).

  32 to 38, for example, the number of simultaneous reset steps Rc and selective erasing operations (selective writing operations) performed in one field period is two in one field period. However, as compared with the driving method shown in FIG. 13, the contrast is improved, the pseudo contour is reduced, and the address power is reduced.

  In addition, according to the configuration shown in FIGS. 32 to 38, the number of display gradations is 23, so the number of display gradations is larger than the configuration shown in FIGS. 14 to 31 (display gradation number is 15). Will increase.

  As described above in detail, according to the present invention, the number of reset discharges for initializing all discharge cells and selective erasing (writing) discharges corresponding to display pixel data can be reduced within a display period of one field. As a result, the contrast of the image is increased and a reduction in power consumption is achieved. Furthermore, even in the case of performing display with a small change in luminance gradation, the light emission patterns of the two discharge cells do not invert each other, so that the false contour can be suppressed.

It is a figure which shows the conventional light emission drive format for implementing halftone display of 64 gradations. It is a figure which shows schematic structure of the plasma display apparatus which drives a plasma display panel. 6 is a diagram illustrating an example of a conversion table in the data conversion circuit 3. FIG. 6 is a diagram illustrating an example of a conversion table in the data conversion circuit 3. FIG. It is a figure which shows an example of the light emission drive format. It is a figure which shows an example of the application timing of the various drive pulses applied to PDP10 within 1 reset cycle. It is a figure which shows another example of the conversion table in the data conversion circuit. It is a figure which shows another example of the conversion table in the data conversion circuit. It is a figure which shows another example of the light emission drive format. It is a figure which shows another example of the light emission drive format. It is a figure which shows the conversion table used when light-emitting drive of PDP10 by the light emission drive format shown by FIG. It is a figure which shows the conversion table used when light-emitting drive of PDP10 by the light emission drive format shown by FIG. It is a figure which shows another example of the light emission drive format. It is a figure which shows another example of the light emission drive format (selection erase address method) based on the drive method by this invention. It is a figure which shows another example of the light emission drive format (selective writing method) based on the drive method by this invention. 1 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention. 2 is a diagram showing an internal configuration of a data conversion circuit 30. FIG. 2 is a diagram showing an internal configuration of an ABL circuit 31. FIG. 6 is a diagram illustrating conversion characteristics in a data conversion circuit 312. FIG. It is a figure which shows the correspondence of luminance mode and the light emission period in each subfield. 6 is a diagram showing conversion characteristics in a first data conversion circuit 32. FIG. 6 is a diagram illustrating an example of a conversion table in a first data conversion circuit 32. FIG. 6 is a diagram illustrating an example of a conversion table in a first data conversion circuit 32. FIG. 3 is a diagram illustrating an internal configuration of a multi-gradation processing circuit 33. FIG. 5 is a diagram for explaining the operation of an error diffusion processing circuit 330. FIG. 3 is a diagram showing an internal configuration of a dither processing circuit 350. FIG. 6 is a diagram for explaining the operation of a dither processing circuit 350. FIG. 6 is a diagram illustrating an example of a conversion table in a second data conversion circuit 34. FIG. 6 is a diagram illustrating an example of a conversion table in a second data conversion circuit 34. FIG. It is a figure which shows the application timing (selective erase address method) of various drive pulses. It is a figure which shows the application timing (selective writing method) of various drive pulses. It is a figure which shows another example of the light emission drive format (selective erase address method). It is a figure which shows another example of the light emission drive format (selective writing method). 6 is a diagram illustrating another example of conversion characteristics in the first data conversion circuit 32. FIG. It is a figure which shows another example of the conversion table in the 1st data conversion circuit. It is a figure which shows another example of the conversion table in the 1st data conversion circuit. It is a figure which shows another example of the conversion table in the 2nd data conversion circuit. It is a figure which shows another example of the conversion table in the 2nd data conversion circuit.

Explanation of symbols

1 A / D Converter 2 Drive Control 3 Data Conversion Circuit 4 Memory 6 Address Driver 7 First Sustain Driver 8 Second Sustain Driver 10 PDP (Plasma Display Panel)
30 Data conversion circuit 31 ABL circuit 31
32 first data conversion circuit 33 multi-gradation processing circuit 34 second data conversion circuit
330 Error diffusion processing circuit
350 Dither processing circuit

Claims (8)

A method for driving a plasma display panel, in which a discharge cell corresponding to one pixel is formed at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes Because
A reset process in which all discharge cells are simultaneously initialized to light emitting cells only in the first subfield of each of a plurality of subfields within a display period of one field;
A pixel data writing step of setting the discharge cells as non- light emitting cells in accordance with display pixel data in any one of the subfields within the display period of the one field;
A sustain light emission process in which only the discharge cells in the state of the light emitting cells in each of the subfields emit light for a light emission period corresponding to the weighting of the subfields;
Possess a multi-gradation processing step of generating said display pixel data by performing multi-gradation processing to the input video signal,
The shortest light emission period of all the subfields in the display period of the one field is assigned to the first subfield of the display period of the one field, and each subfield subsequent to the first subfield is assigned to each subfield. the driving method of a plasma display panel, wherein that you have assigned a long light emitting period than the light emitting period of the shortest. Prior SL maintains light emission process, gradation display by emitting the discharge cells in continuous in each subfield of subfields of the head to the subfield immediately before the subfield of the 1 to the state of the light emitting cells The method for driving a plasma display panel according to claim 1, wherein:   2. The plasma display panel driving method according to claim 1, wherein the multi-gradation processing is error diffusion processing and / or dither processing.   2. The plasma display panel according to claim 1, further comprising an erasing step of erasing wall charges on all the discharge cells only in the last subfield within the display period of the one field. Driving method. The discharge in the state of the light emitting cell in the sustain light emission process in each of a series of n (n: 0 to N) subfields of the N subfields arranged in the display period of the one field. 2. The method of driving a plasma display panel according to claim 1, wherein (N + 1) gradation display is performed by causing a cell to emit light. 2. The driving of a plasma display panel according to claim 1 , wherein each of the subfields in the display period of one field is assigned a light emission period that becomes large by a non-linear change in the order of arrangement of the subfields. Method. Wherein immediately before the multi-gradation processing, as claimed in claim 1, wherein the bit separating said input video signal into upper bit group and a lower bit group required the multi-gradation processing Driving method. The light emission period assigned to each of the subfields is different from each other, and each of the subfields is arranged in order of decreasing the light emission period within the display period of the one field. Display panel drive method.

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