JP2001154630A - Dither processing circuit for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dither processing circuit conducting excellent dither processing suppressing the occurrence of a dither pattern. SOLUTION: Dither coefficients to be allocated to respective pixels in respective pixel groups are changed according to luminance levels shown by the pixel data answering to an input video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dither processing circuit for a display device.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight two-dimensional image display panel, a plasma display panel (hereinafter referred to as a PDP) has been proposed.
) Are attracting attention. The PDP is directly driven by a digital video signal, and the number of luminance gradations that can be represented is determined by the number of bits of pixel data for each pixel based on the digital video signal.

As a method of driving a PDP in gradation, a unit screen display period, for example, a display period of one field, is divided into N pieces each of which emits light for a time corresponding to weighting of each bit digit of pixel data (N bits). A so-called subfield method of driving by dividing into subfields is known. For example, when the pixel data is 8 bits, the display period of one field is divided into subfields S in the order of weighting.
F8, SF7,..., SF1 are divided into eight subfields. In each subfield, an address period in which the setting of the illuminated pixel and the unlit pixel according to the pixel data is performed for each display line of the PDP, and a sustain period in which only the illuminated pixel emits light for a time corresponding to the weight of the subfield. Execute. That is, light emission drive control is performed independently for each subfield to determine whether light emission is performed in that subfield. Therefore, in one field, a subfield in a “light emitting” state and a subfield in a “non-light emitting” state are mixed. At this time, the brightness of the halftone is expressed by the sum of the light emission times performed in each subfield in one field.

In a display device employing a PDP,
By using dither processing in combination with such gradation driving, the number of gradations on the visual side is increased to improve image quality. In the dither processing, one intermediate luminance is expressed by a plurality of pixels adjacent to each other on a display screen. For example, four pixels adjacent to each other vertically and horizontally are regarded as one set, and four dither coefficients (for example, 0, 1, 2) having different coefficient values are used for pixel data corresponding to each of the set of pixels. , 3)
Add to each pixel data.

However, when the dither coefficient is added to the pixel data as described above, a pseudo pattern having no relation to the original pixel data, that is, a so-called dither pattern may be visually recognized, and the image quality is impaired. Was.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a dither processing circuit of a display device capable of performing a good dither process while suppressing the generation of a dither pattern. The purpose is to provide.

[0007]

SUMMARY OF THE INVENTION A dither processing circuit of a display device according to the present invention is a dither processing circuit of a display device for displaying a two-dimensional image on a display screen in accordance with a video signal consisting of continuously generated unit screen information signals. Circuit, a dither coefficient generating means for generating a dither coefficient corresponding to each pixel position of each of the plurality of pixel groups on the screen, and a circuit for generating the dither coefficient based on the video signal corresponding to each of the pixels. The dither coefficient generating means changes the dither coefficient to be generated according to the luminance level represented by the pixel data.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a plasma display device equipped with a dither processing circuit according to the present invention. Such a plasma display device includes a PDP 10 as a plasma display panel and a driving unit (synchronization detection circuit 1, drive control circuit 2, A / D
It comprises a D converter 4, a data conversion circuit 30, a memory 5, an address driver 6, a first sustain driver 7 and a second sustain driver 8).

[0009] PDP10 is provided with column electrodes D ₁ to D _m as address electrodes, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are arranged orthogonal to these column electrodes. PD
In P10, a pair of the row electrode X and the row electrode Y
Row electrodes corresponding to the rows are formed. The row electrode pairs and the column electrodes are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to a pixel is formed at an intersection of each row electrode pair and a column electrode. That is, PD
In P10, n × m pixels corresponding to (first row / first column) to (n-th row / m-th column) are formed.

The synchronization detecting circuit 1 generates a vertical synchronizing signal V when detecting a vertical synchronizing signal from a video signal as a unit screen information signal continuously supplied for each screen. Further, the synchronization detection circuit 1 generates a horizontal synchronization signal H when detecting a horizontal synchronization signal from the video signal. The synchronization detection circuit 1 supplies each of the vertical synchronization signal V and the horizontal synchronization signal H to the drive control circuit 2 and the data conversion circuit 30. The A / D converter 4 samples the video signal according to the clock signal supplied from the drive control circuit 2, converts the video signal into, for example, 8-bit pixel data D for each pixel, and sends the data to the data conversion circuit 30. Supply.

FIG. 2 is a diagram showing the internal configuration of the data conversion circuit 30. As shown in FIG. 2, the data conversion circuit 30 includes an ABL (automatic brightness control) circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second data conversion circuit. The ABL circuit 31
The luminance level of the pixel data D for each pixel sequentially supplied from the A / D converter 4 is adjusted so that the average luminance of the image displayed on the screen of P10 falls within an appropriate luminance range. performed, this time resulting luminance adjusted pixel data D _BL
Is supplied to the first data conversion circuit 32.

FIG. 3 is a diagram showing the internal configuration of the ABL circuit 31. In FIG. 3, the level adjustment circuit 310
Outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average luminance obtained by the average luminance detecting circuit 311 which will be described later. Data conversion circuit 312, the inverse gamma characteristic becomes such luminance adjusted pixel data D _BL from but such non-linear characteristics shown in FIG. 4 (Y = X ^2.2)
Is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, by performing inverse gamma correction processing on the luminance adjustment pixel data _DBL , pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal from which gamma correction has been canceled is restored. The average luminance detection circuit 311 first obtains the average luminance of the inverse gamma conversion pixel data Dr. Here, the average luminance detection circuit 311 determines which of the luminance modes 1 to 4 that the average luminance falls into the four stages of the range from the highest luminance to the lowest luminance, and determines the corresponding luminance mode. Is supplied to the drive control circuit 2, and the average luminance obtained as described above is supplied to the level adjustment circuit 310. That is, the level adjustment circuit 310 outputs the pixel data D in accordance with the average luminance.
Of the brightness adjustment pixel data _DBL
Is supplied to the data conversion circuit 312 and the first data conversion circuit 32 at the next stage. The first data conversion circuit 32, the luminance adjusted pixel data D _BL based on but such conversion characteristics as shown in FIG. 5 "0" to "384" is converted into first conversion pixel data D _H of 9 bits from Are supplied to the multi-gradation processing circuit 33. The first data conversion circuit 32 performs data conversion in accordance with the number of display gradations in the multi-gradation processing circuit 33 to be described later and the number of compression bits by multi-gradation. In other words, the luminance saturation due to the multi-gradation processing of the multi-gradation processing circuit 33 and the occurrence of a flat portion of the display characteristics that occurs when the display gradation is not at a bit boundary (ie,
(Generation of gradation distortion) is prevented.

[0013] multi-gradation processing circuit 33, by performing the error diffusion processing and dither processing with respect to the first converted pixel data D _H of the 9 bits, and also the number of bits while maintaining a Genkaicho number 4 to generate the multi-gradation processing pixel data D _S which is reduced to bits. The error diffusion processing and the dither processing will be described later. The second data conversion circuit 34 converts the display drive pixel data GD comprising the multi-gradation processing pixel data D _S of the 4 bits from the first to twelfth bits in accordance Although such a conversion table shown in FIG. Each of the first to twelfth bits corresponds to each of subfields SF1 to SF12 described later.

As described above, according to the multi-gradation processing circuit 33 and the second data conversion circuit 34, 256 bits of 8 bits are used.
The pixel data D capable of expressing a gradation is converted into 12-bit display drive pixel data GD composed of a total of 13 patterns as shown in FIG. The memory 5 sequentially writes and stores the display drive pixel data GD according to a write signal supplied from the drive control circuit 2. When the writing operation completes the writing of the display drive pixel data GD _11-nm for one screen (n rows and m columns), the memory 5 responds to the read signal supplied from the drive control circuit 2 and The display drive pixel data GD _{11-nm is set} to 1
The data is sequentially read out for each row and supplied to the address driver 6. That is, the memory 5 stores the driving display drive pixel data GD11 _-nm for one screen, each consisting of 12 bits, as DB1 _11-nm : the first bit of the display drive pixel data GD11 _-nm DB2 _11-nm : second bit DB3 _11-nm of the display drive pixel data GD _11-nm: the third bit DB4 _11-nm of the display drive pixel data GD _11-nm: the fourth bit DB5 of the display drive pixel data GD _{11-nm 11-nm:} the fifth bit DB 6 _11-nm of the display drive pixel data GD _11-nm: the sixth bit DB7 _11-nm of the display drive pixel data GD _11-nm: the display drive pixel data GD _11-nm 7 bit DB8 _11-nm: the eighth bit DB9 _11-nm of the display drive pixel data GD _{11 to-nm:} the ninth bit DB 10 _11-nm of the display drive pixel data GD _{11 to-nm:} the display drive pixel data GD ₁₁ to 10 bit DB 11 _11-nm of _-nm: 11th bi display drive pixel data GD _11-nm DOO th DB12 _11-nm: the display divided into 12 as the 12th bit of the display drive pixel data GD _11-nm drive pixel data bits DB1
_{11-nm to} DB12 Captured as _11-nm . And these D
Each of B1 _11-nm , DB2 _11-nm ,..., DB12 _11-nm is set to 1 according to the read signal supplied from the drive control circuit 2.
The data is sequentially read out for each row and supplied to the address driver 6.

The drive control circuit 2 generates a clock signal for the A / D converter 4 and a write / read signal for the memory 5 in synchronization with the horizontal synchronization signal H and the vertical synchronization signal V. Further, the drive control circuit 2 supplies various timing signals for driving the PDP 10 to each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 according to the light emission drive format as shown in FIG.

In the light emission drive format shown in FIG. 7, a unit screen display period, a so-called one field period, is divided into twelve subfields SF1 to SF12. In each subfield, pixel data is written to each discharge cell of the PDP 10 to set “light emitting cells” and “non-light emitting cells”.
And a light emission sustaining process Ic in which only the “light emitting cell” emits light for a period (number of times) corresponding to the weight of each subfield.
And However, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is performed only in the first subfield SF1, and the erase process E is performed only in the last subfield SF12.

FIG. 8 shows that the address driver 6, the first sustain driver 7, and the second sustain driver 8 each include a PDP according to the light emission drive format shown in FIG.
It is a figure which shows the application timing of various drive pulses applied to ten row electrodes and column electrodes. First, the subfield S
In the simultaneous reset process Rc at F1, applies the reset pulse RP _x of negative polarity first sustain driver 7 such is shown in Figure 8 to the row electrodes X ₁ to X _n. Simultaneously with the application of the reset pulse RP _x, the second sustain driver 8, a reset pulse R of positive polarity as shown in FIG. 8
Applying a P _Y to the row electrodes Y ₁ to Y _2. Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed. As a result, all the discharge cells are temporarily set to “light emitting cells”.

Next, pixel data in each subfield
In the writing process Wc, the address driver 6
Logic of display drive pixel data bit DB supplied from 5
Generates pixel data pulse with voltage corresponding to level
I do. At this time, the address driver 6 outputs pixel data for one row.
Data pulse group DP composed of data pulses
_1-mTo be applied. For example, in the subfield SF1
In the pixel data writing process Wc, the display drive pixel data
Bit DB1_11-nm, The amount corresponding to the first line
Mari DB1_11-1mAnd extract these DB1_11-1mEach argument
Consisting of m pixel data pulses corresponding to the logical level
Pixel data pulse group DP1₁And the column electrode D_1-mMark on
Add. Next, the display drive pixel data bit DB1
_11-nmDB1 corresponding to the second row of_21-2mTo
Extract these DB1_21-2mCorresponding to each logic level
Pixel data pulse consisting of m pixel data pulses
Group DP1_TwoAnd the column electrode D_1-mIs applied. Below,
The pixel data writing process of subfield SF1
In Wc, the pixel data pulse group DP1 for each row _Three~
DP1_nTo the column electrode D_1-mTo be applied. The address
The driver 6 has a logic of the display drive pixel data bit DB.
If the level is "1", a high-voltage pixel data pulse
And if it is "0", it is a low voltage (0 volt) pixel
It is assumed that a data pulse is generated.

Further, in the pixel data writing process Wc, the second
The sustain driver 8 generates a negative-polarity scan pulse SP as shown in FIG. 8 at the same timing as each application timing of the pixel data pulse group DP as described above,
This sequentially applies to the row electrodes Y ₁ to Y _n. On this occasion,
Discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and remains in the discharge cell. Wall charges are selectively erased. That is, each of the first to twelfth bits in the display drive pixel data GD determines whether or not to cause a selective erase discharge in the pixel data writing process Wc in each of the subfields SF1 to SF12. Due to the selective erasure discharge, the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc change to “non-light emitting cells”. On the other hand, no discharge occurs in the discharge cells formed in the "column" to which the low-voltage pixel data pulse is applied, and the current state is maintained. That is, the “non-light emitting cell” discharge cells maintain the “non-light emitting cell” state, and the “light emitting cell” discharge cells maintain the “light emitting cell” state. In this way, by the pixel data writing process Wc for each subfield, “light emitting cells” in which a sustain discharge is generated in the light emission sustaining process Ic immediately thereafter and “non-light emitting cells” in which no sustain discharge is generated are set.

Next, the light emission sustaining process I of each subfield
In c, a first sustain driver 7 and second sustain driver 8 each, alternately as shown in FIG. 8 to the row electrodes X ₁ to X _n and Y ₁ to Y _n a positive polarity sustain pulse IP of
Applying a _X and IP _Y. Here, the number of times of the sustain pulse IP applied in the light emission sustain step Ic is SF1: 1 SF2: 2 SF3: 4 SF4: 7 SF5: 11 SF6: 14 SF7: 20 SF8: 25 for each of the subfields SF1 to SF12. SF9: 33 SF10: 40 SF11: 48 SF12: 50

Then, the last subfield SF12
The erasing process E is executed only by the above. In the erasing step E, the address driver 6 generates a positive erasing pulse AP as shown in FIG. 8 and applies it to the column electrodes D _{1 -m} . Further, the second sustain driver 8 generates a negative erasing pulse EP as shown in FIG. 8 at the same time as the application timing of the erasing pulse AP, and applies this to each of the row electrodes Y _{1 to} Y _n . By the simultaneous application of the erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells disappear. That is, by such an erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.

As described above, according to the light emission driving shown in FIGS. 7 and 8, only the discharge cells set as "light emitting cells" in the pixel data writing process Wc in each subfield emit light immediately after that. Light emission is repeated as many times as described above in the maintenance process Ic. At this time, halftone luminance is expressed by the total number of light emissions performed in each of the subfields SF1 to SF12 in one field.

Here, whether each discharge cell is set as a "light-emitting cell" or a "non-light-emitting cell" is determined by the display drive pixel data GD as shown in FIG. That is, when the logical level of each bit of the display drive pixel data GD is the logical level “1”, a selective erase discharge is generated in the pixel data writing process Wc of the subfield corresponding to the bit digit, and the discharge cell Is set to "non-light emitting cell". On the other hand, the logic level of the bit is a logic level "
In the case of "0", the above-mentioned selective erasing discharge is not generated, so that the current state is maintained. The state of the "light emitting cell" is maintained as it is.
In the subfields SF1 to SF12, the discharge cell is set to "
The only opportunity to make the transition from the "non-light-emitting cell" state to the "light-emitting cell" is in the reset step Rc in the first subfield SF1. Any one
Of the discharge cells that have once transitioned to the “non-light emitting cells” in the pixel data writing process Wc,
Does not change to Therefore, according to the display drive pixel data GD shown in FIG. 6, each discharge cell is a “light emitting cell” until a selective erase discharge is generated in a subfield indicated by a black circle in FIG. Then, light emission is performed as many times as described above in the light emission sustaining process Ic of each subfield indicated by a white circle existing therebetween.

Therefore, according to the display drive pixel data GD having 13 types of data patterns as shown in FIG. 6, [0: 1: 3: 7: 14: 25: 39: 59: 84: 117: 157 ： 20
5: 255], which is capable of expressing the luminance of 13 gradations. However, the pixel data D obtained based on the video signal can express 8 bits, that is, 256 gray levels. Therefore, the multi-gradation processing circuit 33 performs multi-gradation processing in order to realize a halftone display in the vicinity of 256 levels even by the 13-level gradation driving.

FIG. 9 is a diagram showing the internal configuration of the multi-gradation processing circuit 33. As shown in FIG. 9, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350. First, the data separation circuit 331 in the error diffusion processing circuit 330 converts the upper 7 bits of the 9-bit first converted pixel data _DH supplied from the first data converter 32 into display data and the lower 2 bits.
The bits are separated as error data. Adder 33
2 is the first converted pixel data D as such error data
An addition value obtained by adding the lower two bits in _H , the delayed output from the delay circuit 334, and the multiplied output from the coefficient multiplier 335 is supplied to the delay circuit 336. The delay circuit 336
The added value supplied from the adder 332 is referred to as pixel data A /
Delayed by the delay time D having the same time and the clock period in D converter 4, and supplies each to the coefficient multiplier 335 and a delay circuit 337 so as delayed addition signal AD _1. The coefficient multiplier 335 supplies the multiplication result obtained by multiplying the delayed addition signal AD ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) to the adder 332. Delay circuit 337
Further the delay addition signal AD ₁ - supplied to the delay circuit 338 which is delayed by (1 horizontal scanning period the delay time D × 4) comprising time as a delay addition signal AD _2. The delay circuit 338 is supplied to the coefficient multiplier 339 such delay addition signal AD ₂ further those delayed by the delay time D as a delay addition signal AD _3. Also, the delay circuit 338
Calculates the delay addition signal AD ₂ further by the delay time D ×
A signal delayed by two times is a delayed addition signal AD ₄
To the coefficient multiplier 340. Further, the delay circuit 3
38, the delay time D × such delay addition signal AD ₂
A signal obtained by delaying the delay addition signal AD ₅
Is supplied to the coefficient multiplier 341. Coefficient multiplier 339
A predetermined coefficient value K ₂ to the delay addition signal AD ₃ (eg, "
3/16 ") to the adder 342 the multiplication result obtained by multiplying the. Coefficient multiplier 340, the delayed addition signal AD ₄
Is multiplied by a predetermined coefficient value K ₃ (for example, “5/16”), and the result is supplied to the adder 342. Coefficient multiplier 341
A predetermined coefficient value K ₄ to the delay addition signal AD ₅ (e.g., "
1/16 ") is supplied to the adder 342. The adder 342 converts the coefficient multipliers 339 and 34.
An addition signal obtained by adding the multiplication results supplied from each of 0 and 341 is supplied to the delay circuit 334. The delay circuit 334 delays the added signal by the delay time D and supplies it to the adder 332. The adder 332 adds the error data (lower 2 bits in the first converted pixel data _DH ), the delayed output from the delay circuit 334, and the multiplied output of the coefficient multiplier 335, and when there is no carry. Generates a carry-out signal C _O having a logical level “0” and a carry level “1” when there is a carry.
33. The adder 333 outputs the result of adding the carry-out signal C _O to the display data (the upper 7 bits in the first converted pixel data D _H ) as 7-bit error diffusion processed pixel data ED.

The operation of the error diffusion processing circuit 330 having such a configuration will now be described with reference to FIG.
An operation for obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the DP 10 will be described as an example. First,
The pixel G (j, k-1) on the left side of the pixel G (j, k), the pixel G (j-1, k-1) on the upper left and the pixel G (j-1, k) on the upper right , And the error data corresponding to each of the pixels G (j-1, k + 1) on the upper right, that is, the error data corresponding to the pixels G (j, k-1): the delay addition signal A
D1 Error data corresponding to _one pixel G (j-1, k + 1): delayed addition signal AD Error data corresponding to _three pixels G (j-1, k): delayed addition signal A
D ₄ pixel G (j-1, k- 1) to the error data corresponding: to the delay addition signal AD ₅ respectively, to implement the weighted addition using the coefficient K ₁ ~K ₄ such as described above. Next, the lower two bits of the first converted pixel data _DH , that is, the pixel G (j,
The error data corresponding to k) is added. Then, the 1-bit carry-out signal C _O as a result of the addition is _output to the first
The upper 7 bits of the converted pixel data _DH , that is, the sum of the upper 7 bits and the display data corresponding to the pixel G (j, k) are obtained as 7-bit error diffusion processed pixel data ED.

That is, the error diffusion processing circuit 330 outputs the pixels G (j, k-1), G (j-1, k + 1), G (j-k) around the pixel G (j, k).
1, k) and G (j-1, k-1) are weighted and added to the display data corresponding to the pixel G (j, k). With this operation, the pixel G (j, k)
, The luminance component corresponding to the lower 2 bits is pseudo-expressed by the peripheral pixels. Therefore, with the number of bits smaller than 8 bits, that is, 7 bits of display data, the luminance equivalent to the 8-bit pixel data D is obtained. The gradation expression becomes possible. If the coefficient value of the error diffusion is constantly added to each pixel, noise due to the error diffusion pattern may be visually confirmed, thereby deteriorating the image quality. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field (frame).

The dither processing circuit 350 performs dither processing on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330 as described below. Thus, while maintaining a luminance gradation level equivalent to the intermediate luminance represented by the 7-bit error diffusion processing pixel data ED, the number of bits is reduced to 4 bits, and the multi-gradation processing pixel data D _S Generate Also in such dither processing, one intermediate luminance is expressed by a plurality of adjacent pixels.

FIG. 11 shows the configuration of the dither processing circuit 350.
It is a figure showing an internal configuration. Low luminance component extraction circuit 351
Is the pixel G of the PDP 10 as shown in FIG._{(1 , 1)}
To pixel G_{(n, m)}Error supplied corresponding to each of the above
Each of the difference diffusion processed pixel data ED is output once every four fields.
The lower three bits are extracted at a ratio. Soshi
Then, the low-luminance component extraction circuit 351 applies the extracted error expansion.
The lower 3 bits of each of the dispersed pixel data ED are
Supply as minute BL to the low luminance component level discriminating circuit 352
I do. First, the low-luminance component level discriminating circuit 352 shown in FIG.
For each pixel group consisting of 4 rows × 4 columns surrounded by a bold line of 2,
Each of the low-luminance components BL corresponding to each pixel in the pixel group
It is determined whether or not all levels are the same. here
If all levels are determined to be the same,
The degree component level discrimination circuit 352 calculates the low luminance component BL
Therefore, the indicated level is any one of "0", "2", "4", and "6".
It is determined whether or not one of them is applicable. At this time, low
The level indicated by the luminance component BL is “0” or “0”.
If it corresponds to any of 2 "," 4 ", and" 6 ", it has low brightness
The degree component level determination circuit 352 outputs the logic level “0”.
The matrix selection signal is supplied to the selector 353. one
On the other hand, it does not correspond to any of "0", "2", "4", and "6"
If not, that is, one of "1", "3", "5", "7"
If so, the low-luminance component level determination circuit 352
Selects the dither matrix selection signal of logic level "1"
53. Also, a low luminance component level determination circuit 352
Are the low luminance components BL corresponding to the respective pixels in the pixel group.
Logic level "1" even if all levels are not the same
Is supplied to the selector 353.
You.

The first dither matrix circuit 354 and the second
Each of the dither matrix circuits 355 expresses “0” to “7” for each 4 × 4 pixel group surrounded by a bold line in FIG. 12 corresponding to each pixel position in the pixel group. Generate the resulting 3-bit dither coefficient. Then, each of the generated dither coefficients is sent to the selector 353 at a timing corresponding to each of the error diffusion processing pixel data ED supplied corresponding to each pixel in the pixel group. Each of the first dither matrix circuit 354 and the second dither matrix circuit 355 performs the same operation in that dither coefficients of "0" to "7" are generated. Are assigned different dither coefficients.

FIG. 13 shows a first dither matrix circuit 35.
FIG. 9 is a diagram showing a dither matrix table showing the assignment of dither coefficients generated at 4 to each pixel position. FIG.
As shown in FIG. 3, the first dither matrix circuit 354
Is the first field of the PDP 10
The (4L-3) th column in the (4K-3) row, the (4L-2) th
The dither coefficients "7", "3", "6", and "2" are generated corresponding to the pixels belonging to the column, the (4L-1) th column, and the 4Lth column, respectively.

In the first field, the first dither matrix circuit 354 operates the (4K-th)
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "0", "4", "1", and "5" are generated corresponding to the pixels belonging to the (L-1) th column and the fourth Lth column, respectively.

In the first field, the first dither matrix circuit 354 operates the (4K-th)
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients “6”, “2”, “7”, and “3” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the first field, the first field
The dither matrix circuit 354 includes the (4L-3) th column, the (4L-2) th column, and the (4L-
1) The dither coefficients "1", "5", "0", and "4" are generated corresponding to the pixels belonging to the column and the fourth L column, respectively.

Note that K is a natural number from 1 to n / 4, and L is a natural number from 1 to m / 4. The next second
In the field, the first dither matrix circuit 35
4 is the (4L-) in the (4K-3) -th row of the PDP 10.
3) row, (4L-2) th row, (4L-1) th row, and 4L
A dither coefficient "4", "0", "5", "1" is generated corresponding to each of the pixels belonging to the column.

In the second field, the first dither matrix circuit 354 operates the (4K-th)
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "3", "7", "2", and "6" are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

In the second field, the first dither matrix circuit 354 operates the (4K-th)
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients “5”, “1”, “4”, and “0” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the second field, the first field
The dither matrix circuit 354 includes the (4L-3) th column, the (4L-2) th column, and the (4L-
1) The dither coefficients “2”, “6”, “3”, and “7” are generated corresponding to each of the pixels belonging to the column and the fourth L-th column.

In the next third field, the first dither matrix circuit 354 operates the (4K-3) th PDP 10
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients “1”, “5”, “0”, and “4” are generated corresponding to the pixels belonging to the column and the fourth L column, respectively.

In the third field, the first dither matrix circuit 354 outputs the (4K-
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients “6”, “2”, “7”, and “3” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

In the third field, the first dither matrix circuit 354 outputs the (4K-
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients “0”, “4”, “1”, and “5” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the third field, the first dither matrix circuit 354 performs the fourth K
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients "7", "3", "6", and "2" are generated corresponding to the pixels belonging to the column and the fourth L column, respectively.

In the next fourth field, the first dither matrix circuit 354 operates the (4K-3) th PDP 10
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients "2", "6", "3", and "7" are generated corresponding to the pixels belonging to the column and the fourth L column, respectively.

In the fourth field, the first dither matrix circuit 354 outputs the (4K-
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients “5”, “1”, “4”, and “0” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

In the fourth field, the first dither matrix circuit 354 operates the (4K-th)
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients "3", "7", "2", and "6" are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the fourth field, the first dither matrix circuit 354 outputs the fourth K
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients “4”, “0”, “5”, and “1” are generated corresponding to each of the pixels belonging to the column and the fourth L-th column.

The first dither matrix circuit 354 repeatedly executes a series of dither coefficient generation operations in the first to fourth fields as shown in FIG. On the other hand, the second dither matrix circuit 355
Generates a dither coefficient corresponding to each pixel position in a 4 row × 4 column pixel group according to a dither matrix table as shown in FIG.

As shown in FIG. 14, in the first first field, the second dither matrix circuit 355 generates the (4L-3) th row in the (4K-3) th row of the PDP 10.
The dither coefficients "7", "3", "6", and "2" are respectively associated with the pixels belonging to the column, the (4L-2) th column, the (4L-1) th column, and the 4Lth column. Occurs.

In the first field, the second dither matrix circuit 355 operates the (4K-th)
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "0", "4", "5", and "1" are generated corresponding to the pixels belonging to the L-1) column and the fourth L column, respectively.

In the first field, the second dither matrix circuit 355 outputs the (4K-
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients “6”, “2”, “7”, and “3” are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the first field, the second
The dither matrix circuit 355 includes the (4L-3) th column, the (4L-2) th column, and the (4L-
1) The dither coefficients “5”, “1”, “0”, and “4” are generated corresponding to each of the pixels belonging to the column and the fourth L-th column.

Note that K is a natural number from 1 to n / 4, and L is a natural number from 1 to m / 4. The next second
In the field, the second dither matrix circuit 35
5 is the (4L-) in the (4K-3) -th row of the PDP 10.
3) row, (4L-2) th row, (4L-1) th row, and 4L
A dither coefficient "1", "5", "4", "0" is generated corresponding to each pixel belonging to the column.

In the second field, the second dither matrix circuit 355 outputs the (4K-
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "2", "6", "3", and "7" are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

In the second field, the second dither matrix circuit 355 outputs the (4K-
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients “4”, “0”, “1”, and “5” are generated corresponding to each of the pixels belonging to the (L−1) th column and the fourth Lth column.

Further, in the second field, the second
The dither matrix circuit 355 includes the (4L-3) th column, the (4L-2) th column, and the (4L-
1) A dither coefficient "3", "7", "2", "6" is generated corresponding to each of the pixels belonging to the column and the fourth L column.

In the next third field, the second dither matrix circuit 355 outputs the (4K-3)
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients “6”, “2”, “7”, and “3” are generated corresponding to each of the pixels belonging to the column and the fourth L column.

In the third field, the second dither matrix circuit 355 outputs the (4K-
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "5", "1", "0", and "4" are generated corresponding to each of the pixels belonging to the (L-1) th column and the fourth Lth column.

In the third field, the second dither matrix circuit 355 outputs the (4K-
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients "7", "3", "6", and "2" are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

Further, in the third field, the second dither matrix circuit 355 outputs the fourth K
(4L-3) th column, (4L-2) th column, (4L
-1) A dither coefficient "0", "4", "5", "1" is generated corresponding to each of the pixels belonging to the column and the fourth L-th column.

In the next fourth field, the second dither matrix circuit 355 outputs the (4K-3)
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients "4", "0", "1", and "5" are generated corresponding to each of the pixels belonging to the column and the fourth L-th column.

In the fourth field, the second dither matrix circuit 355 outputs the (4K-
(2L) column (4L-3), (4L-2) column, (4
The dither coefficients "3", "7", "2", and "6" are generated corresponding to each of the pixels belonging to the L-1) column and the fourth L column.

In the fourth field, the second dither matrix circuit 355 outputs the (4K-
(1) Row (4L-3), Row (4L-2), Row (4)
The dither coefficients "1", "5", "4", and "0" are generated corresponding to each of the pixels belonging to the (L-1) column and the fourth L column.

Further, in the fourth field, the second dither matrix circuit 355 outputs the fourth K
(4L-3) th column, (4L-2) th column, (4L
-1) The dither coefficients "2", "6", "3", and "7" are generated corresponding to the pixels belonging to the column and the fourth L column, respectively.

The second dither matrix circuit 355 repeatedly performs a series of dither coefficient generation operations in the first to fourth fields as shown in FIG. The selector 353 selects and adds the dither coefficient supplied from the first dither matrix circuit 354 when the dither matrix selection signal supplied from the low luminance component level discriminating circuit 352 is at the logical level “0”. To the vessel 356. On the other hand, when the dither matrix selection signal is at the logical level “1”, the selector 3
53 selects the dither coefficient supplied from the second dither matrix circuit 355 and supplies it to the adder 356.

That is, the lower 3 bits of each of the error diffusion processed pixel data ED corresponding to each pixel in the 4 row × 4 column pixel group.
All bits have the same value, and the values are "0", "2", "
In the case of any one of 4 "and" 6 ", the dither coefficient output from the first dither matrix circuit 354 in the form shown in Fig. 13 is supplied to the adder 356. On the other hand, 4 rows x If the lower 3 bits of each of the error diffusion processed pixel data ED corresponding to each pixel in the 4-column pixel group do not all have the same value, the output from the second dither matrix circuit 355 in the form shown in FIG. The dither coefficient thus obtained is supplied to the adder 356. Although the lower three bits of each of the error diffusion processing pixel data ED corresponding to each pixel in the 4 row × 4 column pixel group have the same value, value"
Even if none of "0", "2", "4", and "6" is satisfied, the dither coefficient output from the second dither matrix circuit 355 in the form shown in FIG. Supplied to

The adder 356 adds the dither coefficient represented by 3 bits as shown in FIG. 13 or 14 supplied from the selector 353 to the lower 3 bits of the error diffusion processed pixel data ED. . The adder 356 is
The result of this addition is supplied to the upper bit extraction circuit 357 as dither added pixel data. Upper bit extraction circuit 357
Extracts upper four bits from such dither-added pixel in data, and outputs it as a multi-gradation pixel data D _S.

As described above, the dither processing circuit 350 performs the dither processing by treating the 4 × 4 pixel group surrounded by the thick line in FIG. 12 as one display unit. That is, the lower 3 bits of each of the error diffusion processed pixel data ED corresponding to each of the 16 pixels in the 4 row × 4 column pixel group
The dither coefficients “0” to “7” represented by 3 bits are assigned to the bits and added as shown in FIG. 13 or FIG. As described above, the lower 3 bits of each of the error diffusion processing pixel data ED corresponding to each of the 16 pixels include:
When the dither coefficients “0” to “7” represented by 3 bits are added, 1) When a carry occurs only in the pixel to which the dither coefficient “7” is added, 2) The dither coefficients “6” and “7” In the case where carry occurs in a pixel to which "is added" 3) In the case where carry occurs in a pixel to which dither coefficients "5" to "7" are added 4) A pixel to which dither coefficients "4" to "7" are added 5) Carry occurs at the pixel to which dither coefficient "3" to "7" is added. 6) Carry at the pixel to which dither coefficient "2" to "7" is added. 7) When carry occurs in a pixel to which dither coefficients "1" to "7" are added. 8) When carry does not occur in all pixels. One of eight carry states occurs.

The effect of the carry is the adder 3
This is reflected in the upper 4 bits in the dither-added pixel data output from 56. Therefore, when viewing the pixel group of 4 rows × 4 columns as one display unit, eight kinds of combinations occur as the luminance represented by the upper 4 bits in the dither-added pixel data. That is, even in the multi-gradation processing pixel data D _S 4 bits even number of bits obtained by the upper bit extracting circuit 357, a luminance gradation number which can be expressed in 8-fold, i.e., 7-bit equivalent halftone The display becomes possible.

However, if a dither coefficient of "0" to "7" is added to each pixel position of the 4 row × 4 column pixel group and fixed, each pixel has no relation to the pixel data due to the influence of the carry as described above. A pattern (dither pattern) may be recognized as visual noise. Therefore, the dither processing circuit 3
In 50, the dither coefficient to be assigned to each of the 16 pixels in the 4 row × 4 column pixel group is changed for each field as shown in FIG.

As a result, all the lower 3 bits of each of the error diffusion processed pixel data ED corresponding to each of the 16 pixels in the 4 row × 4 column pixel group are “0”, “2”, “4”, “4”. If the value indicates any one of 6 ", the generation of the dither pattern is suppressed. However, all the lower three bits in each of the error diffusion processed pixel data ED are "
If the value indicates any one of 1 "," 3 "," 5 ", and" 7 ", a dither pattern occurs.

FIG. 15 shows a carry pattern indicating a carry from lower 3 bits to a higher 4 bits generated by addition of dither coefficients as shown in FIG. 13, and a dither pattern visually recognized by the carry pattern. FIG. In FIG. 15, for example, when the lower 3 bits of the error diffusion processing pixel data ED corresponding to each pixel in the 4 row × 4 column pixel group indicate “0”, the dither coefficient “0” is added to this.
No carry occurs even if any of .about. "7" is added. Therefore, there is no effect of carry on the upper 4 bits through the first to fourth fields. However, when the lower three bits of each of the error diffusion processed pixel data ED indicate "1", the dither coefficient "7" is added in each of the first to fourth fields as shown in FIG. The carry occurs only at the pixel position where Therefore, a checkered lattice-like dither pattern as shown in FIG. 15 occurs due to the afterimage phenomenon of the eyes between the first to fourth fields. When the lower three bits of each of the error diffusion processed pixel data ED indicate "2", the dither coefficients "6" and "7" in each of the first to fourth fields as shown in FIG. Carry is generated at each pixel position where is added. At this time, since the addition of these dither coefficients “7” and “6” is performed evenly once at 16 locations in the 4 × 4 pixel group through the first to fourth fields, a dither pattern is generated. do not do. or,
The lower 3 bits of each of the error diffusion processed pixel data ED are "
In the case of indicating "3", as shown in FIG. 15, in each of the first to fourth fields, the dither coefficients "5", "6",
And carry at the pixel position where "7" is added.
At this time, the addition of the dither coefficients “5”, “6”, and “7” is performed through a first field to a fourth field, and a part that is performed only once and a part that is performed twice are mixed. I have. Therefore, this appears as a checkerboard-like dither pattern as shown in FIG.

As described above, the error diffusion processed pixel data ED
If the lower 3 bits of the "1" are "0", "2", or "4", "6", the generation of the dither pattern can be suppressed.
In the case of 1 "," 3 "," 5 ", or" 7 ", generation of a dither pattern cannot be suppressed.
In 50, if the lower three bits as the low luminance component of the error diffusion processed pixel data ED are “1”, “3”, “5”, or “7”, the first dither matrix circuit 35
The dither addition is performed using the dither coefficient generated by the second dither matrix circuit 355 instead of 4.
That is, at this time, dither addition using a dither matrix table as shown in FIG. 14 having a different dither coefficient assignment method from that of the dither matrix table shown in FIG. 13 is performed.

FIG. 16 shows a pattern indicating the carry from the lower 3 bits to the upper 4 bits generated when the dither coefficient is added according to the dither matrix table shown in FIG. FIG. 4 is a diagram showing a dither pattern to be performed. In FIG. 16, 4 rows × 4
When the lower 3 bits of the error diffusion processing pixel data ED corresponding to each pixel in the column pixel group are “1”, the pixel to which the dither coefficient “7” is added in each of the first to fourth fields. Carry occurs only at the position. Therefore, the first to fourth
Due to the afterimage phenomenon of the eyes between the fields, a relatively thin checkered dither pattern as shown in FIG. 16 occurs. If the lower 3 bits of the error diffusion processed pixel data ED are "3", the pixels to which the dither coefficients "5", "6" and "7" are added in each of the first to fourth fields. Carry occurs at each position. Therefore, a checkered comparatively thin dither pattern as shown in FIG. 16 occurs due to the afterimage phenomenon of the eyes between the first to fourth fields. or,
When the lower 3 bits of the error diffusion processed pixel data ED are "5", the dither coefficients "3", "4", "5", "6" and "7" are respectively used in the first to fourth fields. Carry occurs at each pixel position where "is added. Therefore, a relatively thin checkered dither pattern as shown in FIG. 16 occurs due to the afterimage phenomenon of the eyes between the first to fourth fields.
The lower 3 bits of the error diffusion processed pixel data ED are "
If it is 7 ", the dither coefficients" 1 "," 2 "," 3 "," 4 "," 5 "," 6 "and" 7 "are added in each of the first to fourth fields. A carry occurs at each pixel position, and a relatively thin checkered dither pattern as shown in FIG. 16 occurs due to the afterimage phenomenon of the eyes between the first to fourth fields.

As described above, the second dither matrix circuit 3
Also in the dither processing using the dither coefficient generated at 55, the lower 3 bits of the error diffusion processing pixel data ED are "
In the case of any of 1 "," 3 "," 5 ", or" 7 ", a thin checkered dither pattern is visible as shown in Fig. 16. However, such a checkered dither pattern is visible. 15 has less visual noise than a checkerboard pattern as shown in Fig. 15. As a result, dither noise is reduced.

In the above embodiment, the two dither matrix tables shown in FIG. 13 and FIG. 14 are switched according to the level of the low luminance component in the error diffusion processed pixel data ED. The dither matrix table is not limited to two systems. That is,
There are prepared 3 to 8 dither matrix tables in which dither coefficients are assigned to respective pixel positions in a 4 row × 4 column pixel group differently from each other. They select and use the ones that suit.

[0076]

As described in detail above, in the dither processing circuit of the display device according to the present invention, each pixel in the pixel group on the display is controlled according to the luminance level represented by the pixel data corresponding to the video signal. The value of the dither coefficient to be assigned has been changed.

Therefore, according to the present invention, it is possible to perform a good dither process while suppressing the generation of a dither pattern.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a plasma display device equipped with a dither processing circuit according to the present invention.

FIG. 2 is a diagram showing an internal configuration of a data conversion circuit 30.

FIG. 3 is a diagram showing an internal configuration of an ABL circuit 31;

FIG. 4 is a diagram showing conversion characteristics in a data conversion circuit 312.

FIG. 5 is a diagram showing data conversion characteristics in a first data conversion circuit 32;

FIG. 6 is a diagram showing a conversion table and a light emission drive pattern of a second data conversion circuit 34;

FIG. 7 is a diagram showing a light emission drive format of the plasma display device shown in FIG.

FIG. 8 is a diagram showing application timings of various drive pulses applied to the PDP within one field display period.

FIG. 9 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

FIG. 10 is a diagram for explaining the operation of the error diffusion processing circuit 330.

FIG. 11 is a diagram showing an internal configuration of a dither processing circuit 350.

FIG. 12 is a diagram showing the correspondence between each pixel G in the PDP 10 and a pixel group of 4 rows × 4 columns.

FIG. 13 is a diagram showing a dither matrix table of dither coefficients generated by a first dither matrix circuit 354.

14 is a diagram illustrating a dither matrix table of dither coefficients generated by a second dither matrix circuit 355. FIG.

FIG. 15 is a diagram showing a carry pattern from lower 3 bits to upper 4 bits generated by adding dither coefficients as shown in FIG. 13, and a dither pattern visually recognized by the carry pattern.

FIG. 16 is a diagram showing a carry pattern from lower 3 bits to upper 4 bits generated by addition of dither coefficients as shown in FIG. 14, and a dither pattern visually recognized by the carry pattern.

[Description of Signs of Main Parts] 350 Dither processing circuit 351 Low luminance component extraction circuit 352 Low luminance component level discriminating circuit 353 Selector 354 First dither matrix circuit 355 Second dither matrix circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/28 G09G 3/28 K

Claims (6)

[Claims] 1. A dither processing circuit of a display device for displaying a two-dimensional image on a display screen according to a video signal composed of continuously generated unit screen information signals, wherein each of a plurality of pixel groups on the screen is Dither coefficient generating means for generating a dither coefficient corresponding to each pixel position, and an adder for adding the dither coefficient to pixel data based on the video signal corresponding to each of the pixels and outputting the result as dither processed pixel data The dither processing circuit, wherein the dither coefficient generation means changes the dither coefficient to be generated according to a luminance level represented by the pixel data. 2. The dither processing circuit according to claim 1, wherein the dither coefficient generation means further changes the dither coefficient to be generated for each unit screen information signal. 3. The dither processing circuit according to claim 1, wherein the luminance level is a level of a low luminance component represented by the pixel data. 4. The dither processing circuit according to claim 1, wherein each of the pixel groups is a set of the pixels including N rows and M columns adjacent to each other on the screen. 5. A dither coefficient generating means, comprising: a first dither matrix circuit for generating a first dither matrix in which a plurality of coefficients having mutually different coefficient values correspond to respective pixel positions in the pixel group; A second dither matrix in which assignment to each pixel position in each of the pixel groups is different from that of the first dither matrix;
A second dither matrix circuit for generating a dither matrix; and selecting one of the first dither matrix and the second dither matrix according to a luminance level represented by the pixel data, and using the selected one as the dither coefficient. 2. The dither processing circuit according to claim 1, further comprising: a selector for supplying a signal to the input device. 6. The first dither matrix and the second dither matrix.
6. The dither processing circuit according to claim 5, wherein each dither matrix has a different assignment of each of the coefficients to each pixel position in the pixel group for each of the unit screen information signals.