JP2008193132A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP2008193132A JP2008193132A JP2008127142A JP2008127142A JP2008193132A JP 2008193132 A JP2008193132 A JP 2008193132A JP 2008127142 A JP2008127142 A JP 2008127142A JP 2008127142 A JP2008127142 A JP 2008127142A JP 2008193132 A JP2008193132 A JP 2008193132A
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- Prior art keywords
- layer
- wiring board
- build
- metal foil
- core substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】本発明に係る配線基板の製造方法は、コア基板の両面にビルドアップ層を形成してなる配線基板の製造方法において、前記ビルドアップ層を形成する際に、銅よりも小さな熱膨張係数を有する金属箔を、ビルドアップ層に形成される配線パターンと干渉しない配置でビルドアップ層に組み込むことを要件とする。
【選択図】図11
Description
また、金属箔の片面に接着剤層が被着された接着剤付金属箔をビルドアップ層に積層することにより、ビルドアップ層に金属箔を組み込むことを特徴とする。
図1〜4は、本発明に係る配線基板の製造方法を示す説明図である。図1(a)は、本発明方法において特徴的な製造工程であり、支持体100の両面に接着フィルム40を介して、第1の金属層41と第2の金属層42を積層して被覆する工程を示す。
本実施形態は、図12に示す方法によってコア基板10を形成した後、低熱膨張係数を有する金属箔をビルドアップ層に組み込むことによって、半導体チップの熱膨張係数に近づけた配線基板を製造する方法に関するものである。
Claims (2)
- コア基板の両面にビルドアップ層を形成してなる配線基板の製造方法において、
前記ビルドアップ層を形成する際に、銅よりも小さな熱膨張係数を有する金属箔を、ビルドアップ層に形成される配線パターンと干渉しない配置でビルドアップ層に組み込むことを特徴とする配線基板の製造方法。 - 金属箔の片面に接着剤層が被着された接着剤付金属箔をビルドアップ層に積層することにより、ビルドアップ層に金属箔を組み込むことを特徴とする請求項1記載の配線基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008127142A JP4610633B2 (ja) | 2008-05-14 | 2008-05-14 | 配線基板の製造方法 |
Applications Claiming Priority (1)
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JP2008127142A JP4610633B2 (ja) | 2008-05-14 | 2008-05-14 | 配線基板の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004572126A Division JP4143609B2 (ja) | 2003-05-23 | 2003-05-23 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008193132A true JP2008193132A (ja) | 2008-08-21 |
JP4610633B2 JP4610633B2 (ja) | 2011-01-12 |
Family
ID=39752852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008127142A Expired - Fee Related JP4610633B2 (ja) | 2008-05-14 | 2008-05-14 | 配線基板の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4610633B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013131777A (ja) * | 2009-04-02 | 2013-07-04 | Murata Mfg Co Ltd | 回路基板 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6433945A (en) * | 1987-07-29 | 1989-02-03 | Hitachi Chemical Co Ltd | Wiring board for mounting semiconductor element |
JP2002271040A (ja) * | 2001-03-07 | 2002-09-20 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
-
2008
- 2008-05-14 JP JP2008127142A patent/JP4610633B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6433945A (en) * | 1987-07-29 | 1989-02-03 | Hitachi Chemical Co Ltd | Wiring board for mounting semiconductor element |
JP2002271040A (ja) * | 2001-03-07 | 2002-09-20 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013131777A (ja) * | 2009-04-02 | 2013-07-04 | Murata Mfg Co Ltd | 回路基板 |
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JP4610633B2 (ja) | 2011-01-12 |
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