JP2008187118A - 半導体記憶装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 230000015556 catabolic process Effects 0.000 claims description 118
- 230000015654 memory Effects 0.000 claims description 104
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000006870 function Effects 0.000 abstract description 21
- 230000002093 peripheral effect Effects 0.000 description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 44
- 229910052710 silicon Inorganic materials 0.000 description 44
- 239000010703 silicon Substances 0.000 description 44
- 238000000034 method Methods 0.000 description 40
- 239000007790 solid phase Substances 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 description 23
- 239000013078 crystal Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 230000010354 integration Effects 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 230000006866 deterioration Effects 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 239000007858 starting material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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Abstract
【解決手段】本発明の1態様による半導体記憶装置は、半導体基板に部分的に開口部を有する埋め込み絶縁膜を介して設けられた第1半導体領域と、前記第1半導体領域とは異なる、埋め込み絶縁膜を有さない前記半導体基板の領域に設けられた第2半導体領域と、前記第1半導体領域の前記開口部上を除く前記埋め込み絶縁膜の上方の領域に設けられた第1半導体素子と、前記第1半導体領域の前記埋め込み絶縁膜の開口部上の領域を含む領域に設けられた第2半導体素子と、前記半導体基板の前記第2半導体領域に設けられた第3半導体素子とを具備する。
【選択図】図2
Description
本発明の第1の実施形態による半導体記憶装置を不揮発性半導体記憶装置を例に説明する。図1は、本実施形態による不揮発性半導体記憶装置、例えば、NAND型フラッシュメモリ100の一例を説明するために示す平面図であり、図1(a)は全体図、図1(b)はメモリセル部の拡大図である。
例えば、tSi=5〜100nm、tBOX=10〜200nm、tOx1=20〜60nm、tOx2=3〜9nm、c=2.22、a=10〜200nmとすると、基板10の削れ量は、E1=75.6〜651.8nmになる。
taSi≧(1−d)×E1
とする。ここで、dは、アモルファスシリコン16aを結晶化させる際の体積収縮率である。
E2=tOx1×(1−1/c)
である。ここで、tOx1は、高耐圧トランジスタHTのゲート絶縁膜厚であり、例えば、tOx1=20〜60nmであり、cは、シリコン基板が熱酸化によりシリコン酸化膜となる際の厚さ方向の膨張係数である。
本発明の第2の実施形態による半導体記憶装置200、例えば、NAND型フラッシュメモリの断面構造の一例を図5に示す。本実施形態によるNAND型フラッシュメモリ200は、メモリセルアレイを配置するSOI部112を備えた部分SOI基板に設けられる。メモリセル領域110には、セルトランジスタCT及び選択トランジスタSTが設けられ、そして周辺素子領域120には、高耐圧トランジスタHT及び低耐圧トランジスタLTが設けられる。
E3=tBOX+a
である。ここで、tBOXは、BOX膜厚であり、aは、この後で述べる平坦化工程における削れ量である。この工程で、図示しないが第1のマスクを使用する。本実施形態では、SOI層を固相エピタキシャル成長させる時に種結晶になる開口領域114を掘り下げずに突起するように、すなわち、メサ状に残す。第1の実施形態と同様に、後の工程(3)で固相エピタキシャル成長時にBOX上に結晶性の良い単結晶シリコンを形成するために、開口領域114の間隔は、4〜5μmとすることが好ましい。
taSi=(1−d)×(tSi+(tOx1+tOx2)/c)
とする。ここで、dは、アモルファスシリコンを結晶化させる際の体積収縮率であり、tSiは、SOI層16の厚さであり、tOx1は、高耐圧トランジスタのゲート絶縁膜20の厚さであり、tOx2は、メモリセル領域及び低耐圧トランジスタのゲート絶縁膜22a,22bの厚さであり、cは、シリコン基板を熱酸化によりシリコン酸化膜にする際の厚さ方向の膨張係数である。
本発明の第3の実施形態による半導体記憶装置、例えば、NAND型フラッシュメモリ300の断面構造の一例を図7に示す。本実施形態によるNAND型フラッシュメモリ300は、第2の実施形態とほぼ同じであるが、選択トランジスタST、高耐圧トランジスタHT及び低耐圧トランジスタLTをいずれもバルク半導体基板10上に配置し、セルトランジスタCTをSOI部112のSOI層16上に配置した半導体記憶装置である。
E4>tBOX+tSi
である。ここで、tBOXは、BOX膜厚であり、tSiは、SOI層の膜厚である。この工程で、図示しないが第1のマスクを使用する。本実施形態では、SOI層を固相エピタキシャル成長させる時に種結晶になる開口領域114は、第2の実施形態と同様に、突起するように、すなわちメサ状に残すが、第2の実施形態よりも高く形成する。開口領域114の間隔は、第1の実施形態と同様に、後の工程で固相エピタキシャル成長時にBOX上に結晶性の良い単結晶シリコンを形成するために、4〜5μmとすることが好ましい。
taSi≧(1−d)×tSi
とする。ここで、dは、アモルファスシリコンを結晶化させる際の体積収縮率であり、tSiは、SOI層16の厚さである。
本発明の第4の実施形態による半導体記憶装置は、ゲート絶縁膜形成までの工程で、例えば、CMPによる平坦化を用いないで製造することが可能な半導体記憶装置である。本実施形態による半導体記憶装置400、例えば、NAND型フラッシュメモリの断面構造の一例を図10に示す。
E5=tBOX
である。ここで、tBOXは、BOX膜厚である。
taSi≧(1−d)×tSi
とする。ここで、dは、アモルファスシリコンを結晶化させる際の体積収縮率であり、tSiは、SOI層16の厚さである。
Claims (5)
- 半導体基板に部分的に開口部を有する埋め込み絶縁膜を介して設けられた第1半導体領域と、
前記第1半導体領域とは異なる、埋め込み絶縁膜を有さない前記半導体基板の領域に設けられた第2半導体領域と、
前記第1半導体領域の前記開口部上を除く前記埋め込み絶縁膜の上方の領域に設けられた第1半導体素子と、
前記第1半導体領域の前記埋め込み絶縁膜の開口部上の領域を含む領域に設けられた第2半導体素子と、
前記半導体基板の前記第2半導体領域に設けられた第3半導体素子と
を具備することを特徴とする半導体記憶装置。 - 前記第3半導体素子は、高耐圧トランジスタ及び低耐圧トランジスタを含み、前記高耐圧トランジスタ及び前記低耐圧トランジスタのゲート絶縁膜と該ゲート絶縁膜上の電極との界面の高さは略等しく、前記高耐圧トランジスタ及び前記低耐圧トランジスタのゲート絶縁膜と前記第2半導体領域の前記半導体基板との界面の高さは、前記高耐圧トランジスタの方が低いことを特徴とする、請求項1に記載の半導体記憶装置。
- 前記第1半導体素子、前記第2半導体素子及び前記第3半導体素子のゲート絶縁膜と該ゲート絶縁膜上の電極との界面の高さがそれぞれ略等しいことを特徴とする、請求項1又は2に記載の半導体記憶装置。
- 前記第1半導体素子は、メモリセルトランジスタであり、前記第2半導体素子は、前記メモリセルトランジスタを選択する選択トランジスタであることを特徴とする、請求項1ないし3のいずれかに記載の半導体記憶装置。
- 前記埋め込み絶縁膜の開口部上に、第1半導体素子、前記第2半導体素子、前記第3半導体素子のいずれかの拡散層が設けられていることを特徴とする請求項2ないし4のいずれかに記載の半導体記憶装置。
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---|---|---|---|
JP2007021170A JP4772709B2 (ja) | 2007-01-31 | 2007-01-31 | 半導体記憶装置 |
US12/022,382 US7804133B2 (en) | 2007-01-31 | 2008-01-30 | Semiconductor storage device and manufacturing method thereof |
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JP2007021170A JP4772709B2 (ja) | 2007-01-31 | 2007-01-31 | 半導体記憶装置 |
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Publication Number | Publication Date |
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JP2008187118A true JP2008187118A (ja) | 2008-08-14 |
JP4772709B2 JP4772709B2 (ja) | 2011-09-14 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011243657A (ja) * | 2010-05-14 | 2011-12-01 | Mitsumi Electric Co Ltd | 半導体装置の製造方法 |
JP2012028420A (ja) * | 2010-07-20 | 2012-02-09 | Toshiba Corp | 半導体装置およびその製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110005090A (ko) * | 2009-07-09 | 2011-01-17 | 삼성전자주식회사 | 액정표시장치, 액정구동장치 및 액정표시장치 구동방법 |
KR101570142B1 (ko) * | 2009-08-25 | 2015-11-20 | 삼성전자주식회사 | 액정표시장치 및 액정표시장치의 구동방법 |
KR20120097206A (ko) * | 2011-02-24 | 2012-09-03 | 삼성전자주식회사 | 가변 저항 메모리 소자 및 그 제조 방법 |
KR20120131879A (ko) * | 2011-05-26 | 2012-12-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8822319B2 (en) * | 2012-09-12 | 2014-09-02 | Ememory Technology Inc. | Method of manufacturing non-volatile memory |
US10504912B2 (en) * | 2017-07-28 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology |
CN116798863A (zh) * | 2023-08-18 | 2023-09-22 | 合肥晶合集成电路股份有限公司 | 半导体器件的制备方法 |
Citations (3)
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JPH09260617A (ja) * | 1996-03-26 | 1997-10-03 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2001203285A (ja) * | 1999-12-24 | 2001-07-27 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2006073939A (ja) * | 2004-09-06 | 2006-03-16 | Toshiba Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
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JP2003203967A (ja) | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分soiウェーハの製造方法、半導体装置及びその製造方法 |
US7141116B2 (en) | 2004-09-08 | 2006-11-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a silicon structure |
JP2006165435A (ja) * | 2004-12-10 | 2006-06-22 | Toshiba Corp | 半導体装置及びその製造方法 |
US7459748B2 (en) * | 2005-10-17 | 2008-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP2007165543A (ja) * | 2005-12-13 | 2007-06-28 | Toshiba Corp | 半導体記憶装置の製造方法 |
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- 2007-01-31 JP JP2007021170A patent/JP4772709B2/ja not_active Expired - Fee Related
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260617A (ja) * | 1996-03-26 | 1997-10-03 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2001203285A (ja) * | 1999-12-24 | 2001-07-27 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2006073939A (ja) * | 2004-09-06 | 2006-03-16 | Toshiba Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011243657A (ja) * | 2010-05-14 | 2011-12-01 | Mitsumi Electric Co Ltd | 半導体装置の製造方法 |
JP2012028420A (ja) * | 2010-07-20 | 2012-02-09 | Toshiba Corp | 半導体装置およびその製造方法 |
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JP4772709B2 (ja) | 2011-09-14 |
US7804133B2 (en) | 2010-09-28 |
US20080179677A1 (en) | 2008-07-31 |
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