JP2008171977A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008171977A5 JP2008171977A5 JP2007003184A JP2007003184A JP2008171977A5 JP 2008171977 A5 JP2008171977 A5 JP 2008171977A5 JP 2007003184 A JP2007003184 A JP 2007003184A JP 2007003184 A JP2007003184 A JP 2007003184A JP 2008171977 A5 JP2008171977 A5 JP 2008171977A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- standard cell
- diffusion region
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 243
- 239000004065 semiconductor Substances 0.000 claims description 91
- 229910052751 metal Inorganic materials 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000872 buffer Substances 0.000 claims description 13
- 230000001902 propagating effect Effects 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims 1
- 239000011295 pitch Substances 0.000 description 148
- 230000000694 effects Effects 0.000 description 13
- 230000007423 decrease Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000149 argon plasma sintering Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007003184A JP2008171977A (ja) | 2007-01-11 | 2007-01-11 | 半導体集積回路のレイアウト構造 |
| US11/968,894 US20080169487A1 (en) | 2007-01-11 | 2008-01-03 | Layout structure of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007003184A JP2008171977A (ja) | 2007-01-11 | 2007-01-11 | 半導体集積回路のレイアウト構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008171977A JP2008171977A (ja) | 2008-07-24 |
| JP2008171977A5 true JP2008171977A5 (https=) | 2009-07-30 |
Family
ID=39617086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007003184A Pending JP2008171977A (ja) | 2007-01-11 | 2007-01-11 | 半導体集積回路のレイアウト構造 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20080169487A1 (https=) |
| JP (1) | JP2008171977A (https=) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5410082B2 (ja) * | 2008-12-12 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| WO2010122754A1 (ja) * | 2009-04-22 | 2010-10-28 | パナソニック株式会社 | 半導体集積回路 |
| JP2011242541A (ja) * | 2010-05-17 | 2011-12-01 | Panasonic Corp | 半導体集積回路装置、および標準セルの端子構造 |
| US8507957B2 (en) * | 2011-05-02 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layouts with power rails under bottom metal layer |
| JP2013030602A (ja) * | 2011-07-28 | 2013-02-07 | Panasonic Corp | 半導体集積回路装置 |
| JP2013183123A (ja) * | 2012-03-05 | 2013-09-12 | Elpida Memory Inc | 半導体装置及びその設計方法 |
| US9318607B2 (en) * | 2013-07-12 | 2016-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US9672316B2 (en) * | 2013-07-17 | 2017-06-06 | Arm Limited | Integrated circuit manufacture using direct write lithography |
| US9331016B2 (en) * | 2013-07-25 | 2016-05-03 | Qualcomm Incorporated | SOC design with critical technology pitch alignment |
| JP6281571B2 (ja) * | 2013-08-28 | 2018-02-21 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| KR102083388B1 (ko) | 2013-09-24 | 2020-03-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| CN104517963B (zh) * | 2013-09-27 | 2018-09-18 | 恩智浦美国有限公司 | 状态保持电源选通单元 |
| US9431383B2 (en) | 2014-07-22 | 2016-08-30 | Samsung Electronics Co., Ltd. | Integrated circuit, semiconductor device based on integrated circuit, and standard cell library |
| US9852252B2 (en) | 2014-08-22 | 2017-12-26 | Samsung Electronics Co., Ltd. | Standard cell library and methods of using the same |
| US9607988B2 (en) | 2015-01-30 | 2017-03-28 | Qualcomm Incorporated | Off-center gate cut |
| US9865544B2 (en) | 2015-10-05 | 2018-01-09 | Samsung Electronics Co., Ltd. | Semiconductor device layout having a power rail |
| US9793211B2 (en) * | 2015-10-20 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual power structure with connection pins |
| US10510688B2 (en) * | 2015-10-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via rail solution for high power electromigration |
| CN108701653B (zh) * | 2016-02-25 | 2022-07-29 | 株式会社索思未来 | 半导体集成电路装置 |
| KR102497218B1 (ko) | 2016-04-29 | 2023-02-07 | 삼성전자 주식회사 | 복합 논리 셀을 포함하는 집적 회로 |
| US10236886B2 (en) | 2016-12-28 | 2019-03-19 | Qualcomm Incorporated | Multiple via structure for high performance standard cells |
| US12456663B2 (en) | 2017-02-08 | 2025-10-28 | Samsung Electronics Co., Ltd. | Integrated circuit having contact jumper |
| US10319668B2 (en) | 2017-02-08 | 2019-06-11 | Samsung Electronics Co., Ltd. | Integrated circuit having contact jumper |
| US10790272B2 (en) * | 2017-08-02 | 2020-09-29 | Qualcomm Incorporated | Manufacturability (DFM) cells in extreme ultra violet (EUV) technology |
| WO2019142333A1 (ja) * | 2018-01-19 | 2019-07-25 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| KR102465964B1 (ko) | 2018-05-18 | 2022-11-10 | 삼성전자주식회사 | 다중 높이 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법 |
| US10742218B2 (en) * | 2018-07-23 | 2020-08-11 | International Business Machines Corpoartion | Vertical transport logic circuit cell with shared pitch |
| US10922465B2 (en) * | 2018-09-27 | 2021-02-16 | Arm Limited | Multi-input logic circuitry |
| US10629526B1 (en) * | 2018-10-11 | 2020-04-21 | Nxp Usa, Inc. | Transistor with non-circular via connections in two orientations |
| JP7364922B2 (ja) * | 2018-12-26 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US11735525B2 (en) * | 2019-10-21 | 2023-08-22 | Tokyo Electron Limited | Power delivery network for CFET with buried power rails |
| US11756876B2 (en) * | 2020-04-01 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor devices having power rails and signal tracks arranged in different layer |
| US11222831B2 (en) * | 2020-06-04 | 2022-01-11 | Samsung Electronics Co., Ltd. | Stacked integrated circuit devices |
| WO2022138324A1 (ja) * | 2020-12-25 | 2022-06-30 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| KR20220115400A (ko) | 2021-02-10 | 2022-08-17 | 삼성전자주식회사 | 가산기 셀 및 이를 포함하는 집적 회로 |
| TWI909004B (zh) * | 2021-03-05 | 2025-12-21 | 日商住友電工器件創新股份有限公司 | 半導體裝置 |
| CN115659901B (zh) * | 2022-09-07 | 2023-07-07 | 上海为旌科技有限公司 | 一种芯片物理设计的距离布线优化方法和装置 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3335460B2 (ja) * | 1994-03-09 | 2002-10-15 | 株式会社リコー | スタンダードセルを有する半導体装置 |
| JPH08227428A (ja) * | 1995-02-20 | 1996-09-03 | Matsushita Electric Ind Co Ltd | プリント基板ｃａｄ装置 |
| US6480995B1 (en) * | 1996-04-15 | 2002-11-12 | Altera Corporation | Algorithm and methodology for the polygonalization of sparse circuit schematics |
| US6336207B2 (en) * | 1997-05-27 | 2002-01-01 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuit |
| US6016390A (en) * | 1998-01-29 | 2000-01-18 | Artisan Components, Inc. | Method and apparatus for eliminating bitline voltage offsets in memory devices |
| JP2002026297A (ja) * | 2000-07-07 | 2002-01-25 | Mitsubishi Electric Corp | 半導体装置 |
| TW200506664A (en) * | 2003-08-01 | 2005-02-16 | Ali Corp | An integrated circuit layout design method and layout design software capable of performing automatic layout |
| US7343570B2 (en) * | 2005-11-02 | 2008-03-11 | International Business Machines Corporation | Methods, systems, and media to improve manufacturability of semiconductor devices |
-
2007
- 2007-01-11 JP JP2007003184A patent/JP2008171977A/ja active Pending
-
2008
- 2008-01-03 US US11/968,894 patent/US20080169487A1/en not_active Abandoned
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008171977A5 (https=) | ||
| JP2008171977A (ja) | 半導体集積回路のレイアウト構造 | |
| USRE49821E1 (en) | Semiconductor integrated circuit | |
| KR101913457B1 (ko) | 선형 ＦｉｎＦＥＴ 구조들을 갖는 회로들 | |
| US6271548B1 (en) | Master slice LSI and layout method for the same | |
| CN109962072B (zh) | 半导体装置 | |
| CN101315928B (zh) | 具有单元金氧半组件的集成电路的布局方法 | |
| US9846757B2 (en) | Cell grid architecture for FinFET technology | |
| TW201830638A (zh) | 半導體裝置 | |
| KR100473457B1 (ko) | 반도체 기억장치 | |
| JP7817572B2 (ja) | 半導体集積回路装置 | |
| US8178904B2 (en) | Gate array | |
| TWI866118B (zh) | 半導體裝置和準位位移電路 | |
| TW202349251A (zh) | 積體電路系統及積體電路的設計方法 | |
| TWI864518B (zh) | 半導體結構 | |
| US8994098B2 (en) | Semiconductor device including pillar transistors | |
| CN118318295A (zh) | 半导体集成电路装置 | |
| TWI700833B (zh) | 元件格佈局結構與形成元件格的方法 | |
| US20250113478A1 (en) | Bit line with non-uniform width in a memory array | |
| US20260096081A1 (en) | Semiconductor memory device | |
| WO2024116853A1 (ja) | 半導体集積回路装置 | |
| CN106601732A (zh) | 鳍式场效晶体管的元件格结构 | |
| TW202538742A (zh) | 記憶體晶片 | |
| WO2025004736A1 (ja) | 半導体記憶装置 | |
| JP2005333084A (ja) | 半導体記憶装置 |