JP2008085857A - Voltage-controlled oscillation circuit - Google Patents

Voltage-controlled oscillation circuit Download PDF

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JP2008085857A
JP2008085857A JP2006265421A JP2006265421A JP2008085857A JP 2008085857 A JP2008085857 A JP 2008085857A JP 2006265421 A JP2006265421 A JP 2006265421A JP 2006265421 A JP2006265421 A JP 2006265421A JP 2008085857 A JP2008085857 A JP 2008085857A
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voltage
oscillation circuit
variable capacitance
controlled oscillation
switch element
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Yoshichika Takahashi
佳周 高橋
Tomoki Oda
知己 織田
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Mitsumi Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillation circuit capable of preventing a current leak to shorten a time for stabilizing an oscillation frequency when turning on a power supply. <P>SOLUTION: The voltage-controlled oscillation circuit has a crystal oscillator XTAL, inverters M3, M4, and variable capacitive elements CV1, CV2, applies temperature compensation voltages outputted by a temperature compensation circuit 21 to the variable capacitive element through low-pass filters Ra, Ca, and compensate a temperature in the crystal oscillator for stabilizing an oscillation frequency. In the voltage-controlled oscillation circuit, variable capacitive elements for capacity adjustment CV1a-CV1d, CV2a-CV2d having first switch elements M1a-M1d, M2a-M2d are provided in parallel in the variable capacitive elements, and the first switch element is turned on or off for adjusting capacities of the variable capacitive elements. In this case, there are shift means S1a-S1d, S2a-S2d for raising voltages at the connection point between the variable capacitive elements for capacity adjustment and the first switch element, when the first switch element is turned off. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電圧制御型発振回路に関し、水晶振動子の温度補償を行って発振周波数を安定化する電圧制御型発振回路に関する。   The present invention relates to a voltage controlled oscillation circuit, and more particularly to a voltage controlled oscillation circuit that stabilizes an oscillation frequency by performing temperature compensation of a crystal resonator.

図６は、従来の電圧制御型発振回路（ＶＣＸＯ）の一例の回路構成図を示す。同図中、半導体集積回路１０内の温度補償回路１１は、周囲温度に応じて水晶振動子ＸＴＡＬの温度特性を補償する温度補償電圧ＶＴＣを発生し、抵抗Ｒａ及びコンデンサＣａで構成される低域フィルタを通し、抵抗Ｒｂ，Ｒｃを経て可変容量素子（可変容量ダイオード）ＣＶ１，ＣＶ２に印加する。   FIG. 6 shows a circuit configuration diagram of an example of a conventional voltage-controlled oscillation circuit (VCXO). In the figure, a temperature compensation circuit 11 in the semiconductor integrated circuit 10 generates a temperature compensation voltage VTC that compensates for the temperature characteristics of the crystal resonator XTAL in accordance with the ambient temperature, and is a low-frequency region composed of a resistor Ra and a capacitor Ca. The filter is applied to the variable capacitance elements (variable capacitance diodes) CV1 and CV2 through the resistors Rb and Rc.

可変容量素子ＣＶ１には容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄが並列に設けられ、可変容量素子ＣＶ２には容量調整用可変容量素子ＣＶ２ａ〜ＣＶ２ｄが並列に設けられている。可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄのカソードにはｎチャネルＦＥＴ（電界効果トランジスタ）Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインが接続され、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのソースは接地されている。   The variable capacitance element CV1 is provided with capacitance adjustment variable capacitance elements CV1a to CV1d in parallel, and the variable capacitance element CV2 is provided with capacitance adjustment variable capacitance elements CV2a to CV2d in parallel. The drains of n-channel FETs (field effect transistors) M1a to M1d and M2a to M2d are connected to the cathodes of the variable capacitance elements CV1a to CV1d and CV2a to CV2d, and the sources of the FETs M1a to M1d and M2a to M2d are grounded.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレイン，ソース間は抵抗Ｒ１ａ〜Ｒ１ｄ，Ｒ２ａ〜Ｒ２ｄで接続されており、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄそれぞれはゲートに制御信号を供給されてオン／オフを制御される。なお、上記制御信号は予めＲＯＭに登録されており、制御信号によりＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのいずれかをオンすることで、所望の容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄを可変容量素子ＣＶ１に並列接続して容量調整を行っている。   The drains and sources of the FETs M1a to M1d and M2a to M2d are connected by resistors R1a to R1d and R2a to R2d. Each of the FETs M1a to M1d and M2a to M2d is supplied with a control signal to the gate and controlled on / off. The The control signal is registered in advance in the ROM, and the desired capacitance adjusting variable capacitance elements CV1a to CV1d and CV2a to CV2d are variable by turning on any of the FETs M1a to M1d and M2a to M2d according to the control signal. Capacitance adjustment is performed in parallel with the capacitive element CV1.

半導体集積回路１０の外部には水晶振動子ＸＴＡＬが設けられている。水晶振動子ＸＴＡＬの両端は端子１２ａ，１２ｂを介して半導体集積回路１０内の可変容量素子ＣＶ１，ＣＶ２に接続されると共に、コンデンサＣ１とｐチャネルＦＥＴＭ３及びｎチャネルＦＥＴＭ４で構成される帰還抵抗ＲＦＢ付きのインバータと抵抗ＲｄとコンデンサＣ２との直列接続回路によって接続されている。   A crystal resonator XTAL is provided outside the semiconductor integrated circuit 10. Both ends of the crystal resonator XTAL are connected to variable capacitance elements CV1 and CV2 in the semiconductor integrated circuit 10 via terminals 12a and 12b, and have a feedback resistor RFB composed of a capacitor C1, a p-channel FET M3, and an n-channel FET M4. Are connected by a series connection circuit of an inverter, a resistor Rd, and a capacitor C2.

この電圧制御型発振回路は、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に帰還抵抗ＲＦＢで接続して帰還をかけることで負性抵抗回路を構成しており、可変容量素子ＣＶ１とコンデンサＣ１の直列容量と、可変容量素子ＣＶ２とコンデンサＣ２の直列容量と、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に接続された水晶振動子ＸＴＡＬのインダクタンス成分で発振するコルピッツ発振回路を構成しており、水晶振動子の温度補償を行うことで発振周波数を安定化している。   This voltage-controlled oscillation circuit forms a negative resistance circuit by applying feedback by connecting a feedback resistor RFB between the input and output terminals of the inverters of the FETs M3 and M4, and the variable capacitance element CV1 and the capacitor C1 are connected in series. A Colpitts oscillation circuit that oscillates with the capacitance, the series capacitance of the variable capacitance element CV2 and the capacitor C2, and the inductance component of the crystal resonator XTAL connected between the input and output terminals of the inverters of the FETs M3 and M4 is configured. The oscillation frequency is stabilized by performing temperature compensation of the child.

なお、特許文献１には、帰還抵抗を印加電圧に応じて変化させることにより、制御信号に対して任意の特性で発振周波数が変化するように、制御電圧を非線型増幅する非線型増幅手段を設けた電圧制御発振回路が記載されている。
特開２００６−２５１４１号公報 Patent Document 1 discloses a nonlinear amplifying means for nonlinearly amplifying a control voltage so that an oscillation frequency changes with an arbitrary characteristic with respect to a control signal by changing a feedback resistor according to an applied voltage. The provided voltage controlled oscillator circuit is described.
JP 2006-25141 A

図６の従来回路において、例えばＦＥＴＭ１ｄがオフの場合、端子１２ａの電圧ＶＸ２は、温度補償回路１１の出力する温度補償電圧ＶＴＣを基準として図７に示すように振動する。また、ＦＥＴＭ１ｄのドレイン電圧ＶＮＭは、接地レベル（ＧＮＤ）を基準として図７に示すように振動する。この状況では、ドレイン電圧ＶＮＭが接地レベルから０．７Ｖ以下に低下する瞬間がある。   In the conventional circuit of FIG. 6, for example, when the FET M1d is off, the voltage VX2 at the terminal 12a oscillates as shown in FIG. 7 with respect to the temperature compensation voltage VTC output from the temperature compensation circuit 11. Further, the drain voltage VNM of the FET M1d oscillates as shown in FIG. 7 with respect to the ground level (GND). In this situation, there is a moment when the drain voltage VNM drops from the ground level to 0.7V or less.

この場合、図８の断面図に示すように、ｎチャネルＦＥＴＭ１ｄのドレインをエミッタとし、半導体のｐ型基板をベースとし、可変容量素子ＣＶ１ａのアノードをコレクタとする寄生トランジスタが、ドレイン電圧ＶＮＭが接地レベルから０．７Ｖ以下に低下したときにオンし、ｎチャネルＦＥＴＭ１ｄのドレインから可変容量素子ＣＶ１ａのアノードに電流がリークすることになる。   In this case, as shown in the cross-sectional view of FIG. 8, a parasitic transistor having the drain of the n-channel FET M1d as the emitter, the semiconductor p-type substrate as the base, and the anode of the variable capacitor CV1a as the collector is connected to the drain voltage VNM. It turns on when the voltage drops below 0.7V from the level, and current leaks from the drain of the n-channel FET M1d to the anode of the variable capacitance element CV1a.

低域フィルタの抵抗Ｒａは１００ＫΩ〜１ＭΩ程度でかなり大きい値であり、上記のリーク電流が流れると端子１２ａの電圧ＶＸ２のバイアスレベルが大幅に低下する。これにより、電圧制御型発振回路の電源立ち上げ時に発振周波数が安定するまでの時間が長くなるという問題があった。   The resistance Ra of the low-pass filter is about 100 KΩ to 1 MΩ, which is a very large value. When the above leakage current flows, the bias level of the voltage VX2 at the terminal 12a is greatly reduced. As a result, there is a problem that it takes a long time until the oscillation frequency is stabilized when the power supply of the voltage controlled oscillation circuit is turned on.

本発明は、上記の点に鑑みなされたもので、電流のリークを防止して電源立ち上げ時の発振周波数が安定するまでの時間を短縮できる電圧制御型発振回路を提供することを目的とする。   The present invention has been made in view of the above points, and an object of the present invention is to provide a voltage-controlled oscillation circuit capable of preventing current leakage and shortening the time until the oscillation frequency is stabilized when the power is turned on. .

本発明の電圧制御型発振回路は、水晶振動子（ＸＴＡＬ）とインバータ（Ｍ３，Ｍ４）と可変容量素子（ＣＶ１，ＣＶ２）を有し、温度補償回路（２１）の出力する温度補償電圧を低域フィルタ（Ｒａ，Ｃａ）を通して前記可変容量素子に印加し、前記水晶振動子の温度補償を行って発振周波数を安定化する電圧制御型発振回路であって、前記可変容量素子に第１スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）付きの容量調整用可変容量素子（ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ）を並列に設け、前記第１スイッチ素子をオンまたはオフして前記可変容量素子の容量を調整する電圧制御型発振回路おいて、
前記第１スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）がオフのときに前記容量調整用可変容量素子と前記第１スイッチ素子の接続点の電圧を上昇させるシフト手段（Ｓ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄ）を有することにより、電流のリークを防止して電源立ち上げ時の発振周波数が安定するまでの時間を短縮できる。 The voltage controlled oscillation circuit of the present invention includes a crystal resonator (XTAL), inverters (M3, M4), and variable capacitance elements (CV1, CV2), and reduces the temperature compensation voltage output from the temperature compensation circuit (21). A voltage-controlled oscillation circuit that stabilizes an oscillation frequency by applying a temperature compensation to the crystal resonator by applying a voltage to the variable capacitor through a pass filter (Ra, Ca), and the first switch element Capacitance adjustment variable capacitance elements (CV1a to CV1d, CV2a to CV2d) with (M1a to M1d, M2a to M2d) are provided in parallel, and the first switch element is turned on or off to adjust the capacitance of the variable capacitance element. In the voltage controlled oscillation circuit that
Shift means (S1a to S1d, S2a to S2d) for increasing the voltage at the connection point between the capacitance adjusting variable capacitance element and the first switch element when the first switch elements (M1a to M1d, M2a to M2d) are off. ), Current leakage can be prevented and the time until the oscillation frequency is stabilized when the power is turned on can be shortened.

前記電圧制御型発振回路において、
前記シフト手段は、前記容量調整用可変容量素子（ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ）の両端間に並列に設けられ前記第１のスイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）と反転動作を行う第２スイッチ素子（Ｓ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄ）で構成することができる。 In the voltage controlled oscillation circuit,
The shift means is provided in parallel between both ends of the capacitance adjusting variable capacitance elements (CV1a to CV1d, CV2a to CV2d) and performs a reversing operation with the first switch elements (M1a to M1d, M2a to M2d). Two switch elements (S1a to S1d, S2a to S2d) can be used.

前記電圧制御型発振回路において、
前記シフト手段は、前記第１スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）と前記容量調整用可変容量素子（ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ）の接続点と前記低域フィルタ（Ｒａ，Ｃａ）の出力端子との間に設けられ前記第１スイッチ素子と反転動作を行う第２スイッチ素子（Ｓ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄ）付きの抵抗（Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄ）で構成することができる。 In the voltage controlled oscillation circuit,
The shift means includes a connection point between the first switch element (M1a to M1d, M2a to M2d) and the capacitance adjusting variable capacitor element (CV1a to CV1d, CV2a to CV2d) and the low-pass filter (Ra, Ca). A resistor (R5a to R5d, R6a to R6d) with a second switch element (S1a to S1d, S2a to S2d) that is provided between the output terminal and performs the inverting operation with the first switch element can be formed.

前記電圧制御型発振回路において、
前記シフト手段は、前記第１スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）と前記容量調整用可変容量素子（ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ）の接続点と定電圧源（Ｅ１）との間に設けられ前記第１スイッチ素子と反転動作を行う第２スイッチ素子（Ｓ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄ）付きの抵抗（Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄ）で構成することができる。 In the voltage controlled oscillation circuit,
The shift means is provided between a connection point of the first switch element (M1a to M1d, M2a to M2d) and the capacitance adjusting variable capacitor element (CV1a to CV1d, CV2a to CV2d) and a constant voltage source (E1). The first switch element and a resistor (R5a to R5d, R6a to R6d) with second switch elements (S1a to S1d, S2a to S2d) that perform an inverting operation can be formed.

前記電圧制御型発振回路において、
前記シフト手段は、前記スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）の両端間に並列に配設した第１の抵抗（Ｒ１ａ〜Ｒ１ｄ，Ｒ２ａ〜Ｒ２ｄ）と、前記容量調整用可変容量素子（ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ）と前記第１スイッチ素子（Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ）の接続点と定電圧源（Ｅ１）との間に配設した第２の抵抗（Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄ）で構成することができる。 In the voltage controlled oscillation circuit,
The shift means includes a first resistor (R1a to R1d, R2a to R2d) disposed in parallel between both ends of the switch element (M1a to M1d, M2a to M2d), and the capacitance adjusting variable capacitance element (CV1a). ˜CV1d, CV2a˜CV2d) and second resistors (R5a˜R5d, R6a˜) disposed between the connection points of the first switch elements (M1a˜M1d, M2a˜M2d) and the constant voltage source (E1). R6d).

なお、上記括弧内の参照符号は、理解を容易にするために付したものであり、一例にすぎず、図示の態様に限定されるものではない。   Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

本発明によれば、電流のリークを防止して電源立ち上げ時の発振周波数が安定するまでの時間を短縮できる。   According to the present invention, it is possible to prevent current leakage and shorten the time until the oscillation frequency is stabilized when the power supply is turned on.

以下、図面に基づいて本発明の実施形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

＜一実施形態＞
図１は、本発明の電圧制御型発振回路の一実施形態の回路構成図を示す。同図中、図６と同一部分には同一符号を付す。半導体集積回路２０内の温度補償回路２１は、周囲温度に応じて水晶振動子ＸＴＡＬの温度特性を補償する温度補償電圧ＶＴＣを発生し、抵抗Ｒａ及びコンデンサＣａで構成される低域フィルタを通し、抵抗Ｒｂ，Ｒｃを経て可変容量素子（可変容量ダイオード）ＣＶ１，ＣＶ２に印加する。 <One Embodiment>
FIG. 1 shows a circuit configuration diagram of an embodiment of a voltage controlled oscillation circuit of the present invention. In the figure, the same parts as those in FIG. The temperature compensation circuit 21 in the semiconductor integrated circuit 20 generates a temperature compensation voltage VTC that compensates for the temperature characteristics of the crystal resonator XTAL according to the ambient temperature, and passes through a low-pass filter composed of a resistor Ra and a capacitor Ca. The voltage is applied to variable capacitance elements (variable capacitance diodes) CV1 and CV2 through resistors Rb and Rc.

可変容量素子ＣＶ１には容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄが並列に設けられ、可変容量素子ＣＶ２には容量調整用可変容量素子ＣＶ２ａ〜ＣＶ２ｄが並列に設けられている。可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄのカソードにはｎチャネルＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインが接続され、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのソースは接地されている。   The variable capacitance element CV1 is provided with capacitance adjustment variable capacitance elements CV1a to CV1d in parallel, and the variable capacitance element CV2 is provided with capacitance adjustment variable capacitance elements CV2a to CV2d in parallel. The drains of n-channel FETs M1a to M1d and M2a to M2d are connected to the cathodes of the variable capacitance elements CV1a to CV1d and CV2a to CV2d, and the sources of the FETs M1a to M1d and M2a to M2d are grounded.

また、可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄそれぞれと並列にスイッチＳ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄが設けられている。   Further, switches S1a to S1d and S2a to S2d are provided in parallel with the variable capacitance elements CV1a to CV1d and CV2a to CV2d, respectively.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄそれぞれはゲートに制御信号を供給されてオン／オフを制御され、スイッチＳ１ａ〜Ｓ１ｄ，Ｓ２ａ〜Ｓ２ｄそれぞれは上記制御信号でオフ／オンを制御され、ＦＥＴがオン（またはオフ）であれば対応するスイッチはオフ（またはオン）と反転動作する。   Each of the FETs M1a to M1d and M2a to M2d is supplied with a control signal to the gate and controlled to be turned on / off. Each of the switches S1a to S1d and S2a to S2d is controlled to be turned off / on by the control signal, and the FET is turned on (or If the switch is off, the corresponding switch is turned off (or turned on).

なお、上記制御信号は予めＲＯＭに登録されており、制御信号によりＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのいずれかをオンすることで、所望の容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄを可変容量素子ＣＶ１に並列接続して容量調整を行っている。   The control signal is registered in advance in the ROM, and the desired capacitance adjusting variable capacitance elements CV1a to CV1d and CV2a to CV2d are variable by turning on any of the FETs M1a to M1d and M2a to M2d according to the control signal. Capacitance adjustment is performed in parallel with the capacitive element CV1.

半導体集積回路２０の外部には水晶振動子ＸＴＡＬが設けられている。水晶振動子ＸＴＡＬの両端は端子２２ａ，２２ｂを介して半導体集積回路２０内の可変容量素子ＣＶ１，ＣＶ２に接続されると共に、コンデンサＣ１とｐチャネルＦＥＴＭ３及びｎチャネルＦＥＴＭ４で構成される帰還抵抗ＲＦＢ付きのインバータと抵抗ＲｄとコンデンサＣ２との直列接続回路によって接続されている。   A crystal resonator XTAL is provided outside the semiconductor integrated circuit 20. Both ends of the crystal resonator XTAL are connected to variable capacitance elements CV1 and CV2 in the semiconductor integrated circuit 20 via terminals 22a and 22b, and have a feedback resistor RFB composed of a capacitor C1, a p-channel FET M3, and an n-channel FET M4. Are connected by a series connection circuit of an inverter, a resistor Rd, and a capacitor C2.

この電圧制御型発振回路は、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に帰還抵抗ＲＦＢで接続して帰還をかけることで負性抵抗回路を構成しており、可変容量素子ＣＶ１とコンデンサＣ１の直列容量と、可変容量素子ＣＶ２とコンデンサＣ２の直列容量と、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に接続された水晶振動子ＸＴＡＬのインダクタンス成分で発振するコルピッツ発振回路を構成しており、水晶振動子の温度補償を行うことで発振周波数を安定化している。   This voltage-controlled oscillation circuit forms a negative resistance circuit by applying feedback by connecting a feedback resistor RFB between the input and output terminals of the inverters of the FETs M3 and M4, and the variable capacitance element CV1 and the capacitor C1 are connected in series. A Colpitts oscillation circuit that oscillates with the capacitance, the series capacitance of the variable capacitance element CV2 and the capacitor C2, and the inductance component of the crystal resonator XTAL connected between the input and output terminals of the inverters of the FETs M3 and M4 is configured. The oscillation frequency is stabilized by performing temperature compensation of the child.

図１において、例えばＦＥＴＭ１ｄがオフの場合、スイッチＳ１ｄはオンであり、端子２２ａの電圧ＶＸ２は温度補償回路１１の出力する温度補償電圧ＶＴＣを基準として図２（Ａ）に示すように振動する。また、ＦＥＴＭ１ｄのドレイン電圧ＶＮＭはスイッチＳ１ｄがオンのため温度補償電圧ＶＴＣを基準として図２（Ｂ）に示すように振動し、ドレイン電圧ＶＮＭは接地レベルを下回ることはない。   In FIG. 1, for example, when the FET M1d is off, the switch S1d is on, and the voltage VX2 at the terminal 22a oscillates as shown in FIG. 2A with reference to the temperature compensation voltage VTC output from the temperature compensation circuit 11. Further, the drain voltage VNM of the FET M1d oscillates as shown in FIG. 2B with respect to the temperature compensation voltage VTC because the switch S1d is on, and the drain voltage VNM does not fall below the ground level.

このため、図８に示すように、ｎチャネルＦＥＴＭ１ｄのドレインをエミッタとし、半導体のｐ型基板をベースとし、可変容量素子ＣＶ１ａのアノードをコレクタとする寄生トランジスタがオンすることはなく電流のリークが防止される。従って、電圧制御型発振回路の電源立ち上げ時に発振周波数が安定するまでの時間を短縮できる。   Therefore, as shown in FIG. 8, a parasitic transistor having the drain of the n-channel FET M1d as the emitter, the semiconductor p-type substrate as the base, and the anode of the variable capacitor CV1a as the collector is not turned on, and current leakage occurs. Is prevented. Accordingly, it is possible to shorten the time until the oscillation frequency is stabilized when the power supply of the voltage controlled oscillation circuit is turned on.

＜変形例＞
図３は、本発明の電圧制御型発振回路の変形例の回路構成図を示す。同図中、図６と同一部分には同一符号を付す。図３において、半導体集積回路２０内の温度補償回路２１は、周囲温度に応じて水晶振動子ＸＴＡＬの温度特性を補償する温度補償電圧ＶＴＣを発生し、抵抗Ｒａ及びコンデンサＣａで構成される低域フィルタを通し、抵抗Ｒｂ，Ｒｃを経て可変容量素子（可変容量ダイオード）ＣＶ１，ＣＶ２に印加する。 <Modification>
FIG. 3 shows a circuit configuration diagram of a modified example of the voltage controlled oscillator circuit of the present invention. In the figure, the same parts as those in FIG. In FIG. 3, a temperature compensation circuit 21 in the semiconductor integrated circuit 20 generates a temperature compensation voltage VTC that compensates for the temperature characteristics of the crystal resonator XTAL according to the ambient temperature, and is a low-frequency band constituted by a resistor Ra and a capacitor Ca. The filter is applied to the variable capacitance elements (variable capacitance diodes) CV1 and CV2 through the resistors Rb and Rc.

可変容量素子ＣＶ１には容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄが並列に設けられ、可変容量素子ＣＶ２には容量調整用可変容量素子ＣＶ２ａ〜ＣＶ２ｄが並列に設けられている。可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄのカソードにはｎチャネルＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインが接続され、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのソースは接地されている。   The variable capacitance element CV1 is provided with capacitance adjustment variable capacitance elements CV1a to CV1d in parallel, and the variable capacitance element CV2 is provided with capacitance adjustment variable capacitance elements CV2a to CV2d in parallel. The drains of n-channel FETs M1a to M1d and M2a to M2d are connected to the cathodes of the variable capacitance elements CV1a to CV1d and CV2a to CV2d, and the sources of the FETs M1a to M1d and M2a to M2d are grounded.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインには抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの一端が接続されており、抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの他端はスイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄを介して低域フィルタの出力端子つまり抵抗ＲａとコンデンサＣａの接続点に接続されている。   One ends of resistors R5a to R5d and R6a to R6d are connected to the drains of the FETs M1a to M1d and M2a to M2d, and the other ends of the resistors R5a to R5d and R6a to R6d are connected via switches S3a to S3d and S4a to S4d. The output terminal of the low-pass filter, that is, the connection point between the resistor Ra and the capacitor Ca is connected.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄそれぞれはゲートに制御信号を供給されてオン／オフを制御され、スイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄそれぞれは上記制御信号でオフ／オンを制御され、ＦＥＴがオン（またはオフ）であれば対応するスイッチはオフ（またはオン）と反転動作する。   Each of the FETs M1a to M1d and M2a to M2d is supplied with a control signal to the gate and controlled to be turned on / off, and each of the switches S3a to S3d and S4a to S4d is controlled to be turned off / on by the control signal, and the FET is turned on (or If the switch is off, the corresponding switch is turned off (or turned on).

なお、上記制御信号は予めＲＯＭに登録されており、制御信号によりＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのいずれかをオンすることで、所望の容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄを可変容量素子ＣＶ１に並列接続して容量調整を行っている。   The control signal is registered in advance in the ROM, and the desired capacitance adjusting variable capacitance elements CV1a to CV1d and CV2a to CV2d are variable by turning on any of the FETs M1a to M1d and M2a to M2d according to the control signal. Capacitance adjustment is performed in parallel with the capacitive element CV1.

半導体集積回路２０の外部には水晶振動子ＸＴＡＬが設けられている。水晶振動子ＸＴＡＬの両端は端子２２ａ，２２ｂを介して半導体集積回路２０内の可変容量素子ＣＶ１，ＣＶ２に接続されると共に、コンデンサＣ１とｐチャネルＦＥＴＭ３及びｎチャネルＦＥＴＭ４で構成される帰還抵抗ＲＦＢ付きのインバータと抵抗ＲｄとコンデンサＣ２との直列接続回路によって接続されている。   A crystal resonator XTAL is provided outside the semiconductor integrated circuit 20. Both ends of the crystal resonator XTAL are connected to variable capacitance elements CV1 and CV2 in the semiconductor integrated circuit 20 via terminals 22a and 22b, and have a feedback resistor RFB composed of a capacitor C1, a p-channel FET M3, and an n-channel FET M4. Are connected by a series connection circuit of an inverter, a resistor Rd, and a capacitor C2.

この電圧制御型発振回路は、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に帰還抵抗ＲＦＢで接続して帰還をかけることで負性抵抗回路を構成しており、可変容量素子ＣＶ１とコンデンサＣ１の直列容量と、可変容量素子ＣＶ２とコンデンサＣ２の直列容量と、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に接続された水晶振動子ＸＴＡＬのインダクタンス成分で発振するコルピッツ発振回路を構成しており、水晶振動子の温度補償を行うことで発振周波数を安定化している。   This voltage-controlled oscillation circuit forms a negative resistance circuit by applying feedback by connecting a feedback resistor RFB between the input and output terminals of the inverters of the FETs M3 and M4, and the variable capacitance element CV1 and the capacitor C1 are connected in series. A Colpitts oscillation circuit that oscillates with the capacitance, the series capacitance of the variable capacitance element CV2 and the capacitor C2, and the inductance component of the crystal resonator XTAL connected between the input and output terminals of the inverters of the FETs M3 and M4 is configured. The oscillation frequency is stabilized by performing temperature compensation of the child.

図３において、例えばＦＥＴＭ１ｄがオフの場合、スイッチＳ３ｄはオンであり、ＦＥＴＭ１ｄのドレイン電圧ＶＮＭは図２（Ｂ）と同様に温度補償電圧ＶＴＣ（例えば１．４Ｖ）を基準として振動し、接地レベルを下回ることはない。   In FIG. 3, for example, when the FET M1d is off, the switch S3d is on, and the drain voltage VNM of the FET M1d oscillates on the basis of the temperature compensation voltage VTC (for example, 1.4 V) as in FIG. Never fall below.

このため、図８に示すように、ｎチャネルＦＥＴＭ１ｄのドレインをエミッタとし、半導体のｐ型基板をベースとし、可変容量素子ＣＶ１ａのアノードをコレクタとする寄生トランジスタがオンすることはなく電流のリークが防止される。従って、電圧制御型発振回路の電源立ち上げ時に発振周波数が安定するまでの時間を短縮できる。   Therefore, as shown in FIG. 8, a parasitic transistor having the drain of the n-channel FET M1d as the emitter, the semiconductor p-type substrate as the base, and the anode of the variable capacitor CV1a as the collector is not turned on, and current leakage occurs. Is prevented. Accordingly, it is possible to shorten the time until the oscillation frequency is stabilized when the power supply of the voltage controlled oscillation circuit is turned on.

＜他の変形例＞
図４は、本発明の電圧制御型発振回路の他の変形例の回路構成図を示す。同図中、図３と同一部分には同一符号を付す。この変形例で図３と異なるところは、抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの他端がスイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄを介して定電圧源Ｅ１に接続されている点である。 <Other variations>
FIG. 4 shows a circuit configuration diagram of another modification of the voltage controlled oscillation circuit of the present invention. In the figure, the same parts as those in FIG. 3 is different from FIG. 3 in that the other ends of the resistors R5a to R5d and R6a to R6d are connected to the constant voltage source E1 via the switches S3a to S3d and S4a to S4d.

図４において、半導体集積回路２０内の温度補償回路２１は、周囲温度に応じて水晶振動子ＸＴＡＬの温度特性を補償する温度補償電圧ＶＴＣを発生し、抵抗Ｒａ及びコンデンサＣａで構成される低域フィルタを通し、抵抗Ｒｂ，Ｒｃを経て可変容量素子（可変容量ダイオード）ＣＶ１，ＣＶ２に印加する。   In FIG. 4, a temperature compensation circuit 21 in the semiconductor integrated circuit 20 generates a temperature compensation voltage VTC that compensates for the temperature characteristics of the crystal resonator XTAL in accordance with the ambient temperature, and is a low-frequency band constituted by a resistor Ra and a capacitor Ca. The filter is applied to the variable capacitance elements (variable capacitance diodes) CV1 and CV2 through the resistors Rb and Rc.

可変容量素子ＣＶ１には容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄが並列に設けられ、可変容量素子ＣＶ２には容量調整用可変容量素子ＣＶ２ａ〜ＣＶ２ｄが並列に設けられている。可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄのカソードにはｎチャネルＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインが接続され、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのソースは接地されている。   The variable capacitance element CV1 is provided with capacitance adjustment variable capacitance elements CV1a to CV1d in parallel, and the variable capacitance element CV2 is provided with capacitance adjustment variable capacitance elements CV2a to CV2d in parallel. The drains of n-channel FETs M1a to M1d and M2a to M2d are connected to the cathodes of the variable capacitance elements CV1a to CV1d and CV2a to CV2d, and the sources of the FETs M1a to M1d and M2a to M2d are grounded.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインには抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの一端が接続されており、抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの他端がスイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄを介して定電圧源Ｅ１に接続されている。なお、定電圧源Ｅ１の値は例えば０．７Ｖ程度に設定されている。   One ends of resistors R5a to R5d and R6a to R6d are connected to the drains of the FETs M1a to M1d and M2a to M2d, and the other ends of the resistors R5a to R5d and R6a to R6d are connected via switches S3a to S3d and S4a to S4d. It is connected to a constant voltage source E1. The value of the constant voltage source E1 is set to about 0.7V, for example.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄそれぞれはゲートに制御信号を供給されてオン／オフを制御され、スイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄそれぞれは上記制御信号でオフ／オンを制御され、ＦＥＴがオン（またはオフ）であれば対応するスイッチはオフ（またはオン）と反転動作する。   Each of the FETs M1a to M1d and M2a to M2d is supplied with a control signal to the gate and controlled to be turned on / off, and each of the switches S3a to S3d and S4a to S4d is controlled to be turned off / on by the control signal, and the FET is turned on (or If the switch is off, the corresponding switch is turned off (or turned on).

なお、上記制御信号は予めＲＯＭに登録されており、制御信号によりＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのいずれかをオンすることで、所望の容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄを可変容量素子ＣＶ１に並列接続して容量調整を行っている。   The control signal is registered in advance in the ROM, and the desired capacitance adjusting variable capacitance elements CV1a to CV1d and CV2a to CV2d are variable by turning on any of the FETs M1a to M1d and M2a to M2d according to the control signal. Capacitance adjustment is performed in parallel with the capacitive element CV1.

半導体集積回路２０の外部には水晶振動子ＸＴＡＬが設けられている。水晶振動子ＸＴＡＬの両端は端子２２ａ，２２ｂを介して半導体集積回路２０内の可変容量素子ＣＶ１，ＣＶ２に接続されると共に、コンデンサＣ１とｐチャネルＦＥＴＭ３及びｎチャネルＦＥＴＭ４で構成される帰還抵抗ＲＦＢ付きのインバータと抵抗ＲｄとコンデンサＣ２との直列接続回路によって接続されている。   A crystal resonator XTAL is provided outside the semiconductor integrated circuit 20. Both ends of the crystal resonator XTAL are connected to variable capacitance elements CV1 and CV2 in the semiconductor integrated circuit 20 via terminals 22a and 22b, and have a feedback resistor RFB composed of a capacitor C1, a p-channel FET M3, and an n-channel FET M4. Are connected by a series connection circuit of an inverter, a resistor Rd, and a capacitor C2.

この電圧制御型発振回路は、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に帰還抵抗ＲＦＢで接続して帰還をかけることで負性抵抗回路を構成しており、可変容量素子ＣＶ１とコンデンサＣ１の直列容量と、可変容量素子ＣＶ２とコンデンサＣ２の直列容量と、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に接続された水晶振動子ＸＴＡＬのインダクタンス成分で発振するコルピッツ発振回路を構成しており、水晶振動子の温度補償を行うことで発振周波数を安定化している。   This voltage-controlled oscillation circuit forms a negative resistance circuit by applying feedback by connecting a feedback resistor RFB between the input and output terminals of the inverters of the FETs M3 and M4, and the variable capacitance element CV1 and the capacitor C1 are connected in series. A Colpitts oscillation circuit that oscillates with the capacitance, the series capacitance of the variable capacitance element CV2 and the capacitor C2, and the inductance component of the crystal resonator XTAL connected between the input and output terminals of the inverters of the FETs M3 and M4 is configured. The oscillation frequency is stabilized by performing temperature compensation of the child.

図４において、例えばＦＥＴＭ１ｄがオフの場合、スイッチＳ３ｄはオンであり、ＦＥＴＭ１ｄのドレイン電圧ＶＮＭは定電圧Ｅ１（＝０．７Ｖ）を基準として振動し、接地レベルを下回ることはない。   In FIG. 4, for example, when the FET M1d is off, the switch S3d is on, and the drain voltage VNM of the FET M1d oscillates with the constant voltage E1 (= 0.7 V) as a reference and does not fall below the ground level.

このため、図８に示すように、ｎチャネルＦＥＴＭ１ｄのドレインをエミッタとし、半導体のｐ型基板をベースとし、可変容量素子ＣＶ１ａのアノードをコレクタとする寄生トランジスタがオンすることはなく電流のリークが防止される。従って、電圧制御型発振回路の電源立ち上げ時に発振周波数が安定するまでの時間を短縮できる。   Therefore, as shown in FIG. 8, a parasitic transistor having the drain of the n-channel FET M1d as the emitter, the semiconductor p-type substrate as the base, and the anode of the variable capacitor CV1a as the collector is not turned on, and current leakage occurs. Is prevented. Accordingly, it is possible to shorten the time until the oscillation frequency is stabilized when the power supply of the voltage controlled oscillation circuit is turned on.

＜別の変形例＞
図５は、本発明の電圧制御型発振回路の別の変形例の回路構成図を示す。同図中、図３と同一部分には同一符号を付す。この変形例で図３と異なるところは、抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの他端をスイッチＳ３ａ〜Ｓ３ｄ，Ｓ４ａ〜Ｓ４ｄを介さず定電圧源Ｅ１に接続する点と、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレイン，ソース間を抵抗Ｒ１ａ〜Ｒ１ｄ，Ｒ２ａ〜Ｒ２ｄで接続する点である。 <Another modification>
FIG. 5 shows a circuit configuration diagram of another modification of the voltage-controlled oscillation circuit of the present invention. In the figure, the same parts as those in FIG. 3 differs from FIG. 3 in that the other ends of the resistors R5a to R5d and R6a to R6d are connected to the constant voltage source E1 without passing through the switches S3a to S3d and S4a to S4d, and the FETs M1a to M1d and M2a to The drain and source of M2d are connected by resistors R1a to R1d and R2a to R2d.

図５において、半導体集積回路２０内の温度補償回路２１は、周囲温度に応じて水晶振動子ＸＴＡＬの温度特性を補償する温度補償電圧ＶＴＣを発生し、抵抗Ｒａ及びコンデンサＣａで構成される低域フィルタを通し、抵抗Ｒｂ，Ｒｃを経て可変容量素子（可変容量ダイオード）ＣＶ１，ＣＶ２に印加する。   In FIG. 5, a temperature compensation circuit 21 in the semiconductor integrated circuit 20 generates a temperature compensation voltage VTC that compensates for the temperature characteristics of the crystal resonator XTAL in accordance with the ambient temperature, and is a low-frequency band constituted by a resistor Ra and a capacitor Ca. The filter is applied to the variable capacitance elements (variable capacitance diodes) CV1 and CV2 through the resistors Rb and Rc.

可変容量素子ＣＶ１には容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄが並列に設けられ、可変容量素子ＣＶ２には容量調整用可変容量素子ＣＶ２ａ〜ＣＶ２ｄが並列に設けられている。可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄのカソードにはｎチャネルＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインが接続され、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのソースは接地されている。   The variable capacitance element CV1 is provided with capacitance adjustment variable capacitance elements CV1a to CV1d in parallel, and the variable capacitance element CV2 is provided with capacitance adjustment variable capacitance elements CV2a to CV2d in parallel. The drains of n-channel FETs M1a to M1d and M2a to M2d are connected to the cathodes of the variable capacitance elements CV1a to CV1d and CV2a to CV2d, and the sources of the FETs M1a to M1d and M2a to M2d are grounded.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレイン，ソース間は抵抗Ｒ１ａ〜Ｒ１ｄ，Ｒ２ａ〜Ｒ２ｄで接続されている。また、ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのドレインには抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの一端が接続されており、抵抗Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄの他端は定電圧源Ｅ１に接続されている。なお、定電圧源Ｅ１の値は例えば０．７Ｖ程度に設定されている。   The drains and sources of the FETs M1a to M1d and M2a to M2d are connected by resistors R1a to R1d and R2a to R2d. The drains of the FETs M1a to M1d and M2a to M2d are connected to one ends of resistors R5a to R5d and R6a to R6d, and the other ends of the resistors R5a to R5d and R6a to R6d are connected to the constant voltage source E1. . The value of the constant voltage source E1 is set to about 0.7V, for example.

ＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄそれぞれはゲートに制御信号を供給されてオン／オフを制御される。   Each of the FETs M1a to M1d and M2a to M2d is supplied with a control signal to the gate and controlled to be turned on / off.

なお、上記制御信号は予めＲＯＭに登録されており、制御信号によりＦＥＴＭ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄのいずれかをオンすることで、所望の容量調整用可変容量素子ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄを可変容量素子ＣＶ１に並列接続して容量調整を行っている。   The control signal is registered in advance in the ROM, and the desired capacitance adjusting variable capacitance elements CV1a to CV1d and CV2a to CV2d are variable by turning on any of the FETs M1a to M1d and M2a to M2d according to the control signal. Capacitance adjustment is performed in parallel with the capacitive element CV1.

半導体集積回路２０の外部には水晶振動子ＸＴＡＬが設けられている。水晶振動子ＸＴＡＬの両端は端子２２ａ，２２ｂを介して半導体集積回路２０内の可変容量素子ＣＶ１，ＣＶ２に接続されると共に、コンデンサＣ１とｐチャネルＦＥＴＭ３及びｎチャネルＦＥＴＭ４で構成される帰還抵抗ＲＦＢ付きのインバータと抵抗ＲｄとコンデンサＣ２との直列接続回路によって接続されている。   A crystal resonator XTAL is provided outside the semiconductor integrated circuit 20. Both ends of the crystal resonator XTAL are connected to variable capacitance elements CV1 and CV2 in the semiconductor integrated circuit 20 via terminals 22a and 22b, and have a feedback resistor RFB composed of a capacitor C1, a p-channel FET M3, and an n-channel FET M4. Are connected by a series connection circuit of an inverter, a resistor Rd, and a capacitor C2.

この電圧制御型発振回路は、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に帰還抵抗ＲＦＢで接続して帰還をかけることで負性抵抗回路を構成しており、可変容量素子ＣＶ１とコンデンサＣ１の直列容量と、可変容量素子ＣＶ２とコンデンサＣ２の直列容量と、ＦＥＴＭ３，Ｍ４のインバータの入出力端子間に接続された水晶振動子ＸＴＡＬのインダクタンス成分で発振するコルピッツ発振回路を構成しており、水晶振動子の温度補償を行うことで発振周波数を安定化している。   This voltage-controlled oscillation circuit forms a negative resistance circuit by applying feedback by connecting a feedback resistor RFB between the input and output terminals of the inverters of the FETs M3 and M4, and the variable capacitance element CV1 and the capacitor C1 are connected in series. A Colpitts oscillation circuit that oscillates with the capacitance, the series capacitance of the variable capacitance element CV2 and the capacitor C2, and the inductance component of the crystal resonator XTAL connected between the input and output terminals of the inverters of the FETs M3 and M4 is configured. The oscillation frequency is stabilized by performing temperature compensation of the child.

図５において、例えばＦＥＴＭ１ｄがオフの場合、ＦＥＴＭ１ｄのドレイン電圧ＶＮＭは定電圧Ｅ１（＝０．７Ｖ）にバイアスされているため、接地レベルを下回ることはない。   In FIG. 5, for example, when the FET M1d is off, the drain voltage VNM of the FET M1d is biased to the constant voltage E1 (= 0.7 V), and therefore does not fall below the ground level.

このため、図８に示すように、ｎチャネルＦＥＴＭ１ｄのドレインをエミッタとし、半導体のｐ型基板をベースとし、可変容量素子ＣＶ１ａのアノードをコレクタとする寄生トランジスタがオンすることはなく電流のリークが防止される。従って、電圧制御型発振回路の電源立ち上げ時に発振周波数が安定するまでの時間を短縮できる。   Therefore, as shown in FIG. 8, a parasitic transistor having the drain of the n-channel FET M1d as the emitter, the semiconductor p-type substrate as the base, and the anode of the variable capacitor CV1a as the collector is not turned on, and current leakage occurs. Is prevented. Accordingly, it is possible to shorten the time until the oscillation frequency is stabilized when the power supply of the voltage controlled oscillation circuit is turned on.

本発明の電圧制御型発振回路の一実施形態の回路構成図である。1 is a circuit configuration diagram of an embodiment of a voltage controlled oscillator circuit of the present invention. 図１の各部の電圧波形を示す図である。It is a figure which shows the voltage waveform of each part of FIG. 本発明の電圧制御型発振回路の変形例の回路構成図である。It is a circuit block diagram of the modification of the voltage controlled oscillation circuit of this invention. 本発明の電圧制御型発振回路の他の変形例の回路構成図である。It is a circuit block diagram of the other modification of the voltage controlled oscillation circuit of this invention. 本発明の電圧制御型発振回路の別の変形例の回路構成図である。It is a circuit block diagram of another modification of the voltage controlled oscillation circuit of this invention. 従来の電圧制御型発振回路の一例の回路構成図である。It is a circuit block diagram of an example of the conventional voltage controlled oscillation circuit. 図６の各部の電圧波形を示す図である。It is a figure which shows the voltage waveform of each part of FIG. 寄生トランジスタを説明するための断面図である。It is sectional drawing for demonstrating a parasitic transistor.

符号の説明Explanation of symbols

２０ 半導体集積回路
２１ 温度補償回路
ＣＶ１，ＣＶ２ 可変容量素子
ＣＶ１ａ〜ＣＶ１ｄ，ＣＶ２ａ〜ＣＶ２ｄ 調整用可変容量素子
Ｃ１，Ｃ２ コンデンサ
Ｍ１ａ〜Ｍ１ｄ，Ｍ２ａ〜Ｍ２ｄ，Ｍ３，Ｍ４ ＦＥＴ
Ｒ１ａ〜Ｒ１ｄ，Ｒ２ａ〜Ｒ２ｄ，Ｒ５ａ〜Ｒ５ｄ，Ｒ６ａ〜Ｒ６ｄ 抵抗
ＸＴＡＬ 水晶振動子 20 Semiconductor Integrated Circuit 21 Temperature Compensation Circuit CV1, CV2 Variable Capacitance Element CV1a to CV1d, CV2a to CV2d Adjustment Variable Capacitance Element C1, C2 Capacitor M1a to M1d, M2a to M2d, M3, M4 FET
R1a to R1d, R2a to R2d, R5a to R5d, R6a to R6d Resistor XTAL Quartz Crystal

Claims (5)

水晶振動子とインバータと可変容量素子を有し、温度補償回路の出力する温度補償電圧を低域フィルタを通して前記可変容量素子に印加し、前記水晶振動子の温度補償を行って発振周波数を安定化する電圧制御型発振回路であって、前記可変容量素子に第１スイッチ素子付きの容量調整用可変容量素子を並列に設け、前記第１スイッチ素子をオンまたはオフして前記可変容量素子の容量を調整する電圧制御型発振回路おいて、
前記第１スイッチ素子がオフのときに前記容量調整用可変容量素子と前記第１スイッチ素子の接続点の電圧を上昇させるシフト手段を
有することを特徴とする電圧制御型発振回路。 It has a crystal resonator, inverter, and variable capacitance element. The temperature compensation voltage output from the temperature compensation circuit is applied to the variable capacitance element through a low-pass filter, and the oscillation frequency is stabilized by performing temperature compensation of the crystal resonator. A voltage-controlled oscillation circuit configured to provide a variable capacitance element for capacitance adjustment with a first switch element in parallel with the variable capacitance element, and turn on or off the first switch element to increase a capacitance of the variable capacitance element. In the voltage controlled oscillation circuit to be adjusted,
A voltage-controlled oscillation circuit comprising a shift means for increasing a voltage at a connection point between the capacitance adjusting variable capacitance element and the first switch element when the first switch element is off. 請求項１記載の電圧制御型発振回路おいて、
前記シフト手段は、前記容量調整用可変容量素子の両端間に並列に設けられ前記第１のスイッチ素子と反転動作を行う第２スイッチ素子であることを特徴とする電圧制御型発振回路。 In the voltage controlled oscillation circuit according to claim 1,
The voltage controlled oscillation circuit, wherein the shift means is a second switch element that is provided in parallel between both ends of the capacitance adjusting variable capacitance element and performs an inverting operation with the first switch element. 請求項１記載の電圧制御型発振回路おいて、
前記シフト手段は、前記第１スイッチ素子と前記容量調整用可変容量素子の接続点と前記低域フィルタの出力端子との間に設けられ前記第１スイッチ素子と反転動作を行う第２スイッチ素子付きの抵抗であることを特徴とする電圧制御型発振回路。 In the voltage controlled oscillation circuit according to claim 1,
The shift means is provided between a connection point of the first switch element and the variable capacitance element for capacitance adjustment and an output terminal of the low-pass filter, and has a second switch element that performs an inverting operation with the first switch element. A voltage-controlled oscillation circuit characterized by being a resistor. 請求項１記載の電圧制御型発振回路おいて、
前記シフト手段は、前記第１スイッチ素子と前記容量調整用可変容量素子の接続点と定電圧源との間に設けられ前記第１スイッチ素子と反転動作を行う第２スイッチ素子付きの抵抗であることを特徴とする電圧制御型発振回路。 In the voltage controlled oscillation circuit according to claim 1,
The shift means is a resistor with a second switch element that is provided between a connection point of the first switch element and the variable capacitance element for capacitance adjustment and a constant voltage source and performs an inverting operation with the first switch element. A voltage-controlled oscillation circuit characterized by that. 請求項１記載の電圧制御型発振回路おいて、
前記シフト手段は、前記第１スイッチ素子の両端間に並列に配設した第１の抵抗と、前記容量調整用可変容量素子と前記第１スイッチ素子の接続点と定電圧源との間に配設した第２の抵抗であることを特徴とする電圧制御型発振回路。 In the voltage controlled oscillation circuit according to claim 1,
The shift means is disposed between a first resistor disposed in parallel between both ends of the first switch element, a connection point between the variable capacitance element for capacitance adjustment, the first switch element, and a constant voltage source. A voltage controlled oscillation circuit, characterized by being a second resistor provided.
JP2006265421A 2006-09-28 2006-09-28 Voltage-controlled oscillation circuit Pending JP2008085857A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286907A (en) * 1985-10-11 1987-04-21 Matsushima Kogyo Co Ltd Crystal oscillation circuit
JP2005529536A (en) * 2002-06-10 2005-09-29 ジーシーティー セミコンダクター インコーポレイテッド LC oscillator with wide tuning range and low phase noise
JP2006157767A (en) * 2004-12-01 2006-06-15 Renesas Technology Corp Communication semiconductor integrated circuit with built-in oscillation circuit, communication system, and manufacturing method of semiconductor integrated circuit
JP2007228339A (en) * 2006-02-24 2007-09-06 Renesas Technology Corp Semiconductor integrated circuit for communication with built-in oscillation circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286907A (en) * 1985-10-11 1987-04-21 Matsushima Kogyo Co Ltd Crystal oscillation circuit
JP2005529536A (en) * 2002-06-10 2005-09-29 ジーシーティー セミコンダクター インコーポレイテッド LC oscillator with wide tuning range and low phase noise
JP2006157767A (en) * 2004-12-01 2006-06-15 Renesas Technology Corp Communication semiconductor integrated circuit with built-in oscillation circuit, communication system, and manufacturing method of semiconductor integrated circuit
JP2007228339A (en) * 2006-02-24 2007-09-06 Renesas Technology Corp Semiconductor integrated circuit for communication with built-in oscillation circuit

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