JP2008078754A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008078754A5 JP2008078754A5 JP2006252772A JP2006252772A JP2008078754A5 JP 2008078754 A5 JP2008078754 A5 JP 2008078754A5 JP 2006252772 A JP2006252772 A JP 2006252772A JP 2006252772 A JP2006252772 A JP 2006252772A JP 2008078754 A5 JP2008078754 A5 JP 2008078754A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- latch circuit
- circuit
- mos transistor
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 19
- 230000000295 complement effect Effects 0.000 claims 8
- 230000003068 static effect Effects 0.000 claims 6
- 230000000903 blocking effect Effects 0.000 claims 2
- 230000001902 propagating effect Effects 0.000 claims 2
- 238000011144 upstream manufacturing Methods 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006252772A JP4883621B2 (ja) | 2006-09-19 | 2006-09-19 | 半導体集積回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006252772A JP4883621B2 (ja) | 2006-09-19 | 2006-09-19 | 半導体集積回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008078754A JP2008078754A (ja) | 2008-04-03 |
| JP2008078754A5 true JP2008078754A5 (enExample) | 2009-03-05 |
| JP4883621B2 JP4883621B2 (ja) | 2012-02-22 |
Family
ID=39350404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006252772A Expired - Fee Related JP4883621B2 (ja) | 2006-09-19 | 2006-09-19 | 半導体集積回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4883621B2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5008612B2 (ja) * | 2008-06-27 | 2012-08-22 | シャープ株式会社 | 半導体集積回路及びその制御方法 |
| US7961502B2 (en) * | 2008-12-04 | 2011-06-14 | Qualcomm Incorporated | Non-volatile state retention latch |
| JP2010282411A (ja) * | 2009-06-04 | 2010-12-16 | Renesas Electronics Corp | 半導体集積回路、半導体集積回路の内部状態退避回復方法 |
| KR102112367B1 (ko) * | 2013-02-12 | 2020-05-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| JP6602278B2 (ja) * | 2016-09-16 | 2019-11-06 | 株式会社東芝 | 半導体装置 |
| WO2019142546A1 (ja) * | 2018-01-16 | 2019-07-25 | パナソニックIpマネジメント株式会社 | 半導体集積回路 |
| CN112311383B (zh) * | 2020-12-18 | 2025-03-11 | 福建江夏学院 | 实现电源监控高效低功耗的电路及工作方法 |
| CN113176749B (zh) * | 2021-04-23 | 2024-06-04 | 广东天波信息技术股份有限公司 | 一种避免处理器上电过程中i/o口闩锁的电路 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003215214A (ja) * | 2002-01-29 | 2003-07-30 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
| US7221205B2 (en) * | 2004-07-06 | 2007-05-22 | Arm Limited | Circuit and method for storing data in operational, diagnostic and sleep modes |
| US7154317B2 (en) * | 2005-01-11 | 2006-12-26 | Arm Limited | Latch circuit including a data retention latch |
| KR100630740B1 (ko) * | 2005-03-03 | 2006-10-02 | 삼성전자주식회사 | 스캔 기능을 갖는 고속 펄스 기반의 리텐션 플립플롭 |
-
2006
- 2006-09-19 JP JP2006252772A patent/JP4883621B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103684355B (zh) | 门控时钟锁存器、其操作方法和采用其的集成电路 | |
| CN106560999B (zh) | 用于低功率高速集成时钟门控单元的设备 | |
| US9246489B1 (en) | Integrated clock gating cell using a low area and a low power latch | |
| US8456214B2 (en) | State retention circuit and method of operation of such a circuit | |
| US20070226560A1 (en) | Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit | |
| KR100358873B1 (ko) | 래치 회로 및 레지스터 회로 | |
| JP3653170B2 (ja) | ラッチ回路およびフリップフロップ回路 | |
| US7511535B2 (en) | Fine-grained power management of synchronous and asynchronous datapath circuits | |
| US20130307585A1 (en) | Semiconductor integrated circuit | |
| JP3921456B2 (ja) | 信号経路およびパワーゲート方法ならびにフルサイクルラッチ回路 | |
| TW202025146A (zh) | 針對雙電源記憶體的靈活電源排序 | |
| JP2008078754A5 (enExample) | ||
| JPH08288827A (ja) | 短絡電流および突然の故障の無い論理ビルディングブロック | |
| JP2002507852A (ja) | リーク電流を低減する回路装置 | |
| JP2002185307A (ja) | 中継用マクロセル | |
| WO2007046368A1 (ja) | 半導体集積回路 | |
| TWI543533B (zh) | 快速動態寄存器、積體電路、寄存資料的方法以及可掃描快速動態寄存器 | |
| US7928792B2 (en) | Apparatus for outputting complementary signals using bootstrapping technology | |
| US7986166B1 (en) | Clock buffer circuit | |
| JP2008078754A (ja) | 半導体集積回路 | |
| KR100609484B1 (ko) | 저전력 소모의 플립플롭 | |
| Zhang et al. | Leakage Reduction of Power-Gating Sequential Circuits Based on Complementary Pass-Transistor Adiabatic Logic Circuits | |
| JP3498091B2 (ja) | 半導体回路 | |
| Di et al. | Ultra-low power multi-threshold asynchronous circuit design | |
| JP2001016093A (ja) | 半導体回路 |