JP2007517392A - 露光領域において光学制御モジュールを有するウエハ - Google Patents
露光領域において光学制御モジュールを有するウエハ Download PDFInfo
- Publication number
- JP2007517392A JP2007517392A JP2006546426A JP2006546426A JP2007517392A JP 2007517392 A JP2007517392 A JP 2007517392A JP 2006546426 A JP2006546426 A JP 2006546426A JP 2006546426 A JP2006546426 A JP 2006546426A JP 2007517392 A JP2007517392 A JP 2007517392A
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- Prior art keywords
- control module
- wafer
- exposure
- area
- areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000003287 optical effect Effects 0.000 title claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 71
- 238000000926 separation method Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70681—Metrology strategies
- G03F7/70683—Mark designs
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
Claims (4)
- ウエハにおいて、前記ウエハが複数の露光領域を有し、前記ウエハが各々の前記露光領域において複数の格子領域を有し、各々の前記格子領域がICを含み、前記ウエハが、第1のダイシング経路の第1のグループ及び第2のダイシング経路の第2のグループを有し、前記第1のグループの全ての前記第1のダイシング経路が第1の方向に平行し、かつ第1の経路幅を持ち、前記第2のグループの全ての前記第2のダイシング経路が前記第1の方向に交差する第2の方向に平行し、かつ第2の経路幅を持ち、前記第1のダイシング経路及び前記第2のダイシング経路が前記格子領域及び前記格子領域に含まれる前記ICの後の分離のために設けられ、かつ設計され、各々の前記露光領域において少なくとも2つの制御モジュール領域が設けられ、前記制御モジュール領域の各々が少なくとも1つの光学制御モジュールを含み、1つの前記露光領域に設けられた各制御モジュール領域が所定数の格子領域の代わりに設けられ、各々の前記露光領域の前記少なくとも2つの制御モジュール領域が、前記第2の方向に延在する互いからの平均距離を隔てて配置され、前記平均距離が、前記第2の方向に延在する前記露光領域の一辺の辺長の少なくとも4分の1に等しい、ウエハ。
- 前記平均距離が、前記第2の方向に延在する前記露光領域の一辺の全辺長から前記第2の方向に延在する前記格子領域の一辺の辺長を減算したものに等しい、請求項1に記載のウエハ。
- 各々の前記露光領域が長方形に設計され、4つの前記制御モジュール領域が各々の前記露光領域に設けられ、各々の前記制御モジュール領域が当該露光領域の角領域に配置される、請求項1に記載のウエハ。
- 1つの前記露光領域に設けられた各々の前記制御モジュール領域が1つの格子領域のみの代わりに設けられる、請求項1に記載のウエハ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03104955 | 2003-12-23 | ||
PCT/IB2004/052723 WO2005064408A2 (en) | 2003-12-23 | 2004-12-09 | Wafer with optical control modules in exposure fields |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007517392A true JP2007517392A (ja) | 2007-06-28 |
Family
ID=34717251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006546426A Withdrawn JP2007517392A (ja) | 2003-12-23 | 2004-12-09 | 露光領域において光学制御モジュールを有するウエハ |
Country Status (6)
Country | Link |
---|---|
US (1) | US7538444B2 (ja) |
EP (1) | EP1700162A2 (ja) |
JP (1) | JP2007517392A (ja) |
KR (1) | KR20060110334A (ja) |
CN (1) | CN1898607A (ja) |
WO (1) | WO2005064408A2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009007931A1 (en) * | 2007-07-12 | 2009-01-15 | Nxp B.V. | Wafer, reticle and method for manufacturing integrated circuits on a wafer |
US9620456B2 (en) | 2007-07-12 | 2017-04-11 | Nxp B.V. | Integrated circuits on a wafer and methods for manufacturing integrated circuits |
US9798228B2 (en) | 2015-09-29 | 2017-10-24 | Nxp B.V. | Maximizing potential good die per wafer, PGDW |
US10942444B2 (en) | 2019-05-01 | 2021-03-09 | Nxp Usa, Inc. | Optical control modules for integrated circuit device patterning and reticles and methods including the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4343877A (en) * | 1981-01-02 | 1982-08-10 | Amdahl Corporation | System for design and production of integrated circuit photomasks and integrated circuit devices |
DE4108576A1 (de) * | 1991-03-14 | 1992-09-17 | Mikroelektronik Und Technologi | Belichtungsverfahren zur uebertragung von strukturen |
JP3112745B2 (ja) * | 1992-06-17 | 2000-11-27 | 富士通株式会社 | パターン形成用導電性組成物及び該組成物を用いたパターン形成方法 |
US6005294A (en) * | 1996-05-29 | 1999-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method of arranging alignment marks |
JP4301584B2 (ja) | 1998-01-14 | 2009-07-22 | 株式会社ルネサステクノロジ | レチクル、それを用いた露光装置、露光方法および半導体装置の製造方法 |
US6737207B2 (en) * | 2000-04-25 | 2004-05-18 | Nikon Corporation | Method for evaluating lithography system and method for adjusting substrate-processing apparatus |
TW588414B (en) * | 2000-06-08 | 2004-05-21 | Toshiba Corp | Alignment method, overlap inspecting method and mask |
-
2004
- 2004-12-09 JP JP2006546426A patent/JP2007517392A/ja not_active Withdrawn
- 2004-12-09 EP EP04801511A patent/EP1700162A2/en not_active Withdrawn
- 2004-12-09 CN CNA2004800384203A patent/CN1898607A/zh active Pending
- 2004-12-09 KR KR1020067012584A patent/KR20060110334A/ko not_active Application Discontinuation
- 2004-12-09 WO PCT/IB2004/052723 patent/WO2005064408A2/en not_active Application Discontinuation
- 2004-12-09 US US10/584,504 patent/US7538444B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2005064408A3 (en) | 2006-03-02 |
US20070152303A1 (en) | 2007-07-05 |
KR20060110334A (ko) | 2006-10-24 |
CN1898607A (zh) | 2007-01-17 |
EP1700162A2 (en) | 2006-09-13 |
US7538444B2 (en) | 2009-05-26 |
WO2005064408A2 (en) | 2005-07-14 |
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