WO2009007931A1 - Wafer, reticle and method for manufacturing integrated circuits on a wafer - Google Patents

Wafer, reticle and method for manufacturing integrated circuits on a wafer Download PDF

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Publication number
WO2009007931A1
WO2009007931A1 PCT/IB2008/052780 IB2008052780W WO2009007931A1 WO 2009007931 A1 WO2009007931 A1 WO 2009007931A1 IB 2008052780 W IB2008052780 W IB 2008052780W WO 2009007931 A1 WO2009007931 A1 WO 2009007931A1
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WO
WIPO (PCT)
Prior art keywords
wafer
exposure
exposure fields
reticle
integrated circuits
Prior art date
Application number
PCT/IB2008/052780
Other languages
French (fr)
Inventor
Heimo Scheucher
Original Assignee
Nxp B.V.
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009007931A1 publication Critical patent/WO2009007931A1/en

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70066—Size and form of the illuminated area in the mask plane, e.g. reticle masking blades or blinds
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A wafer (2) comprises a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer (2), first and second saw lines (4, 5) separating the integrated circuits (1), and a plurality of process control modules (6) formed on the wafer (2). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows, and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y) defined by the columns. The plurality of process control modules (6) are formed on the wafer (2) such that a given process control module (6) of the plurality of process modules (6) is bounded by two consecutive first saw lines (4), is bounded by two consecutive second saw lines (5), or is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).

Description

- -
Wafer, reticle and method for manufacturing integrated circuits on a wafer
FIELD OF THE INVENTION
The invention relates to a wafer, to a reticle and to a method for manufacturing integrated circuits on a wafer.
BACKGROUND OF THE INVENTION
Integrated circuits are usually produced by forming a plurality of integrated circuits on a semiconductor wafer by repeatedly exposing the wafer to a reticle mask utilizing a stepper, thereby forming a plurality of exposed areas arranged on the wafer surface. The image of the mask pattern is printed on a resist layer applied on the wafer surface and developed to form a resist pattern used as a mask for, for instance, etching a layer formed on the wafer surface. The integrated circuits are formed by repeating these processes. The individual integrated circuits are separated by saw lines used for a successive separation step.
In addition to the integrated circuits, test devices for measuring electric characteristics are also formed on the wafer. The test devices are usually known as process control modules (PCM), may include active or passive electric devices, such as transistors or resistive tracks, and are usually located within the saw lines.
Published U.S. application for patent No. 2003/0017631 Al discloses a reticle including a device pattern region, in which a plurality of mask patterns of semiconductor device chips is formed, and including a test element group (TEG) pattern region formed on one side of the device pattern region. The TEG pattern region is provided for arranging patterns of TEGs and alignment marks for the exposing apparatus. The lateral dimension of the TEG pattern region is the same as that of the device pattern region. The width, i.e. the vertical dimension, of the TEG pattern region corresponds to two rows of the semiconductor device chip patterns. When producing the chips on the wafer, first, only the device pattern region is repeatedly projected on the wafer, wherein the remaining parts of the wafer and the TEG pattern region are covered by a mask blind. Next, the device pattern region and the TEG pattern region are simultaneously projected on the wafer, wherein the remaining wafer is covered by the mask blind. Then, only the device pattern region is repeatedly projected on the wafer again. In this state, a plurality of exposed areas including only the device regions is - -
arranged with a fixed pitch in the horizontal direction. A TEG region is also formed by the simultaneous projection of the device pattern region and the TEG pattern region.
Next, only the device pattern region is repeatedly projected again, and a portion of the device region is projected at a position adjacent to the position in which both the device pattern region and the TEG pattern region are projected. When only a portion of the device pattern region is projected, a lower end of the upper mask blind is shifted so as to cover the top two rows of the device chip pattern of the device pattern region. In consideration of the alignment pattern region of the mask blind, the lower end of the mask blind must be further shifted to the upper direction. Otherwise, the mask blind might cover a portion of the third row of the device chip patterns, and defective patterns might be formed on the semiconductor wafer.
OBJECT AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide integrated circuits on a wafer whose production can be simplified and a simplified method for producing such integrated circuits on the wafer.
The object is achieved in accordance with the invention by means of a wafer, comprising a plurality of integrated circuits formed lattice-like in rows and columns on the wafer; first and second saw lines separating the integrated circuits, the first saw lines running (i.e. being arranged) parallel and equidistant with respect to each other in a first direction defined by the rows, and the second saw lines running parallel and equidistant with respect to each other in a second direction defined by the columns; and a plurality of process control modules formed on the wafer such that a given process control module of the plurality of process modules is bounded by two consecutive first saw lines, is bounded by two consecutive second saw lines, or is bounded by two consecutive first saw lines as well as by two consecutive second saw lines.
The inventive wafer comprises the integrated circuits and the process control modules formed thereon, i.e. on a wafer surface. The integrated circuits are formed on the wafer in rows and columns and are separated by the first and second saw lines, thus forming a grid on the wafer surface. The first saw lines run parallel and equidistant with respect to each other and form the rows, and the second saw lines run parallel and equidistant with respect to each other and form the columns of the wafer. The first and second directions are - -
thus orthogonal to each other.
Besides the integrated circuits, the inventive wafer comprises the process control modules formed on the wafer, wherein a given process control module of the plurality of process modules is bounded by two consecutive first saw lines, is bounded by two consecutive second saw lines, or is bounded by two consecutive first saw lines as well as by two consecutive second saw lines. As a result, a process control module is not wider or longer than the integrated circuits, so that they fit either within a single row limited by two consecutive first saw lines or within a single column limited by two consecutive second saw lines. Alternatively, the individual process modules may have an area not greater than the area of a single integrated circuit and, thus being delimited by two consecutive first saw lines and by two consecutive second saw lines.
Process control modules, usually abbreviated as PCM, are known per se in the art. Process control modules are test devices for measuring electric characteristics of the wafer. Process control modules may include active or passive electric devices, such as transistors or resistive tracks.
The integrated circuits and the process control modules are particularly formed on the wafer utilizing a reticle. When manufacturing the integrated circuits on the wafer, an area of the wafer corresponding to the reticle is exposed and then the reticle is moved to a further area of the wafer utilizing a stepper. The area exposed by the reticle is an exposure field. Since the process control modules are bounded by either two consecutive first or second saw lines, each first or each second saw line is a continuous saw line not interrupted by a process control module. This eases the conditions for a reliable alignment during the production of the integrated circuits on the wafer utilizing the reticle and the stepper.
In one embodiment of the inventive wafer, the wafer further comprises a plurality of rectangular shaped first exposure fields, each comprising rows and columns defined by the first and second saw lines, and each comprising some of the integrated circuits and no process control modules; and a plurality of rectangular shaped second exposure fields, each comprising rows and columns defined by the first and second saw lines, and each comprising some of the integrated circuits and at least one of the process control modules. The first and second exposure fields are part of the wafer surface on which the integrated circuits and the process control modules are formed on. The first and second exposure fields are rectangular shaped and comprise each several rows and columns. While each second exposure field comprises at least one process control module and several integrated circuits, each first exposure control field only comprises integrated circuits and no process control modules. The - -
process control module of a relevant second process module, thus, fits either within a single row limited by two consecutive first saw lines or within a single column limited by two consecutive second saw lines of the relevant second exposure field. The process control module of a relevant second exposure field may particularly be located next to a boundary of the relevant second exposure field.
The first and second exposure fields may have the same number of rows, wherein the second exposure fields have one more column than the first exposure fields, and the process control modules of the second exposure fields run within a column located next to boundaries of the second exposure fields, or the first and second exposure fields may have the same number of columns, the second exposure field have one more row than the first exposure fields, and the process control modules of the second exposure fields run within a row located next to boundaries of the second exposure fields. Then, the second exposure field comprises a first area corresponding to the first exposure field and a second area, which is either a row or a column comprising the process control modules. When manufacturing this variant of the inventive wafer, then a single reticle can be used. When forming the integrated circuits of the second exposure fields and the process control modules, then the part of the wafer surface associated with the relevant second exposure field is exposed through the entire reticle. When forming the integrated circuits of the first exposure fields, then the second reticle area, i.e. the part of the reticle used for forming the process control modules, is covered and the part of the wafer surface associated with the first area of the second relevant exposure field is exposed through the first reticle area.
The process control module of a relevant second exposure field may run along an entire single row or an entire single column of the relevant second exposure field. The process control module may also run along a single row or a single column of the relevant second exposure field, wherein at least one of the integrated circuits is formed on the wafer within the same single row or single column, respectively. This may result in an increased number of integrated circuits on the inventive wafer.
In order to align the reticle during manufacturing the integrated circuits on the wafer, each first and second exposure field may comprise an optical control module formed on the wafer, each optical control module being bounded by two consecutive first saw lines, by two consecutive second saw lines, or by two consecutive first saw lines as well as by two consecutive second saw lines. Optical control modules per se are well known in the art and are in this context alignment marks formed on the wafer and used for automatically aligning the reticle during the process of manufacturing the integrated circuits on the wafer. Optical - -
control modules may be comprised of square, rectangular or cross-shaped interference fields particularly automatically detectable by the stepper used for the reticle. Automatic alignment utilizing the optical control modules may be accomplished by passing low-energy laser beams through alignment marks on the reticle and reflecting them off corresponding alignment marks, i.e. the optical control modules, on the wafer surface. An optical control module may particularly have a three dimensional structure such that is can be used for each exposure step during the manufacture of the integrated circuits on the wafer.
Particularly, if the second exposure fields of the inventive wafer comprise first and second areas, wherein the first areas correspond to the first exposure fields and comprise integrated circuits but no process control modules, the second area may be a row or a column adjoining a boundary of the relevant second exposure field and comprising one of the process control modules. Then, the optical process modules of the second exposure fields may be located within the first area at corresponding locations that also correspond to locations where the optical control modules are formed on the wafer within the first exposure fields. Then, the same reticle used for exposing the first and second exposure fields can be aligned utilizing the optical process modules in a relatively simple manner.
In one embodiment of the inventive wafer, each first and second exposure field comprises a plurality of optical control modules, particularly formed in the four corners of the first exposure fields and the first areas of the second exposure fields. This may improve alignment of the reticle during forming the integrated circuits on the wafer.
For producing the inventive wafer, a reticle comprising first and second reticle areas can be utilized, wherein the first reticle area is adapted to from the first exposure fields and the first area of the second exposure fields, and the second reticle area is adapted to form the second area of the second exposure fields. This reticle may also include alignment marks corresponding to the optical control modules. Utilizing such a reticle, the integrated circuits on the inventive wafer can be manufactured, comprising the steps of: setting the reticle comprising the first and second reticle areas in an exposing apparatus; the first reticle area being adapted to form the first exposure fields and the first areas of the second exposure fields, and the second reticle area being adapted to form the second areas of the second exposure fields; positioning a semiconductor wafer comprising a resist layer in the exposing apparatus; forming the first exposure fields in the resist layer of the wafer by first exposures through parts of the reticle by covering the second reticle areas; and - -
forming the second exposure fields in the resist layer of the wafer by second exposures t hhrroouugghh tthhee eennttiirree rreettiiccllee..
BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in greater detail hereinafter, by way of non- limiting examples, with reference to the embodiments shown in the drawings. Fig. 1 is a top-view of a plurality of integrated circuits on a wafer; Fig. 2 is a part of the top-view of Fig. 1; Fig. 3 is a reticle and a stepper; Fig. 4 a flow chart illustrating the manufacture of the plurality of integrated circuits on the wafer of Fig. 1; and
Figs. 5 and 6 are several steps during the manufacture of the plurality of integrated circuits on the wafer of Fig. 1.
DESCRIPTION OF EMBODIMENTS
Fig. 1 shows a top-view of a plurality of integrated circuits 1 on a semiconductor wafer 2 and Fig. 2 shows a detail of this top-view. The integrated circuits 1 may have been formed on the wafer 2 as it will be explained below.
The integrated circuits 1 on the wafer 2 are separated by first saw lines 4 running parallel in a first direction x and by second saw lines 5 running parallel in a second direction y. The first and second saw lines 4, 5 are each spaced apart such that two consecutive first saw lines 4 are equidistant and two consecutive second saw lines 5 are equidistant. Therefore, the integrated circuits 1 are formed on the wafer 2 in rows running in the first direction x and columns running in the second direction y. In addition to the integrated circuits 1 , process control modules 6 and optical control modules 7 are formed on the wafer 2. The process control modules 6 are test devices for measuring electric characteristics of the wafer 2 and may include active or passive electric devices, such as transistors or resistive tracks. The optical control modules 7 are alignment marks formed on the wafer 2 and used for automatically aligning a reticle 31 shown in Fig. 3 during the process of manufacturing the integrated circuits 1 on the wafer 2 for the exemplary embodiment. The optical control modules 7 may be comprised of square, rectangular or cross-shaped interference fields particularly automatically detectable by a stepper 32 used for the reticle 31. Automatic alignment utilizing the optical control modules 7 may be accomplished by passing low-energy laser beams through alignment marks 37 on the reticle - -
31 and reflecting them off corresponding alignment marks, i.e. the optical control modules 7, on the wafer surface. The optical control modules 7 may particularly have a three dimensional structure such that they can be used for each exposure step during the manufacture of the integrated circuits 1 on the wafer 2. For the exemplary embodiment, each process control module 6 fits within a single column, but extends in the second direction y corresponding to several integrated circuits 1. Thus, each process control module 6 is delimitated by two consecutive second saw lines 5. Alternatively, the process control modules 6 can be located within a single row, and thus be delimitated by two consecutive first saw lines 4. It is also possible that each process control module 6 is delimitated by both, two consecutive first and two consecutive second saw lines 4, 5.
Since for the exemplary embodiment the integrated circuits 1 have been formed on the wafer 2 utilizing the reticle 31 and the stepper 32, the wafer surface on which the integrated circuits 1 are formed on is comprised of several exposure fields 8, 9, of which Fig. 1 shows only the second exposure fields 9. During manufacturing of the integrated circuits 1 on the wafer 2, an area of the wafer 2 corresponding to the reticle 31 is exposed and then the reticle 31 is moved to a further area of the wafer 2 utilizing the stepper 32. The area having been exposed by the reticle 31 is one of the exposure fields 8, 9. For the exemplary embodiment, the wafer surface comprises five second exposure fields 9 each comprising a single process control module 6. The remaining wafer surface comprises first exposure fields 8.
For the exemplary embodiment, the wafer surface is comprised of several first exposure fields 8 and several second exposure fields 9. Each second exposure field 9 further comprises a first area 9a and a second area 9b. The first areas 9a of the second exposure fields 9 and the first exposure fields 8 comprise integrated circuits 1, but no process control modules 6. The second areas 9b of the second exposure fields 9 comprise the process control modules 6 and, for the exemplary embodiment, also some integrated circuits 1. It is also possible that the second areas 9b do not include any integrated circuits 1 and do only include process control modules 6. For the exemplary embodiment, each optical control module 7 fits within a single row, but extends in the first direction x corresponding to several integrated circuits 1. Thus, each optical control module 7 is delimitated by two consecutive first saw lines 4. Alternatively, the optical control modules 7 can be located within a single column, and thus be delimitated by two consecutive second saw lines 5. It is also possible that each optical control module 7 is delimitated by both, two consecutive first and two consecutive second saw lines 4, 5.
Furthermore, each first and second exposure field 8, 9 comprises for the exemplary embodiment four optical control modules 7 which are located in the four corners of the first exposure fields 8 and in the four corners of the first areas 9a of the second exposure fields 9. As a result, the structure of the first areas 9a of the second exposure fields 9 is similar to the structure of the first exposure fields 8 or, in other word, the first areas 9a of the second exposure fields 9 correspond to the first exposure fields 8.
Fig. 4 shows a flow chart illustrating the manufacture of the integrated circuits 1 on the wafer 2 and figures 5 and 6 show steps during manufacture of the integrated circuits 1 on the wafer 2.
At the beginning, the reticle 31 is set in the stepper 32 and the wafer 2 is positioned in the stepper 32, step A of the flow chart.
The reticle 31 comprises first and second reticle areas 31a, 31b. The first reticle area 31a corresponds to the first exposure field 8 and to the first area 9a of the second exposure field 9 and the second reticle area 31b corresponds to the second area 9b of the second exposure field 9. Thus, when exposing, for instance, a resist layer of the wafer 2 through the reticle 31, the first reticle area 31a of the reticle 31 results in an image of the pattern of the first area 31a which will ultimately form the integrated circuits 1 of the first exposure fields 8 and the first areas 9a of the second exposure fields 9. The exposure of the wafer 2 through the second reticle area 31b ultimately results in forming the integrated circuits 1 and the process control modules 6 of the second areas 9b of the second exposure fields. Therefore, the pattern of the first reticle area 31a corresponds to the pattern of the first areas 9a of the second exposure fields 9 and the pattern of the first exposure fields 8, and the pattern of the second reticle area 31b corresponds to the pattern of the second areas 9b of the second exposure fields 9. The pattern of the reticle 31 which form the integrated circuits 1 are denoted by the reference signs "Ia" and the pattern of reticle 31 which form the process control modules 6 are denoted by the reference signs "6a"
The reticle 31 further comprises alignment marks 37 located at the four corners of the first reticle area 31a. The alignment marks 37 are used for automatically aligning the stepper 32 during the manufacture of the integrated circuits 1 on the wafer 2. This may be accomplished by utilizing a laser 33 which may pass low-energy laser beams through the alignment marks 37 on the reticle 31. The low-energy laser beams may be reflected off the corresponding optical control modules 7 on the wafer surface. - -
After setting the reticle 31 and positioning the wafer 2 in the stepper 32, the first exposure fields 8 are formed on the wafer surface by exposures through the reticle 31 , wherein the second reticle area 31b of the reticle is covered, step B of the flow chart, and the second exposure fields 9 are formed on the wafer surface by exposures through the entire reticle 31, step C of the flow chart.
For forming the first exposure fields 8 or for forming the integrated circuits 1 of the first exposure fields 8, the second reticle area 31b is covered by a mask blind 51 as shown in Fig. 5. Furthermore, the remaining wafer surface is covered by mask blinds 52-54.
When forming the second exposure fields 9, the mask blind 51 is shifted such that the projection through the second reticle area 3 Ib on the wafer surface is also possible. This scenario is depicted in Fig. 6.
For the exemplary embodiment, the stepper 32 moves the reticle 31 over the wafer surface in order to form successively the first and second exposure areas 8, 9. If a first exposure area 8 has to be formed, then the second reticle area 31b is covered by the mask blind 51, and if a second exposure area 9 has to be formed, then the second reticle area 31b is cleared such that the process control module 6 and the integrated circuits 1 of the second area 9b of the relevant second exposure field 9 can be formed on the wafer 2.
Finally, it should be noted that the aforementioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

- -CLAIMS:
1. A wafer, comprising a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer (2); first and second saw lines (4, 5) separating the integrated circuits (1), the first saw lines (4) being arranged parallel and equidistant with respect to each other in a first direction (x) defined by the rows, and the second saw lines (5) being arranged parallel and equidistant with respect to each other in a second direction (y) defined by the columns; and a plurality of process control modules (6) formed on the wafer (2) such that a given process control module (6) of the plurality of process modules (6) is bounded by two consecutive first saw lines (4), is bounded by two consecutive second saw lines (5), or is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).
2. The wafer of claim 1, further comprising a plurality of rectangular shaped first exposure fields (8), each comprising rows and columns defined by the first and second saw lines (4, 5), and each comprising some of the integrated circuits (1) and no process control modules (6); and a plurality of rectangular shaped second exposure fields (9), each comprising rows and columns defined by the first and second saw lines (4, 5), and each comprising some of the integrated circuits (1) and at least one of the process control modules (6).
3. The wafer of claim 2, wherein the at least one process control module (6) is located next to a boundary of the relevant second exposure field (9).
4. The wafer of claim 2, wherein the first and second exposure fields (8, 9) comprise the same number of rows, the second exposure fields (9) comprise one more column than the first exposure fields (8), and the process control modules (6) of the second exposure fields (9) run within a column located next to boundaries of the second exposure fields (9); or wherein the first and second exposure fields (8, 9) comprise the same number of columns, - -
the second exposure fields (9) comprise one more row than the first exposure fields (8), and the process control modules (6) of the second exposure fields (9) run within a row located next to boundaries of the second exposure fields (9).
5. The wafer of claim 2, wherein the process control module (6) of a relevant second exposure field (9) runs along an entire single row of the relevant second exposure field (9); the process control module (6) of a relevant second exposure field (9) runs along a single row of the relevant second exposure field (9), wherein at least one of the integrated circuits (1) is formed on the wafer (2) within the same single row; the process control module (6) of a relevant second exposure field (9) runs along an entire single column of the relevant second exposure field (9); or the process control module (6) of a relevant second exposure field (9) runs along a single column of the relevant second exposure field (9), wherein at least one of the integrated circuits (1) is formed on the wafer (2) within the same single column.
6. The wafer of claim 2, wherein each of the first and second exposure fields (8, 9) comprises an optical control module (7) formed on the wafer (2), each optical control module (7) being bounded by two consecutive first saw lines (4), by two consecutive second saw lines (5), or by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).
7. The wafer of claim 6, wherein each second exposure field (9) comprises first and second areas (9a, 9b), the first areas (9a) corresponding to the first exposure fields (8) and comprising integrated circuits (1) and no process control modules (6), and the second area (9b) being a row or a column adjoining a boundary of the second exposure field (9) and comprising the process control module (6); wherein the optical process modules (7) of the second exposure fields (9) are located within the first area (9a) at corresponding locations which also correspond to locations where the optical control modules (7) are formed on the wafer (2) within the first exposure fields (8).
8. The wafer of claim 7, wherein each first and second exposure field (8, 9) comprises a plurality of optical control modules (7), particularly formed in the four corners of the first exposure fields (8) and the first areas (9a) of the second exposure fields (9). - -
9. A reticle for producing a wafer according to claims 7 or 8, comprising first and second reticle areas (31a, 31b); the first reticle area (31a) being adapted to from the first exposure fields (8) and the first areas (9a) of the second exposure fields (9), and the second reticle area (3 Ib) being adapted to form the second areas (9b) of the second exposure fields (9).
10. A method for manufacturing integrated circuits on a wafer according to claim 7 or 8, comprising the steps of: setting a reticle (31) comprising first and second reticle areas (3 Ia, 3 Ib) in an exposing apparatus (32); the first reticle area (31a) being adapted to form the first exposure fields (8) and the first areas (9a) of the second exposure fields (9), and the second reticle area (31b) being adapted to form the second areas (9b) of the second exposure fields (9); positioning a semiconductor wafer (2) comprising a resist layer in the exposing apparatus (32); forming the first exposure fields (8) in the resist layer of the wafer (2) by first exposures through parts of the reticle (31) by covering the second reticle area (31b); and forming the second exposure fields (9) in the resist layer of the wafer (2) by second exposures through the entire reticle (31).
PCT/IB2008/052780 2007-07-12 2008-07-10 Wafer, reticle and method for manufacturing integrated circuits on a wafer WO2009007931A1 (en)

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EP07112368.1 2007-07-12

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Citations (6)

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Publication number Priority date Publication date Assignee Title
JPH05291106A (en) * 1992-04-15 1993-11-05 Sanyo Electric Co Ltd Exposure method for semiconductor wafer
JPH06289595A (en) * 1993-04-05 1994-10-18 Matsushita Electric Ind Co Ltd Reticle for reduction stepper
US20020117735A1 (en) * 2001-02-27 2002-08-29 U.S. Philips Corporation Semiconductor wafer with process control modules
US20030017631A1 (en) * 1999-11-09 2003-01-23 Kawasaki Microelectronics, Inc. Method of arranging exposed areas including a limited number of TEG regions on a semiconductor wafer
JP2004252064A (en) * 2003-02-19 2004-09-09 Denso Corp Reticle and exposure method of semiconductor wafer
US20070152303A1 (en) * 2003-12-23 2007-07-05 Heimo Scheucher Wafer with optical control modules in exposure fields

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291106A (en) * 1992-04-15 1993-11-05 Sanyo Electric Co Ltd Exposure method for semiconductor wafer
JPH06289595A (en) * 1993-04-05 1994-10-18 Matsushita Electric Ind Co Ltd Reticle for reduction stepper
US20030017631A1 (en) * 1999-11-09 2003-01-23 Kawasaki Microelectronics, Inc. Method of arranging exposed areas including a limited number of TEG regions on a semiconductor wafer
US20020117735A1 (en) * 2001-02-27 2002-08-29 U.S. Philips Corporation Semiconductor wafer with process control modules
JP2004252064A (en) * 2003-02-19 2004-09-09 Denso Corp Reticle and exposure method of semiconductor wafer
US20070152303A1 (en) * 2003-12-23 2007-07-05 Heimo Scheucher Wafer with optical control modules in exposure fields

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