JP2007511894A5 - - Google Patents

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Publication number
JP2007511894A5
JP2007511894A5 JP2006532518A JP2006532518A JP2007511894A5 JP 2007511894 A5 JP2007511894 A5 JP 2007511894A5 JP 2006532518 A JP2006532518 A JP 2006532518A JP 2006532518 A JP2006532518 A JP 2006532518A JP 2007511894 A5 JP2007511894 A5 JP 2007511894A5
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JP
Japan
Prior art keywords
semiconductor wafer
solution
solvent
cmp
post
Prior art date
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Pending
Application number
JP2006532518A
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English (en)
Japanese (ja)
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JP2007511894A (ja
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Publication date
Priority claimed from US10/431,053 external-priority patent/US7188630B2/en
Application filed filed Critical
Publication of JP2007511894A publication Critical patent/JP2007511894A/ja
Publication of JP2007511894A5 publication Critical patent/JP2007511894A5/ja
Pending legal-status Critical Current

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JP2006532518A 2003-05-07 2004-04-30 半導体製造プロセスの過程で導電面を不動態化するための方法 Pending JP2007511894A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/431,053 US7188630B2 (en) 2003-05-07 2003-05-07 Method to passivate conductive surfaces during semiconductor processing
PCT/US2004/013373 WO2004102620A2 (en) 2003-05-07 2004-04-30 Method to passivate conductive surfaces during semiconductor processing

Publications (2)

Publication Number Publication Date
JP2007511894A JP2007511894A (ja) 2007-05-10
JP2007511894A5 true JP2007511894A5 (https=) 2007-06-21

Family

ID=33416375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006532518A Pending JP2007511894A (ja) 2003-05-07 2004-04-30 半導体製造プロセスの過程で導電面を不動態化するための方法

Country Status (7)

Country Link
US (2) US7188630B2 (https=)
EP (1) EP1625247A2 (https=)
JP (1) JP2007511894A (https=)
KR (1) KR101059006B1 (https=)
CN (1) CN1784513A (https=)
TW (1) TW200504855A (https=)
WO (1) WO2004102620A2 (https=)

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US20080207005A1 (en) * 2005-02-15 2008-08-28 Freescale Semiconductor, Inc. Wafer Cleaning After Via-Etching
WO2006125461A1 (en) * 2005-05-25 2006-11-30 Freescale Semiconductor, Inc Treatment solution and method of applying a passivating layer
WO2006125462A1 (en) * 2005-05-25 2006-11-30 Freescale Semiconductor, Inc Cleaning solution for a semiconductor wafer
US20090045164A1 (en) * 2006-02-03 2009-02-19 Freescale Semiconductor, Inc. "universal" barrier cmp slurry for use with low dielectric constant interlayer dielectrics
WO2007102138A2 (en) * 2007-01-02 2007-09-13 Freescale Semiconductor, Inc. Barrier slurry compositions and barrier cmp methods
US7803719B2 (en) * 2006-02-24 2010-09-28 Freescale Semiconductor, Inc. Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and passivating coupling material comprising multiple organic components for use in a semiconductor device
WO2007095973A1 (en) * 2006-02-24 2007-08-30 Freescale Semiconductor, Inc. Integrated system for semiconductor substrate processing using liquid phase metal deposition
US20100273330A1 (en) * 2006-08-23 2010-10-28 Citibank N.A. As Collateral Agent Rinse formulation for use in the manufacture of an integrated circuit
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US8097535B2 (en) * 2006-09-04 2012-01-17 Nxp B.V. Fabrication of self-assembled nanowire-type interconnects on a semiconductor device
KR101202720B1 (ko) * 2008-02-29 2012-11-19 주식회사 엘지화학 화학적 기계적 연마용 수계 슬러리 조성물 및 화학적 기계적 연마 방법
JP2009238896A (ja) * 2008-03-26 2009-10-15 Renesas Technology Corp 半導体集積回路装置の製造方法
US8580656B2 (en) * 2008-07-14 2013-11-12 Air Products And Chemicals, Inc. Process for inhibiting corrosion and removing contaminant from a surface during wafer dicing and composition useful therefor
US20100215841A1 (en) 2009-02-20 2010-08-26 E.I. Du Pont De Nemours And Company Process for inhibiting oxide formation on copper surfaces
US8088690B2 (en) 2009-03-31 2012-01-03 International Business Machines Corporation CMP method
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US20110045203A1 (en) * 2009-08-21 2011-02-24 E. I. Du Pont De Nemours And Company Process for inhibiting oxide formation on copper surfaces
US20110117696A1 (en) * 2009-11-19 2011-05-19 Air Liquide Electronics U.S. Lp CdTe SURFACE TREATMENT FOR STABLE BACK CONTACTS
CN102110641A (zh) * 2009-12-29 2011-06-29 中芯国际集成电路制造(上海)有限公司 在化学机械研磨过程中防止钨塞凹陷缺陷的方法
US8883701B2 (en) 2010-07-09 2014-11-11 Air Products And Chemicals, Inc. Method for wafer dicing and composition useful thereof
KR20130084932A (ko) * 2012-01-18 2013-07-26 삼성전자주식회사 반도체 소자의 제조 방법
US9481855B2 (en) * 2012-09-17 2016-11-01 Ekc Technology Inc Cleaning composition and method for cleaning a semiconductor device substrate after chemical mechanical polishing
US8920567B2 (en) 2013-03-06 2014-12-30 International Business Machines Corporation Post metal chemical-mechanical planarization cleaning process
JP6542766B2 (ja) 2013-10-23 2019-07-10 ドンジン セミケム カンパニー リミテッドＤｏｎｇｊｉｎ Ｓｅｍｉｃｈｅｍ Ｃｏ．， Ｌｔｄ． 金属膜研磨スラリー組成物、及びこれを利用した金属膜研磨時に発生するスクラッチの減少方法
US9971073B2 (en) * 2014-04-14 2018-05-15 Corning Incorporated Enhanced performance metallic based optical mirror substrates
US9666447B2 (en) 2014-10-28 2017-05-30 Tokyo Electron Limited Method for selectivity enhancement during dry plasma etching
CN108250977B (zh) * 2016-12-28 2021-08-27 安集微电子科技（上海）股份有限公司 一种用于阻挡层平坦化的化学机械抛光液
US10181408B2 (en) * 2017-01-31 2019-01-15 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Chemical mechanical polishing method for tungsten using polyglycols and polyglycol derivatives
CN111863592B (zh) * 2019-04-29 2023-11-10 中芯国际集成电路制造(上海)有限公司 研磨后清洗方法以及半导体结构的形成方法
CN110965115A (zh) * 2020-01-02 2020-04-07 荆门德威格林美钨资源循环利用有限公司 一种钛合金表面氧化层的去除方法
CN112246747B (zh) * 2020-09-30 2021-09-17 青岛金汇源电子有限公司 一种连续式半导体晶圆蚀刻设备

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US6660638B1 (en) * 2002-01-03 2003-12-09 Taiwan Semiconductor Manufacturing Company CMP process leaving no residual oxide layer or slurry particles
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US7188630B2 (en) * 2003-05-07 2007-03-13 Freescale Semiconductor, Inc. Method to passivate conductive surfaces during semiconductor processing

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