JP2007511099A - フォトレジストストリッピングの間のバリヤー物質損失の最小化 - Google Patents

フォトレジストストリッピングの間のバリヤー物質損失の最小化 Download PDF

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Publication number
JP2007511099A
JP2007511099A JP2006539755A JP2006539755A JP2007511099A JP 2007511099 A JP2007511099 A JP 2007511099A JP 2006539755 A JP2006539755 A JP 2006539755A JP 2006539755 A JP2006539755 A JP 2006539755A JP 2007511099 A JP2007511099 A JP 2007511099A
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JP
Japan
Prior art keywords
layer
silicon
gas mixture
photoresist
dielectric
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Pending
Application number
JP2006539755A
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English (en)
Japanese (ja)
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JP2007511099A5 (enExample
Inventor
アナプラゲイダ，ラオ
ツー，ヘレン
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Lam Research Corp
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Lam Research Corp
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Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of JP2007511099A publication Critical patent/JP2007511099A/ja
Publication of JP2007511099A5 publication Critical patent/JP2007511099A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2006539755A 2003-11-12 2004-11-09 フォトレジストストリッピングの間のバリヤー物質損失の最小化 Pending JP2007511099A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/712,326 US20050101135A1 (en) 2003-11-12 2003-11-12 Minimizing the loss of barrier materials during photoresist stripping
PCT/US2004/037376 WO2005048335A1 (en) 2003-11-12 2004-11-09 Minimizing the loss of barrier materials during photoresist stripping

Publications (2)

Publication Number Publication Date
JP2007511099A true JP2007511099A (ja) 2007-04-26
JP2007511099A5 JP2007511099A5 (enExample) 2007-10-18

Family

ID=34552671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539755A Pending JP2007511099A (ja) 2003-11-12 2004-11-09 フォトレジストストリッピングの間のバリヤー物質損失の最小化

Country Status (8)

Country Link
US (1) US20050101135A1 (enExample)
EP (1) EP1683192A1 (enExample)
JP (1) JP2007511099A (enExample)
KR (1) KR20060123144A (enExample)
CN (1) CN1868039A (enExample)
IL (1) IL174648A0 (enExample)
TW (1) TW200524051A (enExample)
WO (1) WO2005048335A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011100765A (ja) * 2009-11-04 2011-05-19 Fujitsu Semiconductor Ltd 半導体素子の製造方法
JP4825911B2 (ja) * 2006-03-24 2011-11-30 アプライド マテリアルズ インコーポレイテッド 介在チャンバでの脱フッ素化及びウェハ脱フッ素化ステップによるプラズマエッチング及びフォトレジストストリッププロセス

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7517801B1 (en) * 2003-12-23 2009-04-14 Lam Research Corporation Method for selectivity control in a plasma processing system
US8222155B2 (en) * 2004-06-29 2012-07-17 Lam Research Corporation Selectivity control in a plasma processing system
US7396769B2 (en) * 2004-08-02 2008-07-08 Lam Research Corporation Method for stripping photoresist from etched wafer
US7479457B2 (en) * 2005-09-08 2009-01-20 Lam Research Corporation Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof
JP2007180420A (ja) * 2005-12-28 2007-07-12 Fujitsu Ltd 半導体装置の製造方法及び磁気ヘッドの製造方法
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
US20090078675A1 (en) * 2007-09-26 2009-03-26 Silverbrook Research Pty Ltd Method of removing photoresist
WO2009039551A1 (en) * 2007-09-26 2009-04-02 Silverbrook Research Pty Ltd Method of removing photoresist
CN102877041B (zh) * 2011-07-14 2014-11-19 中国科学院微电子研究所 薄膜沉积方法以及半导体器件制造方法
CN102610511A (zh) * 2012-03-21 2012-07-25 中微半导体设备(上海)有限公司 光刻胶的去除方法
US8901007B2 (en) * 2013-01-03 2014-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Addition of carboxyl groups plasma during etching for interconnect reliability enhancement
US10354860B2 (en) * 2015-01-29 2019-07-16 Versum Materials Us, Llc Method and precursors for manufacturing 3D devices
JP6523091B2 (ja) 2015-07-24 2019-05-29 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330911A (ja) * 1996-06-11 1997-12-22 Toshiba Corp 半導体装置の製造方法
JP2003264170A (ja) * 2002-01-07 2003-09-19 Tokyo Electron Ltd プラズマ処理方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6455232B1 (en) * 1998-04-14 2002-09-24 Applied Materials, Inc. Method of reducing stop layer loss in a photoresist stripping process using a fluorine scavenger
JP3803523B2 (ja) * 1999-12-28 2006-08-02 株式会社東芝 ドライエッチング方法及び半導体装置の製造方法
US6372636B1 (en) * 2000-06-05 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
US6352921B1 (en) * 2000-07-19 2002-03-05 Chartered Semiconductor Manufacturing Ltd. Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
US6479391B2 (en) * 2000-12-22 2002-11-12 Intel Corporation Method for making a dual damascene interconnect using a multilayer hard mask
US6647994B1 (en) * 2002-01-02 2003-11-18 Taiwan Semiconductor Manufacturing Company Method of resist stripping over low-k dielectric material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330911A (ja) * 1996-06-11 1997-12-22 Toshiba Corp 半導体装置の製造方法
JP2003264170A (ja) * 2002-01-07 2003-09-19 Tokyo Electron Ltd プラズマ処理方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4825911B2 (ja) * 2006-03-24 2011-11-30 アプライド マテリアルズ インコーポレイテッド 介在チャンバでの脱フッ素化及びウェハ脱フッ素化ステップによるプラズマエッチング及びフォトレジストストリッププロセス
JP2011100765A (ja) * 2009-11-04 2011-05-19 Fujitsu Semiconductor Ltd 半導体素子の製造方法

Also Published As

Publication number Publication date
US20050101135A1 (en) 2005-05-12
TW200524051A (en) 2005-07-16
CN1868039A (zh) 2006-11-22
KR20060123144A (ko) 2006-12-01
WO2005048335A1 (en) 2005-05-26
EP1683192A1 (en) 2006-07-26
IL174648A0 (en) 2006-08-20

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