JP2007506276A - 低誘電率を有する誘電体層を形成するための方法 - Google Patents

低誘電率を有する誘電体層を形成するための方法 Download PDF

Info

Publication number
JP2007506276A
JP2007506276A JP2006526795A JP2006526795A JP2007506276A JP 2007506276 A JP2007506276 A JP 2007506276A JP 2006526795 A JP2006526795 A JP 2006526795A JP 2006526795 A JP2006526795 A JP 2006526795A JP 2007506276 A JP2007506276 A JP 2007506276A
Authority
JP
Japan
Prior art keywords
layer
wafer
dielectric
wetting
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006526795A
Other languages
English (en)
Japanese (ja)
Inventor
ハーバンス、サクデブ
ガーケイ、ロング
ジョン、ラップ
マリー、マテラ‐ロンゴ
ナラ、サーマ
スティーブン、マイスナー
Original Assignee
コニンクリユケ フィリップス エレクトロニクス エヌ．ブイ．
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by コニンクリユケ フィリップス エレクトロニクス エヌ．ブイ． filed Critical コニンクリユケ フィリップス エレクトロニクス エヌ．ブイ．
Publication of JP2007506276A publication Critical patent/JP2007506276A/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Paints Or Removers (AREA)
JP2006526795A 2003-09-19 2004-09-18 低誘電率を有する誘電体層を形成するための方法 Withdrawn JP2007506276A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50445203P 2003-09-19 2003-09-19
PCT/IB2004/051793 WO2005029567A1 (en) 2003-09-19 2004-09-18 Method of forming dielectric layers with low dielectric constants

Publications (1)

Publication Number Publication Date
JP2007506276A true JP2007506276A (ja) 2007-03-15

Family

ID=34375500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006526795A Withdrawn JP2007506276A (ja) 2003-09-19 2004-09-18 低誘電率を有する誘電体層を形成するための方法

Country Status (5)

Country Link
EP (1) EP1668683A1 (zh)
JP (1) JP2007506276A (zh)
KR (1) KR20060096996A (zh)
CN (1) CN1883038A (zh)
WO (1) WO2005029567A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101220029B1 (ko) * 2008-04-02 2013-01-21 미쓰이 가가쿠 가부시키가이샤 조성물 및 그 제조 방법, 다공질 재료 및 그 형성 방법, 층간 절연막, 반도체 재료, 반도체 장치, 및 저굴절률 표면 보호막

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5429673A (en) * 1993-10-01 1995-07-04 Silicon Resources, Inc. Binary vapor adhesion promoters and methods of using the same
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
US6066578A (en) * 1997-12-01 2000-05-23 Advanced Micro Devices, Inc. Method and system for providing inorganic vapor surface treatment for photoresist adhesion promotion
US6218020B1 (en) * 1999-01-07 2001-04-17 Alliedsignal Inc. Dielectric films from organohydridosiloxane resins with high organic content
US6541367B1 (en) * 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
JP2002324745A (ja) * 2001-04-25 2002-11-08 Tokyo Ohka Kogyo Co Ltd レジスト膜形成方法
JP2003257836A (ja) * 2002-03-05 2003-09-12 Matsushita Electric Ind Co Ltd 有機膜形成方法

Also Published As

Publication number Publication date
CN1883038A (zh) 2006-12-20
EP1668683A1 (en) 2006-06-14
KR20060096996A (ko) 2006-09-13
WO2005029567A1 (en) 2005-03-31

Similar Documents

Publication Publication Date Title
USRE39690E1 (en) Enhanced planarization technique for an integrated circuit
US6348407B1 (en) Method to improve adhesion of organic dielectrics in dual damascene interconnects
EP1178528B1 (en) Wafer pretreatment to decrease the deposition rate of silicon dioxide on silicon nitride in comparison to its deposition rate on a silicon substrate
US7557420B2 (en) Low temperature process for polysilazane oxidation/densification
US4885262A (en) Chemical modification of spin-on glass for improved performance in IC fabrication
US5607773A (en) Method of forming a multilevel dielectric
JP3568537B2 (ja) マイクロエレクトロニクス構造体用電子ビーム加工膜
US7705431B1 (en) Method of improving adhesion between two dielectric films
JP2008117903A (ja) 半導体装置の製造方法
US7071539B2 (en) Chemical planarization performance for copper/low-k interconnect structures
US20090140418A1 (en) Method for integrating porous low-k dielectric layers
JP2004538637A (ja) Ｍｓｑ系多孔質低ｋ膜材料のプラズマ硬化
US7557035B1 (en) Method of forming semiconductor devices by microwave curing of low-k dielectric films
JP3015763B2 (ja) 半導体装置の製造方法
JP4489898B2 (ja) フッ素化ｂｐｓｇ膜の堆積及び平坦化の改良された方法
US5567660A (en) Spin-on-glass planarization by a new stagnant coating method
US6831015B1 (en) Fabrication method of semiconductor device and abrasive liquid used therein
US6472751B1 (en) H2 diffusion barrier formation by nitrogen incorporation in oxide layer
US20040175922A1 (en) Method for forming a low-k dielectric structure on a substrate
JP2007506276A (ja) 低誘電率を有する誘電体層を形成するための方法
US5872066A (en) Method of forming inter-metal dielectric layer for WVIA process
JP3127983B2 (ja) 半導体装置の製造方法
US5910680A (en) Germanium silicate spin on glass semiconductor device and methods of spin on glass synthesis and use
US6265298B1 (en) Method for forming inter-metal dielectrics
JPH104087A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070918

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080703

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20091007