JP2007318060A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiP-type semiconductor device capable of suppressing a noise applied between chips, even if a semiconductor substrate and semiconductor chip are integrated into a stack. <P>SOLUTION: The semiconductor device packaged to include a semiconductor has a structure in which a mesh-like conductive layer 16m is formed on the semiconductor substrate 10 having an active element formed thereon, and a semiconductor chip 19 having an active element formed thereon is mounted on its upper layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a SiP (system in package) type semiconductor device incorporating an active element and a passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

  The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting substrate (printed wiring substrate) be improved? Has been studied and developed as an important issue.

  For example, as a package form of a semiconductor device, a transition from a lead insertion type such as DIP (Dual Inline Package) to a surface mounting type is performed, and furthermore, bumps (projection electrodes) made of solder, gold, or the like are provided on a pad electrode of a semiconductor chip. A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

  Furthermore, development is progressing into a package of a complicated form called SiP that incorporates passive elements such as inductances and capacitors and incorporates a matching circuit and a filter.

  Among the semiconductor devices of the SiP type as described above, for example, a semiconductor device in which two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip are integrated is known. For example, Patent Document 1 discloses the configuration of the above-described SiP-type semiconductor device.

  Among the semiconductor devices of the SiP type as described above, a semiconductor device in which two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip are integrated is known. Yes.

  For example, in a semiconductor device in which an analog chip and a digital chip are stacked, there is an influence of digital noise particularly from the digital chip to the analog chip. Therefore, the distance between the digital chip and the analog chip needs to be sufficiently long.

In order to reduce the influence of the above-mentioned noise, as described in Patent Document 1, a structure that is laid flat on the same plane is often taken.
However, the structure in which two or more semiconductor chips as described above are laid flat increases the size of the entire semiconductor device, and does not satisfy the demand for miniaturization.

Patent Document 2 describes a semiconductor device in which an analog chip and a digital chip are stacked.
In the case of a stack structure in which two or more semiconductor chips are placed vertically, it is possible to provide a structure that shields noise. For example, a noise shielding sheet may be interposed, but the noise shielding sheet has a thickness. However, it is practically impossible to adopt a stack structure while realizing a reduction in thickness.

  For this reason, analog and digital chips are mounted on both sides of the organic substrate, respectively, but it is necessary to form external electrodes on the substrate through-hole and one side, which increases the overall thickness. Thinning has become difficult.

In the above, a semiconductor device having an analog chip and a digital chip has been particularly described. However, it is desired to reduce the influence of noise between chips even in a combination of a digital chip and a digital chip, or an analog chip and an analog chip. This is a problem when integrating into a stack type.
Japanese Patent Laid-Open No. 5-114693 JP 2003-124236 A

  The problem to be solved is that it is difficult to suppress noise acting between chips when two or more semiconductor chips are integrated into a stack type in a semiconductor device of SiP type.

  The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, wherein a semiconductor substrate on which an active element is formed, an electromagnetic wave shielding layer formed on the semiconductor substrate, and an active substrate are formed, A semiconductor chip mounted on an upper layer of the electromagnetic wave shielding layer.

  The semiconductor device of the present invention described above is a semiconductor device packaged including a semiconductor, wherein an electromagnetic wave shielding layer is formed on a semiconductor substrate on which an active element is formed, and an active element is formed on the upper layer. In this configuration, the manufactured semiconductor chip is mounted.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor, the step of forming an electromagnetic wave shielding layer on a semiconductor substrate on which an active element is formed, and the electromagnetic wave shielding. And mounting a semiconductor chip on which an active element is formed on the upper layer.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor. First, an electromagnetic wave shielding layer is formed on a semiconductor substrate on which an active element is formed. Then, a semiconductor chip having an active element formed on the electromagnetic wave shielding layer is mounted.

  In the semiconductor device of the present invention, an electromagnetic wave shielding layer such as a mesh-like conductive layer or an electromagnetic wave absorbing layer is formed between the semiconductor substrate and the semiconductor chip in the SiP-type semiconductor device, which becomes a noise shielding layer. Thereby, even if the semiconductor substrate and the semiconductor chip are integrated as a stack type, noise acting between the chips can be suppressed.

  In the semiconductor device manufacturing method of the present invention, in a SiP-type semiconductor device, an electromagnetic wave shielding layer such as a mesh-like conductive layer or an electromagnetic wave absorbing layer is formed between the semiconductor substrate and the semiconductor chip. To do. Thereby, even if the semiconductor substrate and the semiconductor chip are integrated as a stack type, noise acting between the chips can be suppressed.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a pad 11 connected to an electronic circuit is formed on a silicon substrate 10 on which an electronic circuit including an active element is formed, and a region excluding the pad 11 is covered with a protective layer 12 such as silicon oxide.
For example, the first resin layer 13 made of polyimide resin, epoxy resin, acrylic resin, or the like is formed on the protective layer 12.
In the first resin layer 13, an opening 13 a reaching the pad 11 of the silicon substrate 10 is formed.
For example, a first layer made of a seed layer 14 such as TiCu and a copper layer 16 is formed on the first resin layer 13 so as to be integrated with a plug portion connected to the pad 11 of the silicon substrate 10 and embedded in the opening 13a. One wiring is formed.
Further, for example, the conductive post 18 is formed on the first wiring.

Further, for example, a region between the conductive posts 18 becomes a chip mounting region, and a mesh-shaped conductive layer 16 m is formed on the first resin layer 13. The mesh-like conductive layer 16m is fixed to a constant potential such as ground, for example, and becomes an electromagnetic wave shielding layer.
FIG. 1B is a plan view showing the layout of the mesh-like conductive layer. The mesh-shaped conductive layer 16m has a configuration in which, for example, square-shaped conductive layers are arranged in a mesh shape.
The mesh-like conductive layer 16m is formed by processing a copper layer of the same layer as the copper layer constituting the first wiring into a mesh shape.

A semiconductor chip 19 on which an active element is formed is mounted on the mesh conductive layer 16m.
The semiconductor chip 19 has a configuration in which a pad 19b is formed on a circuit surface on which an active element of the semiconductor body portion 19a is formed, and a region excluding the pad 19b is covered with a protective layer 19c such as silicon oxide. That is, the pad 19b is mounted by the die attach film 19d so that the formation surface thereof faces the upper surface.

Further, for example, the second resin layer 20 made of the same polyimide resin as the first resin layer 13 is formed so as to cover the conductive posts 18 and the semiconductor chip 19.
In the second resin layer 20, an opening 20 a reaching the upper surface of the conductive post 18 and the pad 19 b of the semiconductor chip 19 is formed.
A seed layer 21 such as TiCu and copper is embedded on the second resin layer 20 so as to be embedded in the opening 20a and integrated with a plug portion connected to the upper surface of the conductive post 18 and the pad 19b of the semiconductor chip 19. A second wiring made of the layer 23 is formed.

Further, for example, a conductive post 25 made of copper or the like is formed in connection with the second wiring.
An insulating buffer layer 26 made of polyamideimide resin, polyimide resin, epoxy resin, phenol resin, polyparaphenylene benzobisoxazole resin, or the like is formed on the second resin layer 20 in the gap between the conductive posts 25. .
Further, bumps (projection electrodes) 27 are formed on the surface of the buffer layer 26 so as to be connected to the conductive posts 25.

  In the above semiconductor device, an insulating layer is formed by laminating a plurality of resin layers (first resin layer 13 and second resin layer 20) on the silicon substrate 10, and the first wiring and A wiring layer such as a second wiring is formed, and the semiconductor chip 19 is connected to the wiring layer and embedded in the insulating layer.

In the semiconductor device of the present embodiment, the silicon substrate 10 is a digital chip, for example, while the semiconductor chip 19 is an analog chip, for example.
For example, the mesh-like conductive layer formed between the silicon substrate 10 and the semiconductor chip 19 is fixed to a constant potential such as ground and becomes an electromagnetic wave shielding layer, whereby the silicon substrate 10 and the semiconductor chip 19 are integrated as a stack type. Although it is configured, noise acting between the two chips can be suppressed.

In the above configuration, for example, the mesh-like conductive layer 16m is formed in a mesh shape by arranging a large number of openings. For example, square-shaped members having the same size as the openings are arranged alternately with the openings. It is the composition which was made. The square-shaped conductive layers are connected at the corners.
The size of the opening is set so as to maximize the shielding effect according to the frequency of the noise to be shielded, for example, 30 μm □ to 150 μm □.

  Even if the silicon substrate 10 and the semiconductor chip 19 are a combination opposite to the above, or both are digital chips or analog chips, noise between the chips can be suppressed in the same manner as described above.

For example, the mesh-like conductive layer 16m may be a layer that is thermally connected to the silicon substrate 10 and / or the semiconductor chip 19 to promote heat dissipation.
For example, the mesh-like conductive layer 16m is connected to the ground potential of the semiconductor chip 19, and when higher heat dissipation or shielding is required, the mesh-like conductive layer 16m is connected to the ground potential of the silicon substrate 10. .

  In the semiconductor device according to the present embodiment, the mesh-like conductive layer 16m has a single-layer structure, but may be a stacked body of a plurality of conductive layers.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 2 to 9 can be performed at the wafer level.
First, as shown in FIG. 2A, for example, an electronic circuit including an active element (not shown) is formed on a silicon substrate 10 having a thickness of 725 μm, and a pad 11 connected to the electronic circuit is formed on the circuit surface. Then, a protective layer 12 such as silicon oxide is formed in a region excluding the pad 11.

Next, as shown in FIG. 2B, a photosensitive insulating material such as polyimide resin, phenol resin, or epoxy resin is supplied to the upper layer of the protective layer 12 by, for example, spin coating or printing. Then, the first resin layer 13 is formed. The first resin layer 13 has a thickness of about 4 to 10 μm after curing.
When the photosensitive polyimide resin is formed by spin coating, for example, the film is formed under the following conditions.
Spin coating: 1000 rpm (30 seconds) + 1950 rpm (40 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 90 ° C (120 seconds) + 100 ° C (120 seconds)

Next, as shown in FIG. 2C, for example, pattern exposure and development are performed with an exposure amount of 125 mJ / cm ² , and an opening 13 a reaching the pad 11 of the silicon substrate 10 is formed in the first resin layer 13. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the first insulating layer 13.

  Next, as shown in FIG. 2D, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 13a of the first resin layer 13 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 14 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

Next, as shown in FIG. 3A, for example, in order to prevent plating on areas other than the opening 13a formed in the first resin layer 13 and the formation area of the first wiring, resist coating and development processing are performed. Then, a resist film 15 having a pattern opening the opening 13a of the first resin layer 13 and the formation region of the first wiring is formed.
Here, in the semiconductor chip mounting region, the resist film 15 is patterned so as to open in a mesh shape. For example, the mesh opening has a size of 30 μm □ to 150 μm □, and the size is determined from the frequency of noise generated from the element. If the entire surface is covered, degassing and adhesion from the insulating layer deteriorate, but this can be prevented by forming a mesh.

Next, as shown in FIG. 3B, for example, an opening formed in the first resin layer 13 by plating copper by electrolytic plating using the resist film 15 as a mask and the seed layer 14 as one electrode. A copper layer 16 is formed in the formation region of 13a and the first wiring.
Further, a mesh-like conductive layer 16m is formed in the mounting region of the semiconductor chip by the electrolytic plating of copper.

  Next, as shown in FIG. 3C, the resist film 15 is removed by, for example, an ashing process, and as shown in FIG. 4A, a resist film 17 is formed by, for example, spin coating. Exposure and development are performed by a lithography process to form an opening reaching the surface of the copper layer 16 in the conductive post formation region.

  Next, as shown in FIG. 4B, for example, a conductive post 18 is formed in the upper layer of the copper layer 16 in the opening region of the resist film 17 by electrolytic plating using the seed layer 14 as one electrode. . The height of the conductive post is preferably about the same as or higher than the height of the surface when the semiconductor chip is mounted in the next step, for example, 120 μm.

Next, as shown in FIG. 4C, the resist film 17 is removed by, for example, an ashing process, and as shown in FIG. 5A, for example, the seeds are formed using the conductive posts 18 and the copper layer 16 as a mask. Layer 14 is etched.
Thus, the first wiring composed of the seed layer 14 and the copper layer 16 is formed on the first resin layer 13 integrally with the plug portion connected to the pad 11 of the silicon substrate 10.
Similarly, in the semiconductor chip mounting region, the seed layer 14 is removed by etching using the mesh-like conductive layer 16m as a mask.

  Next, as shown in FIG. 5B, for example, the pad 19b is formed on the circuit surface on which the active element of the semiconductor body portion 19a is formed in a separate process in advance, and the region excluding the pad 19b is oxidized. A semiconductor chip 19 covered with a protective layer 19c such as silicon is face-up by a die attach film 19d on a mesh-like conductive layer 16m, which is a semiconductor chip mounting area, that is, a surface on which a pad 19b is formed. Mount with face up. At this time, for example, the pads of the semiconductor chip are simultaneously recognized as the upper surface alignment marks of the conductive posts 18 and mounting is performed with high accuracy.

In the manufacturing method of the semiconductor chip 19, for example, the thickness is reduced to 25 to 50 μm by a grinding method or the like, the die attach film 19 d as an adhesive is laminated on the back surface, and the individual pieces are thinned by full-cut dicing.
The mounting conditions are a temperature of 160 ° C., a load of 1.6 N, and a time of 2 seconds when the chip size is 1.5 mm □. The mounting load is adjusted according to the chip size.
After mounting, a curing process is performed at 170 ° C. for 1 hour or more for curing the die attach film 19d.

Next, as shown in FIG. 5C, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, PBO resin or the like is supplied by, for example, spin coating or printing, and the conductive post 18 is formed. A second resin layer 20 is formed covering the upper surface and the semiconductor chip 19. For example, it is formed to have a film thickness of 50 μm after curing.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 700 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)

Next, for example, pattern exposure and development are performed at an exposure amount of 125 mJ / cm ² , and an opening 20 a reaching the upper surface of the conductive post 18 and the pad 19 b of the semiconductor chip 19 is formed in the second resin layer 20. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the second resin layer 20.

  Next, as shown in FIG. 6A, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 20a of the second resin layer 20 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 21 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

  Next, as shown in FIG. 6B, for example, in order to prevent plating other than the opening 20a formed in the second resin layer 20 and the formation area of the second wiring, resist coating and development processing are performed. Then, a resist film 22 having a pattern opening the opening 20a of the second resin layer 20 and the formation region of the second wiring is formed.

  Next, as shown in FIG. 6C, for example, an opening formed in the second resin layer 20 by plating copper by electrolytic plating using the resist film 22 as a mask and the seed layer 21 as one electrode. A copper layer 23 is formed in the formation region of 20a and the second wiring.

  Next, as shown in FIG. 7A, for example, the resist film 22 is removed by ashing or the like, and as shown in FIG. 7B, for example, a resist film 24 is formed, and pattern exposure and development are performed. Thus, an opening for the conductive post is formed.

  Next, as shown in FIG. 7C, the conductive posts 25 are formed in the openings for the conductive posts by, for example, electrolytic plating of copper using the seed layer 21 as one electrode. The conductive post 25 has a diameter of 180 to 300 μm and a height of 80 to 180 μm, for example.

  Next, as shown in FIG. 8A, for example, the resist film 24 is removed, and as shown in FIG. 8B, the seed layer 21 is etched using the conductive posts 25 and the copper layer 23 as a mask. . Thereby, the second wiring composed of the seed layer 21 and the copper layer 23 is formed, and the conductive post 25 is formed on the second wiring.

  Next, as shown in FIG. 8C, for example, an epoxy resin, a polyimide resin, a silicone resin, a polyamideimide resin, a polyimide resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is spun. A film is formed by coating, printing, molding, or the like, and an insulating buffer layer 26 is formed with a film thickness that completely covers the conductive post 25.

  Next, as shown in FIG. 9A, for example, after the resin hardening of the buffer layer 26, the cue of the conductive post 25 is performed by grinding. The conditions at this time are set to 3500 rpm and 0.5 mm / second using, for example, a # 600 wheel.

  Next, as shown in FIG. 9B, bumps (projection electrodes) 27 are formed so as to be connected to the conductive posts 25 by, for example, mounting solder balls or printing solder paste.

Next, as shown in FIG. 9C, for example, the silicon substrate 10 is thinned to a desired thickness from the back surface side of the silicon substrate 10 by BGR, and the silicon substrate 10 is diced by the blade B to be thin pieces.
Thus, the semiconductor device having the structure shown in FIG. 1 can be manufactured.

  According to the manufacturing method of the semiconductor device according to the above-described embodiment, in the SiP-type semiconductor device, the mesh-like conductive layer is formed between the semiconductor substrate and the semiconductor chip, and is fixed to a constant potential, for example. By using it, it becomes a noise shielding layer. Thereby, even if the semiconductor substrate and the semiconductor chip are integrated as a stack type, noise acting between the chips can be suppressed.

For example, the mesh-like conductive layer 16m may be formed as a layer that is thermally connected to the silicon substrate 10 and / or the semiconductor chip 19 to promote heat dissipation.
Further, the mesh conductive layer 16m may be formed as a laminate of a plurality of conductive layers.

As the semiconductor chip incorporated in the semiconductor device according to the above-described embodiment, a stack type thin structure that does not interfere with each other in the combination of digital, digital chip, analog, combination of analog chip, and combination of digital and analog chip is possible. .
Further, the chip size of the first layer and the second layer is not restricted by the size relationship because of the rewiring structure. Further, in the above embodiment, since any chip is not connected by wire bonding, it is not necessary to increase the thickness of the insulating film by the height of the wire loop, and a thin stack structure is realized. .
A low thermal resistance type SiP can be configured by arranging a semiconductor chip that requires high heat dissipation in the first layer and utilizing the high heat dissipation of the silicon substrate.
In addition, since the conductive post is formed in the same layer as the semiconductor chip, the step generated in the insulating layer is reduced, the step breakage can be suppressed, and the mounting substrate when mounted on the mounting substrate can be suppressed. It is possible to secure the stress relaxation function by reducing the variation in the height of the conductive posts that contribute to the stress relaxation generated therebetween.

  The semiconductor device according to the present embodiment has a configuration in which two semiconductor chips are stacked, but since one is a substrate itself, there is one semiconductor chip embedded in the resin insulating layer, and as an embedded chip Only one chip to be embedded needs to be thinned as necessary.

Second Embodiment FIG. 10 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
Although the configuration is substantially the same as that of the semiconductor device according to the first embodiment, an insulating layer formed by laminating a resin layer on the silicon substrate 10 includes the semiconductor chip 19 in the layer where the semiconductor chip 19 is mounted. It includes a frame-shaped resin layer 28 formed on the outer periphery at a predetermined distance from the semiconductor chip 19, and the semiconductor chip 19 is different from that of the frame-shaped resin layer 28 in mounting.
The second resin layer 20 is formed by covering the semiconductor chip 19 and the frame-shaped resin layer 28 and filling the gaps.
Other than the above, the semiconductor device is the same as that of the first embodiment.

  For example, the frame-shaped resin layer 28 is formed at a distance of about 30 μm from the outer periphery of the semiconductor chip 19. This is to prevent the resin from flowing into the corner and forming voids when the second resin layer 20 is formed.

  As in the first embodiment, the semiconductor device of the present embodiment is used, for example, with the mesh-like conductive layer formed between the silicon substrate 10 and the semiconductor chip 19 being fixed to a constant potential such as ground. Thus, although the silicon substrate 10 and the semiconductor chip 19 are integrated as a stack type, noise acting between the two chips can be suppressed.

A method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.
First, as shown in FIG. 11A, the conductive post 18 is formed, and the process of etching the seed layer 14 using the conductive post 18 and the copper layer 16 as a mask is performed in the same manner as in the first embodiment. At this time, the seed layer 14 is removed by etching using the mesh-like conductive layer 16m as a mask in the semiconductor chip mounting region.

Next, as shown in FIG. 11B, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, PBO resin or the like is supplied by, for example, spin coating or printing, and the conductive post 18 is formed. A resin layer 28a for a frame-shaped resin layer is formed covering the upper surface and the semiconductor chip 19. For example, it is formed to have a film thickness of 50 μm after curing.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 700 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)

Next, as shown in FIG. 11C, for example, pattern exposure and development are performed at an exposure amount of 125 mJ / cm ² , and a predetermined area from the area where the semiconductor chip 19 is mounted on the outer periphery of the area where the semiconductor chip 19 is mounted The frame-shaped resin layer 28 is arranged at a distance. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the frame-shaped resin layer 28.

  Next, as shown in FIG. 12A, for example, a pad 19b is formed on the circuit surface on which the active element of the semiconductor body portion 19a is formed in a separate process in advance, and the region excluding the pad 19b is oxidized. A semiconductor chip 19 covered with a protective layer 19c such as silicon is face-up by a die attach film 19d on a mesh-like conductive layer 16m, which is a semiconductor chip mounting area, that is, a surface on which a pad 19b is formed. Mount with face up. In the present embodiment, the frame-shaped resin layer 28 is formed in advance, so that it is fitted and mounted.

  Next, as shown in FIG. 12B, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, PBO resin or the like is supplied by, for example, a spin coating method or a printing method, and the frame-shaped resin layer 28 is supplied. The second resin layer 20 is formed by covering the semiconductor chip 19 and filling the gap between the frame-shaped resin layer 28 and the semiconductor chip 19.

Next, as shown in FIG. 12C, for example, pattern exposure and development are performed at an exposure amount of 125 mJ / cm ² , and the opening 20a reaching the upper surface of the conductive post 18 and the pad 19b of the semiconductor chip 19 is formed in the second resin. Layer 20 is formed. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the second resin layer 20.
Subsequent steps can be performed in substantially the same manner as in the first embodiment.

  According to the manufacturing method of the semiconductor device according to the above-described embodiment, in the SiP-type semiconductor device, the mesh-like conductive layer is formed between the semiconductor substrate and the semiconductor chip, and is fixed to a constant potential, for example. By using it, it becomes a noise shielding layer. Thereby, even if the semiconductor substrate and the semiconductor chip are integrated as a stack type, noise acting between the chips can be suppressed.

  Furthermore, since the frame-shaped resin layer 28 is formed in the layer in which the semiconductor chip is embedded, the step caused by embedding the semiconductor chip can be further relaxed and the disconnection can be suppressed, and it can be mounted on the mounting substrate. The stress variation function can be ensured by reducing the variation in the height of the conductive posts contributing to the relaxation of the stress generated between the mounting substrate and the mounting substrate.

Third Embodiment FIG. 13 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a pad 31 connected to an electronic circuit is formed on a silicon substrate 30 on which an electronic circuit including an active element is formed, and a region excluding the pad 31 is covered with a protective layer 32 such as silicon oxide.
Further, for example, a seed layer 33 such as TiCu and a conductive post 35 made of copper are formed on the pad 31.
Further, for example, a frame-shaped resin layer 36 that covers the conductive post 35 and is formed at a predetermined distance from the region where the semiconductor chip 38 is mounted is formed on the outer periphery of the region where the semiconductor chip 38 is mounted. ing.
The frame-shaped resin layer 36 has an opening 36 a that exposes the upper surface of the conductive post 35.

Further, for example, the gap region of the frame-shaped resin layer 36 formed by covering the conductive posts 35 becomes a chip mounting region, and an electromagnetic wave absorbing layer 37 that is an electromagnetic wave shielding layer is formed on the upper layer of the protective layer 32. A semiconductor chip 38 on which an active element is formed is mounted on the upper layer.
The semiconductor chip 38 has a configuration in which a pad 38b is formed on a circuit surface on which an active element of the semiconductor body portion 38a is formed, and a region excluding the pad 38b is covered with a protective layer 38c such as silicon oxide. That is, it is mounted by the die attach film 38d so that the formation surface of the pad 38b faces the upper surface.

In addition, for example, the first resin layer 39 made of polyimide resin or the like is formed by covering the frame-shaped resin layer 36 and the semiconductor chip 38 and filling the gaps.
Here, for example, the frame-shaped resin layer 36 is formed away from the outer periphery of the semiconductor chip 38 by about 30 μm. This is to prevent the resin from flowing into the corners and forming voids when the first resin layer 39 is formed.

For example, the first resin layer 39 is formed with an opening 39 a that communicates with the opening 36 a of the frame-shaped resin layer 36 and reaches the upper surface of the conductive post 35 and reaches the pad 38 b of the semiconductor chip 38. ing.
A seed layer 40 such as TiCu and copper is embedded on the first resin layer 39 by being embedded in the opening 39a and integrated with the upper surface of the conductive post 35 and the plug portion connected to the pad 38b of the semiconductor chip 38. A first wiring made of the layer 42 is formed.

Further, for example, a second resin layer 43 made of the same polyimide resin as the first resin layer 39 is formed so as to cover the first wiring and the first resin layer 39, and the second resin layer 43 includes An opening 43a reaching the copper layer 42 of the first wiring is formed.
Further, for example, a bump (projection electrode) 44 is formed so as to be embedded in the opening 43 a of the second resin layer 43 and project from the surface of the second resin layer 43.

  In the semiconductor device described above, an insulating layer is formed by laminating a plurality of resin layers (first resin layer 39 and second resin layer 43) on the silicon substrate 30, and the first wiring and the like are formed in the insulating layer. The wiring layer is formed, and the semiconductor chip 38 is connected to the wiring layer and embedded in the insulating layer.

In the semiconductor device according to the present embodiment, the silicon substrate 30 is, for example, a digital chip, while the semiconductor chip 38 is, for example, an analog chip.
For example, the electromagnetic wave absorbing layer 37 formed between the silicon substrate 30 and the semiconductor chip 38 is a film formed by applying an electromagnetic wave absorbing paste, and can block noise between the two chips.

  Even if the silicon substrate 30 and the semiconductor chip 38 are a combination opposite to the above, or both are digital chips or analog chips, noise between chips can be suppressed in the same manner as described above.

  In the semiconductor device of the present embodiment, the buffer layer and the conductive post penetrating the buffer layer are not provided. For example, in the case of a semiconductor chip having a size of 4.5 mm □ or less, the semiconductor device is mounted on a mounting substrate or the like. Since the stress applied to the substrate is not so large, connection reliability during mounting can be ensured without providing a buffer layer.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 14 to 20 can be performed at the wafer level.
First, as shown in FIG. 14A, for example, an electronic circuit including an active element (not shown) is formed on a silicon substrate 30 having a thickness of 725 μm, and a pad 31 connected to the electronic circuit is formed on the circuit surface. Then, a protective layer 32 such as silicon oxide is formed so as to cover the region excluding the pad 31.

  Next, as shown in FIG. 14B, for example, the protective layer 32 is coated by sputtering, and a TiCu film is formed on the entire surface to form the seed layer 33. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

  Next, as shown in FIG. 14C, for example, a resist film 34 is formed by spin coating or the like, and exposure and development are performed by a photolithography process, so that the surface of the seed layer 33 is formed in the conductive post formation region. An opening reaching the top is formed.

  Next, as shown in FIG. 14D, the conductive post 35 is formed in the upper layer of the seed layer 33 in the opening region of the resist film 34 by, for example, electrolytic plating using the seed layer 33 as one electrode. . The height of the conductive post is preferably about the same as or higher than the height of the surface when the semiconductor chip is mounted in the next step, for example, 25 to 50 μm.

  Next, as shown in FIG. 15A, for example, the resist film 34 is removed by ashing or the like, and as shown in FIG. 15B, for example, the seed layer 33 is etched using the conductive posts 35 as a mask. Process.

Next, as shown in FIG. 15C, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, or PBO resin is supplied by, for example, a spin coating method or a printing method, and the conductive post 35 is formed. A frame-shaped resin layer resin layer 36b is formed by coating. For example, it forms so that it may become a film thickness of 25-50 micrometers after hardening.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 1000 rpm (30 seconds) + 1950 rpm (40 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)

Next, as shown in the perspective view of FIG. 16A and the cross-sectional view of FIG. 16B, for example, pattern exposure and development with an exposure amount of 125 mJ / cm ² , and the outer periphery of the region where the semiconductor chip 38 is mounted The frame-shaped resin layer 36 is arranged at a predetermined distance from the region where the semiconductor chip 38 is mounted. At this time, the opening 36a is formed so that the upper surface of the conductive post 35 is exposed, and the resin of the scribe line is also removed.
After development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the frame-shaped resin layer 36.

  Next, as shown in FIG. 17A, for example, an electromagnetic wave absorbing paste is applied by using a dispenser or the like to form an electromagnetic wave absorbing layer 37, and a semiconductor layer previously formed in a separate process thereon is formed. A pad 38b is formed on the circuit surface on which the active element of the main body portion 38a is formed, and a region excluding the pad 38b is a semiconductor chip 38 covered with a protective layer 38c such as silicon oxide, which is a semiconductor chip mounting region. A die attach film 38d is mounted on the electromagnetic wave absorbing layer 37 face up, that is, with the formation surface of the pad 38b as the upper surface. In the present embodiment, the frame-shaped resin layer 36 is formed in advance. At this time, for example, the upper surface of the conductive post 35 is used as an alignment mark to simultaneously recognize the pad 38b of the semiconductor chip 38 and mount with high accuracy.

At the time of manufacture, the semiconductor chip 38 is thinned to 25 to 50 μm, for example, by a grinding method, etc., and a die attach film 38d as an adhesive is laminated on the back surface, and the individual chips are thinned by full-cut dicing.
The mounting conditions are a temperature of 160 ° C., a load of 3.2 N, and a time of 2 seconds when the chip size is 1.5 mm □. The mounting load is adjusted according to the chip size.
After mounting, a curing process is performed at 170 ° C. for 1 hour or more for curing the die attach film 38d. At this time, the electromagnetic wave absorbing layer 37 is also cured.

  Next, as shown in FIG. 17B, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, or PBO resin is supplied by, for example, spin coating or printing, and the frame-shaped resin layer 36 is supplied. The first resin layer 39 is formed by covering the semiconductor chip 38 and filling the gap between the frame-shaped resin layer 36 and the semiconductor chip 38.

Next, as shown in FIG. 17C, for example, pattern exposure and development are performed at an exposure amount of 125 mJ / cm ² , and the opening 39a reaching the upper surface of the conductive post 35 and the pad 38b of the semiconductor chip 38 is formed in the first resin. Layer 39 is formed. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the first resin layer 39.

  Next, as shown in FIG. 18A, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 39a of the first resin layer 39 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 40 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

  Next, as shown in FIG. 18B, for example, in order to prevent plating in areas other than the opening 39a formed in the first resin layer 39 and the formation area of the first wiring, resist coating and development processing are performed. Then, a resist film 41 having a pattern that opens the opening 39a formed in the first resin layer 39 and the formation region of the first wiring is formed.

  Next, as shown in FIG. 18C, for example, an opening formed in the first resin layer 39 by plating copper by electrolytic plating using the resist film 41 as a mask and the seed layer 40 as one electrode. A copper layer 42 is formed in the formation region 39a and the first wiring.

Next, as shown in FIG. 19A, for example, the resist film 41 is removed by ashing or the like, and as shown in FIG. 19B, for example, the seed layer 40 is etched using the copper layer 42 as a mask. To do.
Thus, the first wiring composed of the seed layer 40 and the copper layer 42 is formed on the first resin layer 39 integrally with the plug portion connected to the conductive post 35 and the pad 38b of the semiconductor chip 38.

Next, as shown in FIG. 19C, a photosensitive insulating material such as a BCB resin, a polyimide resin, an epoxy resin, or a PBO resin is supplied by, for example, spin coating or printing, and the first wiring and the first wiring The second resin layer 43 is formed by covering the first resin layer 39. For example, it is formed to have a film thickness of 50 μm after curing.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 700 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)

Next, for example, pattern exposure and development are performed at an exposure amount of 125 mJ / cm ² , and an opening 43 a reaching the first wiring is formed in the second resin layer 43. At this time, the resin of the scribe line is also removed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the second resin layer 43.

  Next, as shown in FIG. 20 (a), for example, by mounting a solder ball or printing a solder paste so as to be connected to the first wiring in the opening 43a of the second resin layer 43, bumps are formed. A (projection electrode) 44 is formed.

Next, as shown in FIG. 20B, for example, the silicon substrate 30 is thinned from the back surface side of the silicon substrate 30 to a desired thickness by BGR, and the silicon substrate 30 is diced by the blade B to be thinly divided into individual pieces.
Thus, the semiconductor device having the structure shown in FIG. 13 can be manufactured.

  According to the manufacturing method of the semiconductor device according to the present embodiment, in the SiP type semiconductor device, the electromagnetic wave absorbing layer which is an electromagnetic wave shielding layer is formed between the semiconductor substrate and the semiconductor chip, and the noise shielding layer and To do. Thereby, even if the semiconductor substrate and the semiconductor chip are integrated as a stack type, noise acting between the chips can be suppressed.

As the semiconductor chip incorporated in the semiconductor device according to the above-described embodiment, a stack type thin structure that does not interfere with each other in the combination of digital, digital chip, analog, combination of analog chip, and combination of digital and analog chip is possible. .
In addition, since the conductive post is formed in the same layer as the semiconductor chip, the step generated in the insulating layer is reduced, the step breakage can be suppressed, and the mounting substrate when mounted on the mounting substrate can be suppressed. It is possible to secure the stress relaxation function by reducing the variation in the height of the conductive posts that contribute to the stress relaxation generated therebetween.

  In addition, since the frame-shaped resin layer 36 is formed in the layer in which the semiconductor chip is embedded, the step caused by embedding the semiconductor chip can be further relaxed, and the step disconnection can be suppressed. The stress variation function can be ensured by reducing the variation in the height of the conductive posts contributing to the relaxation of the stress generated between the mounting substrate and the mounting substrate.

  The semiconductor device according to the present embodiment has a configuration in which two semiconductor chips are stacked, but since one is a substrate itself, there is one semiconductor chip embedded in the resin insulating layer, and as an embedded chip Only one chip to be embedded needs to be thinned as necessary.

The present invention is not limited to the above description.
For example, passive elements such as inductances and capacitors may be formed on the first and second wirings.
In the embodiment, two layers of wiring (first wiring and second wiring) are formed as the wiring in the insulating layer, but the present invention is not limited to this. The number of resin insulation layers is not limited to the number of layers as described above.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

  The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a plan view showing a layout of a mesh-like conductive layer. 2A to 2D are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 3A to 3C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 4A to 4C are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 5A to 5C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 6A to 6C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 7A to 7C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 8A to 8C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 9A to 9C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. 11A to 11C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 12A to 12C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. 14A to 14D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. 15A to 15C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 16A is a perspective view showing a manufacturing process of a semiconductor device manufacturing method according to the third embodiment of the present invention, and FIG. 16B is a cross-sectional view. 17A to 17C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. 18A to 18C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. 19A to 19C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. 20A and 20B are cross-sectional views illustrating the manufacturing steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Pad, 12 ... Protective layer, 13 ... 1st resin layer, 13a ... Opening part, 14 ... Seed layer, 15 ... Resist film, 16 ... Copper layer, 16m ... Mesh-like conductive layer, 17 ... Resist film, 18 ... conductive post, 19 ... semiconductor chip, 19a ... semiconductor body part, 19b ... pad, 19c ... protective layer, 19d ... die attach film, 20 ... second resin layer, 20a ... opening, 21 ... seed Layer, 22 ... resist film, 23 ... copper layer, 24 ... resist film, 25 ... conductive post, 26 ... buffer layer, 27 ... bump, 28 ... frame-shaped resin layer, 28a ... frame-shaped resin layer resin layer, 30 DESCRIPTION OF SYMBOLS ... Silicon substrate, 31 ... Pad, 32 ... Protective layer, 33 ... Seed layer, 34 ... Resist film, 35 ... Conductive post, 36 ... Frame-shaped resin layer, 36a ... Opening, 36b ... Resin layer for frame-shaped resin layer , 37 ... Electric Wave absorbing layer, 38 ... semiconductor chip, 38a ... semiconductor body portion, 38b ... pad, 38c ... protective layer, 38d ... die attach film, 39 ... first resin layer, 39a ... opening, 40 ... seed layer, 41 ... resist Membrane, 42 ... Copper layer, 43 ... Second resin layer, 43a ... Opening, 44 ... Bump

Claims (20)

A semiconductor device packaged including a semiconductor,
A semiconductor substrate on which active elements are formed;
An electromagnetic wave shielding layer formed on the semiconductor substrate;
A semiconductor device comprising: a semiconductor chip on which an active element is formed and mounted on an upper layer of the electromagnetic wave shielding layer. The semiconductor device according to claim 1, wherein the electromagnetic wave shielding layer is a mesh-like conductive layer. An insulating layer formed by laminating a plurality of resin layers on the semiconductor substrate;
A wiring layer formed in the insulating layer;
The semiconductor device according to claim 1, wherein the semiconductor chip is connected to the wiring layer and embedded in the insulating layer. The semiconductor device according to claim 2, wherein the mesh conductive layer is used while being fixed at a constant potential. The semiconductor device according to claim 2, wherein the mesh-shaped conductive layer is formed by arranging a large number of openings having a size corresponding to a frequency of noise generated between the semiconductor substrate and the semiconductor chip. The semiconductor device according to claim 2, wherein the size of the opening of the mesh conductive layer is 30 μm □ to 150 μm □. The insulating layer includes a frame-shaped resin layer formed at a predetermined distance from the semiconductor chip at an outer periphery of the semiconductor chip in a layer on which the semiconductor chip is mounted;
The semiconductor device according to claim 3, wherein the semiconductor chip is mounted by being fitted into the frame-shaped resin layer. The semiconductor device according to claim 2, wherein the mesh conductive layer is a layer that is thermally connected to the semiconductor substrate and / or the semiconductor chip to promote heat dissipation. The semiconductor device according to claim 2, wherein the mesh-shaped conductive layer is a stacked body of a plurality of conductive layers. The semiconductor device according to claim 1, wherein the electromagnetic wave shielding layer is an electromagnetic wave absorbing layer. A method of manufacturing a semiconductor device packaged including a semiconductor,
Forming an electromagnetic wave shielding layer on the semiconductor substrate on which the active element is formed;
Mounting a semiconductor chip on which an active element is formed on an upper layer of the electromagnetic wave shielding layer. In the step of forming the electromagnetic wave shielding layer, a mesh-like conductive layer is formed,
The method for manufacturing a semiconductor device according to claim 11, wherein in the step of mounting the semiconductor chip, the semiconductor chip is mounted on an upper layer of the mesh-like conductive layer. A step of laminating a plurality of resin layers on the semiconductor substrate to form an insulating layer;
Forming a wiring layer in the insulating layer, and
The method for manufacturing a semiconductor device according to claim 11, wherein in the step of mounting the semiconductor chip, the semiconductor chip is formed so as to be connected to the wiring layer and embedded in the insulating layer. The step of forming the mesh conductive layer and the step of mounting the semiconductor chip include forming the mesh conductive layer and mounting the semiconductor chip in a semiconductor device formation region of the semiconductor substrate in a wafer state. Item 12. A method for manufacturing a semiconductor device according to Item 11. The step of forming the mesh-shaped conductive layer is formed on the semiconductor substrate as a mesh formed by arranging a large number of openings having a size corresponding to the frequency of noise generated between the semiconductor substrate and the semiconductor chip. 11. A method for manufacturing a semiconductor device according to 11. The method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the mesh-shaped conductive layer, the size of the opening of the mesh-shaped conductive layer is formed to be 30 μm □ to 150 μm □. The step of forming the insulating layer further includes the step of forming a frame-shaped resin layer at a predetermined distance from the semiconductor chip at the outer periphery of the semiconductor chip in the layer on which the semiconductor chip is mounted,
The method for manufacturing a semiconductor device according to claim 12, wherein in the step of mounting the semiconductor chip, the semiconductor chip is mounted by being inserted into the frame-shaped resin layer. The semiconductor device according to claim 11, wherein in the step of forming the mesh conductive layer, the mesh conductive layer is formed as a layer that is thermally connected to the semiconductor substrate and / or the semiconductor chip to promote heat dissipation. Manufacturing method. The method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the mesh-shaped conductive layer, a plurality of conductive layers are stacked as the mesh-shaped conductive layer. In the step of forming the electromagnetic wave shielding layer, an electromagnetic wave absorbing layer is formed,
The method for manufacturing a semiconductor device according to claim 11, wherein in the step of mounting the semiconductor chip, the semiconductor chip is mounted on an upper layer of the electromagnetic wave absorption layer.

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