JP2005217222A - Integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when an analog element and a digital element are integrated in a chip-on-chip structure, the quality of an analog signal is deteriorated due to the influence of a noise from a digital signal processing circuit. <P>SOLUTION: This integrated circuit device is configured by laminating an analog element 1 having an analog signal processing circuit and a digital element 2 having a digital signal processing circuit in a status that their mutual circuit formation faces are faced to each other. An element circuit 12 including the digital signal processing circuit is formed on the main surface of the digital element 2, and a shield layer 15 constituted of soft magnetic materials is formed in a statue that the element circuit part 12 is covered. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an integrated circuit device configured using analog elements and digital elements.

  In recent years, as information terminals have become more personally owned, it has been required to reduce the size of communication equipment, in particular, the size of integrated circuit devices that actually handle signals. Therefore, in the past, attempts have been made to integrate various functions that have been realized by integration on a mother board as SoC (System on Chip). SoC is a technology for highly integrating a plurality of functions on one chip.

  However, in adopting SoC, along with the advancement of the system, the long-term development and the development risk for integrating various system functions into one chip are regarded as problems. Therefore, recently, SIP (System in Package) technology has been reviewed in terms of low cost, flexibility in use, and quick delivery. If SIP is classified from the structural aspect, it can be divided into chip level type (chip-on-chip type, chip stack type), package level type, wafer level type, and plain MCP (multi-chip package) type. In particular, a chip-on-chip type integrated circuit device is effective in achieving high density and high speed. Further, as a chip stack type integrated circuit device, one described in Patent Document 1 below is known, and as a plain MCP type integrated circuit device, one described in Patent Document 2 below is known.

JP 2003-124236 A JP-A-10-79623

  However, when a chip-on-chip type SIP structure is adopted, for example, an integrated circuit element (analog element) having an analog signal processing circuit connected to an antenna and an integrated circuit element (digital element) having a digital signal processing circuit connected thereto. Are simply stacked face-to-face and integrated three-dimensionally (integrated), the circuit forming surfaces of each other are arranged close to each other. Therefore, when the integrated circuit device is actually driven, there is a problem that distortion of the analog signal occurs due to noise leakage from the digital signal processing circuit to the analog signal processing circuit.

  An integrated circuit device according to the present invention is obtained by laminating an analog element having an analog signal processing circuit and a digital element having a digital signal processing circuit with their circuit formation surfaces facing each other, on the main surface of the digital element. In addition, an element circuit part including a digital signal processing circuit is formed, and a shield layer made of a soft magnetic material is formed so as to cover the element circuit part.

  In the integrated circuit device according to the present invention, the element circuit portion of the digital element is covered with a shield layer made of a soft magnetic material, thereby leaking noise generated in the digital signal processing circuit and unnecessary electromagnetic radiation to the analog signal processing circuit. Is suppressed by the shield layer.

  According to the integrated circuit device of the present invention, it is possible to improve the quality of an analog signal by suppressing the influence of noise and electromagnetic radiation on the analog signal processing circuit.

  Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

  1A and 1B show the configuration of an integrated circuit device according to a first embodiment of the present invention, in which FIG. 1A is a schematic sectional side view and FIG. 1B is a schematic plan view thereof. Note that FIG. 1A shows a cross section of the XX portion of FIG. In FIG. 1B, only half of the analog elements are displayed with the center line of the digital element as a boundary, and the other half is omitted. The illustrated integrated circuit device is roughly configured to include an analog element 1 and a digital element 2. The analog element 1 and the digital element 2 are electrically and mechanically connected via a plurality of solder balls 3. The external dimensions (planar vertical and horizontal dimensions) of the digital element 2 are set larger than those of the analog element 1. Then, the analog element 1 is mounted in the flip-chip method (chip-on-chip method) almost at the center of the digital element 2.

  The analog element 1 has an analog signal processing circuit for processing an analog signal, particularly a high frequency signal (RF signal). The analog signal processing circuit is formed on the main surface side of the analog element 1. More specifically, the analog element 1 is based on a semiconductor substrate 4 such as a silicon wafer, and an insulating film (not shown) is provided on one surface of the semiconductor substrate 4 (the lower surface of the semiconductor substrate 4 in FIG. 1). Thus, an element circuit portion 5 including an analog signal processing circuit is formed. The element circuit unit 5 is provided with a plurality of electrode pads 6 connected to the analog signal processing circuit.

  The analog element 1 is configured by, for example, a micro-electro-mechanical system (MEMS) element that is a minute electromechanical composite element, particularly, an RF-MEMS element that handles a high-frequency analog signal (RF signal). The MEMS element is obtained by a manufacturing process using a semiconductor manufacturing technique (microfabrication technique) on the semiconductor substrate 4 serving as a base of the analog element 1.

  The MEMS element has, for example, a hollow structure in which a fixed electrode serving as a signal input side and a beam electrode serving as a signal output side (movable electrode) are arranged in an opposed state with a minute gap on an insulating film of a substrate. None, by generating a Coulomb force (electrostatic attractive force, electrostatic repulsive force) between these electrodes by applying an external voltage, a filter element (MEMS resonator) that performs an electrical filter operation, and a switching operation It functions as a microswitch to be performed, and further as an optical element (such as an optical switch or a light modulation element).

  The hollow structure of the MEMS element is obtained by removing a thin film layer called a sacrificial layer by wet etching or the like, and in order to obtain this hollow structure, the formation part of the electrode pad 6 described above is another part. It is formed so as to be higher (projected). Specifically, as shown in FIG. 2, the insulating film 7 is formed on the semiconductor substrate 4, and the electrode pad 6 and the MEMS element wiring 9 are formed on the insulating film 7 via the sacrificial layer 8. Further, after forming the lead-out wiring 10 between the electrode pad 6 and the MEMS element wiring 9 and electrically connecting both (6, 9), the sacrificial layer (not shown) under the MEMS element wiring 9 is etched. By removing, the structure below the MEMS element wiring 9 is made a hollow structure. At this time, by leaving the sacrificial layer 8 under the electrode pad 6 without etching, the formation portion of the electrode pad 6 protrudes from the other portions.

  In the analog element 1 having such a MEMS element structure portion, an element circuit portion (including a MEMS element structure portion) 5 is formed in a wafer state, and then the element circuit portion 5 is covered with a protective film (not shown). The protective film is formed by applying a polymer resin on the entire surface of the wafer by a spin coating method, a spray method, a dip method or the like. After the protective film is formed, the wafer is divided into a plurality of analog elements (chips) 2 by dividing the wafer into individual pieces by a dicing apparatus or a laser processing machine, and is performed in the wafer state in advance. The non-defective product and the defective product are selected according to the inspection result of each element. Then, only the analog elements 1 selected as non-defective products are arranged on a temporary placement adhesive sheet or jig. Further, the protective element (resin) is removed by dipping in the solvent while the analog element 1 thus temporarily placed is held in a fixed state by vacuum suction or the like. At this time, the analog elements 1 regarded as non-defective products are positioned and arranged so that the corresponding digital elements 2 and the respective electrode positions (electrode pad forming portions) face each other.

  The digital element 2 has a digital signal processing circuit that processes a digital signal. The digital signal processing circuit is formed on the main surface of the digital element 2. More specifically, the digital element 2 is based on a semiconductor substrate 11 such as a silicon wafer, and an insulating film (not shown) is provided on one surface of the semiconductor substrate 11 (the upper surface of the semiconductor substrate 11 in FIG. 1). Thus, an element circuit unit 12 including a digital signal processing circuit is formed. Further, as shown in FIG. 3, the element circuit section 12 is provided with a plurality of electrode pads 13 connected to the digital signal processing circuit and a plurality of external connection pads 14. Among these, the plurality of electrode pads 13 are arranged on the main surface of the digital element 2 inside the area where the analog element 1 is mounted, and the plurality of external connection pads 14 are areas where the analog element 1 is mounted. Is disposed outside (close to the end face of the digital element 2).

  The electrode pad 13 is used for electrical connection with the analog element 1. That is, when the analog element 1 is mounted face-down on the digital element 2, the solder balls 3 are temporarily attached to the electrode pads 13 of the digital element 2 in advance, and the analog circuit so that the circuit formation surfaces face each other in this state. The analog element 1 and the digital element 2 are joined by sandwiching the solder ball 3 between the electrode pads 5 and 13 with the element 1 and the digital element 2 facing each other and melting the solder ball 3 by heat treatment. On the other hand, when the integrated circuit device in which the analog element 1 is mounted on the digital element 2 is mounted on a motherboard (not shown), for example, the external connection pad 14 is wire-bonded to the integrated circuit device and the motherboard. It is used for electrical connection by, for example.

  A shield layer 15 is formed on the main surface of the digital element 2 and on the element circuit portion 12. The shield layer 15 has a property of absorbing electromagnetic waves, and has, for example, a flat grain structure using a soft magnetic material mainly composed of Fe (iron), Co (cobalt), or the like. More specifically, a metal oxide (non-conductor) soft magnetic material having an electric resistance higher than that of metal, more specifically, Mn (manganese) -Zn (zinc) ferrite, Ni (nickel) -Zn ferrite, etc. The shield layer 15 is formed using soft ferrite. The shield layer 15 covers almost the entire area of the element circuit portion 12 except for the formation portions of the plurality of electrode pads 13 and the plurality of external connection pads 14 when the digital element 2 is viewed in a plan view. In addition, it is formed in a laminated state on the main surface of the digital element 2. Incidentally, in FIG. 1B and FIG. 3, the formation region of the shield layer 15 is surrounded by a broken line.

  The shield layer 15 is a final stage in the production of the digital element 2. For example, a plating method, a spin coating method, a coating method such as spray, a printing method such as a silk screen, a physical film forming method such as sputtering or vapor deposition, a CVD (Chemical It can be formed using a chemical film-forming method such as Vapor Deposition. For example, after forming a passivation film such as silicon nitride on the surface layer portion of the element circuit portion 12 in a wafer state, the portions of the electrode pad 13 and the external connection pad 14 are exposed by patterning using a photolithography technique. For example, an acrylic resin ink mixed with oxide soft ferrite fine particles is printed on the surface of the wafer (on the passivation film) by a silk screen method, so that almost the entire area of the element circuit portion 12 is covered with the shield layer 15. As the oxide soft ferrite fine particles used as the constituent material of the shield layer 15, Mn—Zn ferrite (for example, BSF-547 in which the average particle size of the fine particles is 3.2 μm: trade name of Toda Kogyo Co., Ltd.) is used. Can do.

  As a result, the shield layer 15 is formed on the main surface of the digital element 2 in the pattern shape as shown in FIG. The final thickness dimension of the shield layer 15 is determined in consideration of the results of simulations and preliminary experiments for confirming the actual shield effect, as well as the ease of film formation and the necessary cost in the actual manufacturing process. Moreover, the printing film thickness at the time of forming the shield layer 15 by silk screen printing is suitably set, for example in the range of 10-100 micrometers according to the ferrite content (10-50 volume%) in ink. After the acrylic resin ink is printed in this way, the acrylic resin ink is dried and cured by, for example, a drying process for 30 minutes in an environment of normal temperature or high temperature (maximum 120 ° C.). Thereafter, a solder ball 13 is temporarily attached to the portion of the electrode pad 13 exposed by the patterning using, for example, a conductive paste (solder paste or the like). The diameter of the solder ball 13 is appropriately set within a range of, for example, 100 to 300 μm in consideration of a thickness dimension of the shield layer 15 (for example, 100 μm at the maximum). At this time, when the electrode pad 13 is formed of Al (aluminum), the solder ball 3 whose composition of the solder material is adjusted for Al is used.

  In the integrated circuit device configured as described above, the analog element 1 is mounted on the digital element 2 with the element circuit portions 5 and 12 facing each other, and almost the entire area of the element circuit portion 12 of the digital element 2 is shielded. Since it is covered with the layer 15, the part facing the element circuit portion 5 of the analog element 1 on the main surface of the digital element 2 is covered with the shield layer 15 except for the pad opening for solder bonding. It becomes a state. As a result, the shield layer 15 covering the element circuit unit 12 of the digital element 2 faces the element circuit unit 5 of the analog element 1. Therefore, leakage of noise generated by switching or the like in the digital signal processing circuit is suppressed by the shield layer 15, and unnecessary electromagnetic radiation to the analog signal processing circuit is suppressed by absorption of electromagnetic waves in the shield layer 15. As a result, in the chip-on-chip integrated circuit device (SIP) in which the analog element 1 and the digital element 2 are three-dimensionally stacked and integrated, the influence of noise and electromagnetic radiation on the analog signal processing circuit is suppressed, Good quality of the analog signal can be maintained.

  Further, the analog element 1 has a configuration in which the portion where the electrode pad 6 is formed protrudes from the other portions by leaving the sacrificial layer 8 under the electrode pad 6 without being etched as described above. Therefore, when the analog element 1 and the digital element 2 are joined by the solder ball 3, a sufficient gap can be secured in the facing portion between the analog element 1 and the digital element 2. Therefore, by forming a MEMS element structure (see FIG. 2) in a region facing the digital element 2 in the element circuit section 5 of the analog element 1, mechanical movement (vibration) of the MEMS element using the hollow structure is performed. Etc.) can be mechanically protected by the digital element 1 without interfering with the digital element 1. Therefore, handling of the integrated circuit device is facilitated.

  4A and 4B show the configuration of an integrated circuit device according to the second embodiment of the present invention. FIG. 4A is a schematic side sectional view thereof, and FIG. 4B is a schematic plan view thereof. 4A shows a cross section of the X′-X ′ portion of FIG. In FIG. 4B, only half of the digital elements are displayed with the center line of the analog element as a boundary, and the other half is omitted. The illustrated integrated circuit device is roughly configured to include a digital element 21 and an analog element 22. The digital element 21 and the analog element 22 are electrically and mechanically connected via a plurality of solder balls 23. The external dimensions (planar vertical and horizontal dimensions) of the analog element 22 are set larger than that of the digital element 21. Then, the digital element 21 is mounted in the flip-chip method (chip-on-chip method) almost at the center of the analog element 22.

  The digital element 21 has a digital signal processing circuit for processing a digital signal. This digital signal processing circuit is formed on the main surface side of the digital element 21. More specifically, the digital element 21 is configured based on a semiconductor substrate 24 such as a silicon wafer, and an insulating film (not shown) is provided on one surface of the semiconductor substrate 24 (the lower surface of the semiconductor substrate 24 in FIG. 4). Thus, an element circuit unit 25 including a digital signal processing circuit is formed. The element circuit unit 25 is provided with a plurality of electrode pads 26 connected to the digital signal processing circuit.

  Further, a first shield layer 27 is formed on the main surface of the digital element 21 except for a portion where the electrode pad 26 is formed, and a second shield layer 28 is formed on the opposite surface (back surface). Yes. These shield layers 27 and 28 have the same material composition and function as the shield layer 15 described in the first embodiment. That is, each shield layer 27, 28 is a soft magnetic material mainly composed of Fe, Co, or the like, more specifically, Mn (manganese) -Zn (zinc) which is a soft magnetic material of metal oxide (non-conductor). ) It is formed using soft ferrite such as ferrite and Ni (nickel) -Zn ferrite. Among these, the 1st shield layer 27 is formed in the state which covers the substantially whole area (except for a pad formation part) of the element circuit part 25 of the digital element 21. The second shield layer 28 is formed so as to cover the entire back surface of the digital element 21. The second shield layer 28 may be provided as necessary.

  The shield layers 27 and 28 are the final stages for producing the digital element 21, and include, for example, a plating method, a spin coating method, a coating method such as spraying, a printing method such as a silk screen, a physical film forming method such as sputtering and vapor deposition, and a CVD method. It can be formed using a chemical film-forming method such as (Chemical Vapor Deposition). For example, after forming a passivation film such as silicon nitride on the surface layer portion of the element circuit portion 25 in a wafer state, the electrode pad 13 and the external connection pad 14 are exposed by patterning using a photolithography technique. For example, the first shield layer 27 covers almost the entire area of the element circuit portion 25 by applying ink mixed with oxide soft ferrite fine particles to the surface of the wafer (on the passivation film) by a spray method. At this time, the first shield layer 27 can be formed only in a desired region by covering a portion (such as a pad forming portion) where the ink is not applied with a mask. Further, the second shield layer 28 is formed on the back surface of the wafer by applying the same ink as described above by a spray method. The oxide soft ferrite fine particles used as the constituent materials of the shield layers 27 and 28 include Ni-Zn ferrite (for example, BSN-355B in which the average particle size of the fine particles is 5.5 μm: trade name of Toda Kogyo Co., Ltd.) ) Can be used. Thereafter, after the ink is dried and cured, for example, the wafer is divided into pieces by using a dicing machine, for example, so that one wafer is cut into a plurality of digital elements (chips) 21 and the wafer state in advance. The non-defective product and the defective product are selected according to the inspection result for each element. Then, a solder ball 23 is temporarily attached to the electrode pad 26 portion of the digital element 21 that is a non-defective product using, for example, a conductive paste (solder paste or the like). At this time, when the electrode pad 26 is formed of AU (gold), a solder ball 23 in which the composition of the solder material is adjusted for Au is used.

  The analog element 22 has an analog signal processing circuit for processing an analog signal, particularly a high frequency signal (RF signal). The analog signal processing circuit includes, for example, a switch for switching a signal line, a capacitor, a coil, an antenna, a high-frequency input circuit block configured by combining a compound semiconductor signal amplifier as necessary, a signal branch circuit, and the like It has the above-mentioned MEMS element structure. The analog signal processing circuit is formed on the main surface of the analog element 22. More specifically, the analog element 22 is configured based on, for example, an alumina substrate 29, and includes an element including a digital signal processing circuit on one surface of the alumina substrate 29 (the upper surface of the alumina substrate 29 in FIG. 4). A circuit portion 30 is formed. The element circuit section 30 is provided with a plurality of electrode pads 31 connected to the digital signal processing circuit and a plurality of external connection pads 32. Among these, the plurality of electrode pads 31 are arranged on the main surface of the analog element 22 inside the area where the digital element 21 is mounted, and the plurality of external connection pads 32 are areas where the digital element 21 is mounted. Is disposed outside (close to the end face of the analog element 22). Further, a circuit block 33 such as an antenna is formed on the main surface of the analog element 22 at a position separated from the mounting area by a predetermined dimension so as not to overlap the area where the digital element 21 is mounted.

  The electrode pad 31 is used for electrical connection with the digital element 21. That is, when the digital element 21 is mounted face-down on the analog element 22, the solder balls 23 are temporarily attached to the electrode pads 31 of the analog element 21 in advance, and each circuit formation surface faces in this state. The digital element 21 and the analog element 22 are joined by sandwiching the solder ball 23 between the electrode pads 26 and 31 with the element 21 and the analog element 22 facing each other and melting the solder ball 23 by heat treatment. On the other hand, when the integrated circuit device in which the digital element 21 is mounted on the analog element 22 is mounted on, for example, a motherboard (not shown), the external connection pad 32 is wire-bonded to the integrated circuit device and the motherboard. It is used for electrical connection by, for example.

  The analog element 22 is formed by dividing the wafer into individual pieces by a dicing apparatus or a laser processing machine in the final process after the formation of the element circuit part (including the MEMS element structure part) 30 in the wafer state. The wafers are cut into individual pieces, and non-defective products and defective products are selected according to the inspection results for each element previously performed in the wafer state. Separately, the digital element 21 selected as a non-defective product is placed face-to-face above the analog element 22 so that the solder balls 23 are sandwiched between the elements, and the solder balls are heated. By joining the digital element 21 and the analog element 22 by melting 23, an integrated circuit device having a chip-on-chip structure is obtained.

  In the integrated circuit device having the above-described configuration, the digital element 21 is mounted on the analog element 22 with the element circuit portions 25 and 30 facing each other, and almost the entire area of the element circuit portion 25 of the digital element 21 is provided in the first area. 1 on the main surface of the digital element 21, the portion facing the element circuit portion 30 of the analog element 22 is all the first except for the pad opening for solder bonding. The state is covered with the shield layer 27. As a result, the first shield layer 27 that covers the element circuit unit 25 of the digital element 21 faces the element circuit unit 30 of the analog element 21. Therefore, noise leakage caused by switching or the like in the digital signal processing circuit is suppressed by the first shield layer 27, and unnecessary electromagnetic radiation to the analog signal processing circuit is absorbed by electromagnetic waves in the first shield layer 27. It is suppressed. As a result, in a chip-on-chip integrated circuit device (SIP) in which the digital element 21 and the analog element 22 are three-dimensionally stacked and integrated, the influence of noise and electromagnetic radiation on the analog signal processing circuit is suppressed, Good quality of the analog signal can be maintained. Furthermore, since the surface opposite to the main surface of the digital element 21 is covered with the second shield layer 28, noise emission from the digital signal processing circuit can be suppressed. Therefore, the influence of noise on the analog signal processing circuit can be suppressed more reliably.

  In addition, as the configuration of the analog element 22, the digital element 21 and the analog element 22 are made to have a configuration in which the formation portion of the electrode pad 31 is protruded from other portions by the same means as in the first embodiment. When the solder balls 23 are joined, a sufficient gap can be secured in the facing portion between the digital element 21 and the analog element 22. Therefore, in the element circuit unit 30 of the analog element 22, the MEMS element structure unit is formed in a region facing the digital element 21, so that the MEMS element using the hollow structure does not hinder the mechanical movement of the MEMS element. The element structure can be mechanically protected by the digital element 21. Therefore, handling of the integrated circuit device is facilitated.

  In the first and second embodiments, the analog element and the digital element are joined by solder balls. However, the present invention is not limited to this, and the ball shape is made of a low melting point metal other than solder. It is good also as what joins two elements using this electrode.

1 is a diagram illustrating a configuration of an integrated circuit device according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the analog element which concerns on 1st Embodiment of this invention. It is a top view which shows the structure of the digital element which concerns on 1st Embodiment of this invention. It is a figure which shows the structure of the integrated circuit device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,22 ... Analog element, 2,21 ... Digital element, 3,23 ... Solder ball, 5, 12, 25, 30 ... Element circuit part, 15, 27, 28 ... Shield layer

Claims (5)

An integrated circuit device in which an analog element having an analog signal processing circuit and a digital element having a digital signal processing circuit are stacked with their circuit forming surfaces facing each other,
An integrated circuit comprising: an element circuit portion including the digital signal processing circuit formed on a main surface of the digital element; and a shield layer made of a soft magnetic material so as to cover the element circuit portion. apparatus. The integrated circuit device according to claim 1, wherein the shield layer is formed using a metal oxide. The integrated circuit device according to claim 1, wherein the analog element has a MEMS element structure. The integrated circuit device according to claim 2, wherein the metal oxide is soft ferrite. An element circuit part including the analog signal processing circuit is formed on a main surface of the analog element, and the MEMS element structure part is formed in a region facing the digital element in the element circuit part. 4. The integrated circuit device according to claim 3, wherein:

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