JP2006040983A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a multi-chip stack structure which hardly allows wire shorts to occur. <P>SOLUTION: The method of manufacturing the semiconductor device comprises processes of: preparing a wiring mother board which has a plurality of product formation regions with a chip mounting portion, and wire connection pads 5 formed on a first surface 2a and base electrodes 6 formed on a second surface 2b; fastening a semiconductor chip 17 of a lower stage on the chip mounting portion, and connecting the electrodes and the pads 5 by wires 20; applying an insulating resin 21 so as to selectively cover these and then making the surface of the insulating resin 21 into a flat surface 22 to form a coating resin layer 21; fastening a semiconductor chip 24 of an upper stage on the flat surface 22 and connecting the electrodes and the pads 5 by wires 26; forming an insulating resin layer so as to cover the coating resin 21 and the semiconductor chip 24, and wires 26; forming external electrode terminals 4 on the base electrodes 6; and dividing the wiring mother board and the resin layer lengthwise and crosswise into individual product formation regions. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a technique effective when applied to a method for manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked in a package.

  Portable electronic devices such as mobile phones and digital cameras have been made smaller and lighter due to their portability. For this reason, electronic parts such as semiconductor devices incorporated in these electronic devices (electronic devices) are further reduced in size and weight. In addition, the memory capacity tends to increase as the functionality of electronic device applications increases. Therefore, a semiconductor device in which a plurality of semiconductor chips are stacked to increase the capacity, that is, a semiconductor device having a so-called chip stack structure has been proposed.

  In one of the chip stack structures, a semiconductor chip (lower stage) is fixed to a wiring board having an opening in a state where an electrode is a lower surface (hereinafter referred to as face down), and the electrode is an upper surface on the lower semiconductor chip. The semiconductor chip (upper stage) is fixed in a state (hereinafter referred to as face-up). The lower semiconductor chip has a center pad structure in which electrodes are arranged along the center of the chip, and each electrode faces the opening. The electrode facing the opening and the wiring on the lower surface of the base substrate are connected by a wire and covered with a mold resin. Further, the electrodes of the upper semiconductor chip and the wiring on the upper surface of the base substrate are connected by wires and covered with a mold resin. A plurality of bump electrodes are provided on the lower surface of the base substrate (for example, Patent Document 1).

  Another one of the chip stack structures is to fix the LSI chip on the upper surface of the wiring board by flip chip connection, and to fix the other LSI chip on the LSI chip in a face-up state, The wiring on the upper surface of the wiring board is connected by a thin metal wire (for example, Patent Document 2).

  In another chip stack structure, a semiconductor chip (lower stage) is fixed to the upper surface of the substrate in a face-up state. The electrodes of the semiconductor chip and the wiring on the upper surface of the substrate are connected by wires. On the upper surface side of the semiconductor chip, a semiconductor chip (upper stage) having an insulating layer on the lower surface is fixed in a face-up state through an adhesive layer. The wires of the lower semiconductor chip are located in the adhesive layer. Further, the electrodes of the upper semiconductor chip and the wiring on the upper surface of the substrate are connected by wires (for example, Patent Document 3).

JP 2001-85609 A JP 2003-31763 A JP 2002-222913 A

  One technique for increasing the memory capacity is to employ the chip stack structure as described above. In the chip stack structure described in Patent Document 1, since an opening is provided in the wiring board, the electrode of the semiconductor chip must face the opening, which is a limitation. Further, since there is a difference in wire length between the lower semiconductor chip and the upper semiconductor chip, the inductance (L) is different and it is difficult to match the characteristics. For example, it is difficult to apply to a high-speed operation product such as a DDR-SDRAM.

  In the chip stack structure described in Patent Document 2, since the lower chip is flip chip connection (face down) and the upper chip is wire connection, the wiring length connected to the electrode of the semiconductor chip is greatly different. It becomes difficult to match the characteristics.

In the chip stack structure described in Patent Document 3, since the upper chip is pushed into the adhesive layer and stacked, the wires in the adhesive layer are pushed down, and a defect such as a short circuit is likely to occur.
An object of the present invention is to provide a method of manufacturing a semiconductor device having a chip stack structure in which a wire short circuit is unlikely to occur.
An object of the present invention is to provide a method of manufacturing a semiconductor device having a chip stack structure in which characteristics are well matched.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
(1) A manufacturing method of a semiconductor device of the present invention includes:
(A) A wiring board having product formation portions in a matrix, having a semiconductor chip mounting portion and a wire connection pad on a first surface of the product formation portion, opposite to the first surface of the product formation portion Preparing a wiring mother board having a plurality of base electrodes electrically connected to the wire connection pads on a second surface to be a surface;
(B) fixing the semiconductor chip to the semiconductor chip mounting portion of the product forming portion in a state where the surface having the electrodes is exposed;
(C) connecting the predetermined electrode of the semiconductor chip and the predetermined wire connection pad with a conductive wire;
(D) applying an insulating resin so as to cover the semiconductor chip and the wire without covering the wire connection pad;
(E) forming a coating resin layer in which a predetermined region of the upper surface is a flat surface by bringing a jig whose contact surface is flat into contact with the surface of the coated insulating resin;
(F) fixing the semiconductor chip on the flat surface of the coating resin layer in a state where a surface having an electrode is exposed;
(G) connecting the predetermined electrode of the semiconductor chip on the flat surface and the predetermined wire connection pad with a conductive wire;
(H) forming an insulating resin layer on the first surface of the wiring motherboard so as to cover the coating resin layer and the semiconductor chip and wires on the coating resin layer;
(I) forming an external electrode terminal on the base electrode on the second surface of the wiring motherboard;
(J) cutting the wiring mother board and the resin layer so as to divide the product forming portion into individual pieces.

  A semiconductor chip having a center pad structure in which electrodes are arranged along the center is fixed to a chip mounting portion of the wiring mother board, and a semiconductor chip having a center pad structure and / or a semiconductor chip having a peripheral pad structure in which electrodes are arranged in the periphery. Is fixed on the flat surface of the coating resin layer.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means of (1), (a) wire bonding is performed after the lower chip is connected in a face-up state, and then a coating resin layer is formed so as to protect the wire. Defects can be prevented. As a result, the reliability of the semiconductor device is improved.

(B) Since the surface of the coating resin layer is flattened and the upper chip is fixed to the flat surface, the upper chip can be fixed with high accuracy.
(C) If the lower chip and the upper chip are the same type of semiconductor chip, the lengths of the wires connected to the lower chip and the upper chip will be approximately the same in the lower chip and the upper chip. Can be performed satisfactorily. As a result, the present invention can be applied to high-speed products.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

  1 to 18 are diagrams relating to a semiconductor device having a chip stack structure and a manufacturing method thereof according to Embodiment 1 of the present invention. 1 to 3 are diagrams related to the structure of the semiconductor device, and FIGS. 4 to 18 are diagrams related to a method of manufacturing the semiconductor device. In the first embodiment, an example will be described in which semiconductor chips having an electrode array having a center pad structure are stacked in two steps in a face-up state.

  As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment has an insulating property formed on a rectangular wiring board 2 and a first surface 2 a of the wiring board 2. A plurality of external electrode terminals 4 (see FIGS. 2 and 2) formed on a sealing body 3 made of resin (see FIGS. 1 and 2) and a second surface 2b opposite to the first surface 2a of the wiring board 2. (See FIG. 3). The external electrode terminals 4 are not particularly limited, but are provided in three rows on both sides of the wiring board 2 as shown in FIG.

  The wiring substrate 2 is made of, for example, a glass epoxy resin substrate. As shown in FIGS. 1 and 2, the first surface 2a is provided with a row of wire connection pads 5 on both sides, and the second surface 2b is provided with a row. A base electrode 6 is provided. The first surface 2 a and the second surface 2 b that are separated from the wire connection pad 5 and the base electrode 6 are covered with insulating films (solder resist films) 7 and 8. Further, as shown in FIG. 2, a conductor layer 9 is provided in the middle layer of the wiring board 2. The conductor layer 9 is connected to the wire connection pad 5 and the base electrode 6 by a conductor 10 provided so as to extend vertically in the wiring board 2. Solder balls are attached to the surface of the base electrode 6 to form external electrode terminals 4. Accordingly, the predetermined wire connection pad 5 is electrically connected to the predetermined external electrode terminal 4 through the conductor 10, the conductor layer 9, and the conductor 10. Further, the wire connection pad 5 has a rectangular shape extending long in a direction orthogonal to the arrangement direction. A wire connected to the lower chip is connected to the inner side of the two rows of wire connection pads 5, and a wire connected to the upper chip is connected to the outer side.

  On the first surface 2a of the wiring board 2, a dam 15 protruding in a rectangular frame shape is formed so as to surround the semiconductor chip mounting region. A lower semiconductor chip 17 is mounted by an adhesive 16 on the wiring board surface (first surface 2 a) inside the dam 15. The adhesive body 16 is formed of, for example, an adhesive. The lower semiconductor chip 17 is fixed to the wiring board 2 in a face-up state where the electrodes are on the upper surface. As shown in FIGS. 2 and 1, the electrodes of the lower semiconductor chip 17 and the inner side portions of the wire connection pads 5 of the two rows of wire connection pads 5 are connected by conductive wires 20.

  In addition, a coating resin layer 21 made of an insulating resin is formed in a region inside the dam 15. The covering resin layer 21 covers the lower semiconductor chip 17 and the wires 20 connected to the electrodes of the semiconductor chip 17.

  On the other hand, the center of the coating resin layer 21 is recessed and a flat surface 22 is formed. The flat surface 22 has a size larger than that of the lower semiconductor chip 17. An upper semiconductor chip 24 is fixed to the flat surface 22 by an adhesive 23. The adhesive body 23 is formed of, for example, a double-sided tape having adhesiveness on both sides. In the first embodiment, the upper semiconductor chip 24 is a semiconductor chip that forms the same memory as the lower semiconductor chip 17 and has the same electrode arrangement (see FIGS. 8 and 14). Therefore, as shown in FIGS. 1 and 2, the electrodes 25 of the upper semiconductor chip 24 and the portions of the two rows of wire connection pads 5 on the outer side of the wire connection pads 5 are connected by the conductive wires 26. Has been.

  Further, a sealing body 3 made of an insulating resin is formed on the first surface 2 a of the wiring board 2 so as to completely cover the upper semiconductor chip 24 and the wires 26. In the manufacture of the semiconductor device 1, a wiring mother board that is a base of the wiring board 2 is used, and a resin layer that is a base of the sealing body 3 formed on the first surface of the wiring mother board is cut vertically and horizontally. Since it is formed, as shown in FIGS. 1 and 2, the wiring board 2 and the sealing body 3 have the same size.

  Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS. In manufacturing the semiconductor device 1, as shown in FIG. 4, a wiring mother board 30 is prepared.

  As shown in FIG. 4, the wiring mother board 30 has a structure having a plurality of product forming portions 31 partitioned in the plane direction. The wiring mother board 30 is made of, for example, a glass epoxy resin plate having a thickness of about 200 μm.

  The product forming portions 31 are arranged in a matrix in the vertical and horizontal directions. The product forming part 31 is a part where the one semiconductor device 1 described above is manufactured. In FIG. 4, the boundary of each product formation part 31 is shown with the dotted line. Since the boundary line is usually electroplated with a plating specification, a metal-plated wire is the boundary line. In the following description, a method for manufacturing a semiconductor device will be described mainly using this single product forming unit 31. In addition, the wiring mother board 30 is composed of a wiring board having a first surface and a second surface opposite to the first surface, and is cut at the boundary of the product forming portion at the final stage of the manufacturing process. By this cutting, the wiring mother board 30 becomes the wiring board 2. Therefore, also in the product forming unit 31, the first surface of the product forming unit 31 is referred to as the first surface 2a, and the second surface is referred to as the second surface 2b.

  FIG. 5 is a plan view in which a dam 15 protruding in a frame shape is formed on the first surface 2 a of the product forming portion 31. The structure of the product formation part 31 is the same structure as the wiring board 2 already demonstrated. That is, the wiring mother board 30 is made of, for example, a glass epoxy resin board, and has a rectangular chip mounting region 33 at the center of the first surface 2a of the product forming portion 31 as shown in FIG. A plurality of wire connection pads 5 are arranged in a row on the outside of the long side of the chip mounting region 33. The wire connection pad 5 has a rectangular shape and extends along the short side direction of the chip mounting region 33. Then, wires can be connected to the inner side and the outer side of the elongated wire connection pad 5, respectively. A wire connected to the lower chip is connected to the inner side, and a wire connected to the upper stage is connected to the outer side.

  As shown in FIG. 6, the base electrode 6 is provided on the second surface 2 b of the product forming portion 31. The external electrode terminal 4 is formed on the surface of the base electrode 6 as described above. Three rows of base electrodes 6 are arranged on the opposite surface of each row of wire connection pads 5.

  As shown in FIG. 6, the first surface 2 a and the second surface 2 b that are separated from the wire connection pad 5 and the base electrode 6 are covered with insulating films (solder resist films) 7 and 8. A conductor layer 9 is provided in the middle layer of the wiring mother board 30. The conductor layer 9 is connected to the wire connection pad 5 and the base electrode 6 by a conductor 10 provided so as to extend vertically in the wiring mother board 30.

  The dam 15 acts as a barrier (dam) that stops the flow of the resin when the above-described coating resin layer 21 is applied by a dispenser or the like. The dam 15 is formed by, for example, screen printing and has a height of about 20 μm. As shown in FIG. 7, the dam 15 may selectively remove the solder resist film 7 provided on the first surface 2a of the wiring mother board 30 and use the step portion of the removed portion as a dam. .

  Next, the semiconductor chip (lower semiconductor chip) 17 constituting the memory is mounted on the chip mounting region 33 inside the dam 15 in a face-up state where the electrode 18 is the upper surface. FIG. 8 is a plan view of a state in which the lower semiconductor chip 17 is fixed (chip bonding) to the first surface 2a of the product forming portion 31 and wire bonded. FIG. 9 is a sectional view taken along line XX in FIG. The lower semiconductor chip 17 is fixed to the wiring mother board 30 by the adhesive 16. The adhesive body 16 is, for example, an adhesive.

  Next, each electrode 18 at the center of the upper surface of the lower semiconductor chip 17 and each wire connection pad 5 on the first surface 2 a of the wiring motherboard 30 are connected by a conductive wire 20. At this time, the wire connection pad 5 is selected as the first bonding point and the electrode 18 is used as the second bonding point so that the height (loop height) of the wire 20 is lowered. Further, the first bonding point is selected in the region closer to the inside of the elongated wire connection pad 5.

  Next, as shown in FIGS. 10 and 11, an insulating resin 21 a is applied to the inner region of the dam 15. The insulating resin 21a in a fluid state rises in the rectangular dam 15 due to its surface tension. Then, the lower semiconductor chip 17 and the wire 20 are covered. Therefore, as shown in FIG. 12, the lower surface of the jig 34 is brought into contact with the insulating resin 21a.

  The jig 34 has a convex portion 35 projecting to the lower surface side, and the tip surface of the convex portion 35 is a flat surface 36. The convex portion 35 has a rectangular shape, which is larger than the above-described upper semiconductor chip 24 and smaller than the application region of the insulating resin 21a. As a result, a recess 37 is formed in the upper part of the insulating resin 21 a by the contact of the jig 34, and the bottom surface of the recess 37 becomes the flat surface 22. The contact operation of the jig 34 is performed in a state where the insulating resin 21 a is not cured, and is performed so as not to press the wire 20 by the jig 34. As a result, the wire 20 is not deformed and does not approach or come into contact with the adjacent wire 20, so that a short circuit does not occur. In a state where the wire 20 is not deformed, the insulating resin 21a is cured to form a cured coating resin layer 21 as shown in FIG. In FIG. 13, a rectangular region without dots is a recess 37 that becomes the flat surface 22.

  Next, as shown in FIGS. 14 and 15, the semiconductor chip (upper semiconductor chip) 24 is fixed on the flat surface 22 of the recess 37 formed in the upper portion of the coating resin layer 21 via the adhesive 23. In the first embodiment, the upper semiconductor chip 24 is the same as the lower semiconductor chip 17 and constitutes a memory. Therefore, the upper semiconductor chip 24 has the same dimensions as the lower semiconductor chip 17, and the arrangement (including functions) of the electrodes 25 is the same. The adhesive body 23 is formed of, for example, a thin double-sided tape having adhesiveness on both sides. As a result of using a thin double-sided tape, the work is easy and the semiconductor device 1 can be made thinner.

  Next, as shown in FIGS. 14 and 15, each electrode 25 at the center of the upper surface of the upper semiconductor chip 24 and each wire connection pad 5 on the first surface 2 a of the wiring mother board 30 are connected by a conductive wire 26. Connecting. At this time, the wire bonding pad 5 is selected as the first bonding point and the electrode 25 is used as the second bonding point so that the height (loop height) of the wire 26 is lowered. In addition, the first bonding point is selected in a region closer to the outside of the elongated wire connection pad 5.

  Next, as shown in FIG. 16, an insulating resin is formed on the entire first surface 2a of the wiring mother board 30 with a certain thickness, and the resin layer 40 covering the entire semiconductor chip 24 and the wires 26 is also covered. Form. The resin layer 40 is formed by, for example, a transfer molding method. FIG. 17 is a cross-sectional view of a single product forming portion 31. The resin layer 40 formed on the first surface 2 a of the wiring mother board 30 completely covers the covering resin layer 21, the upper semiconductor chip 24, and the wires 20 and 26. Here, as an example of the dimension in the thickness direction, the wiring mother board 30 is 200 μm thick, the adhesive 16 is 10 μm thick, the lower semiconductor chip 17 is 120 μm thick, and the lower semiconductor chip 17 and the upper semiconductor chip 17 are upper. The thickness of the covering resin layer 21 between the semiconductor chip 24 is 200 μm, the thickness of the adhesive 23 (tape) is 10 μm, the thickness of the upper semiconductor chip 24 is 120 μm, and the resin layer 40 on the upper semiconductor chip 24. The thickness is 250 μm. The height of the wire 26 connected to the upper semiconductor chip 24 from the semiconductor chip 24 is about 150 μm. Therefore, the thickness without forming the external electrode terminal 4 is as thin as 0.91 mm as a whole.

  Next, as shown in FIG. 18, the wiring mother board 30 is turned over, and the external electrode terminals 4 protruding from the surface of the base electrode 6 are formed with the second surface 2 b being the upper surface. For example, a solder ball having a diameter of about 450 μm is attached, and then the outer electrode terminal 4 having a height of about 350 μm is formed by forming a hemisphere by reflow (reheating treatment).

  Next, although not shown in the drawing, the wiring mother board 30 is cut (divided) at the boundary lines of the respective product forming portions 31 to manufacture a plurality of semiconductor devices 1 shown in FIGS. By this division, the wiring mother board 30 is divided into the wiring board 2, and the resin layer 40 is divided into the sealing body 3.

  FIGS. 19A to 19C are cross-sectional views showing a first modification of the method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 19A, Modification 1 selectively covers the lower semiconductor chip 17 and the wires 20 mounted on the first surface 2a of the wiring motherboard 30 as in the first embodiment. Insulating resin 21a is formed. Next, as shown in FIG. 19A, the upper semiconductor chip 24 is placed on the insulating resin 21a, and then the upper semiconductor chip 24 is slowly adjusted to a predetermined height with a jig 50 having a flat bottom surface. In this way, the insulating resin 21a is pressed so as to be partially embedded, and then the insulating resin 21a is cured. After the curing process, the jig 50 is removed.

  In the first modification, the insulating semiconductor 21a is formed on the upper semiconductor chip 24, and then the upper semiconductor chip 24 is directly connected to the upper semiconductor chip 24 using the jig 50 without forming a recess as in the first embodiment. The semiconductor chip 24 is partially hidden in the insulating resin 21a, and the insulating resin 21a is cured, and at the same time, the upper semiconductor chip 24 is fixed by the covering resin layer 21, thereby reducing the manufacturing cost by reducing the number of processes. Can be planned.

  20A to 20C are cross-sectional views showing a second modification of the method for manufacturing a semiconductor device according to the first embodiment. In the first modification, the jig 50 that presses the upper semiconductor chip 24 against the insulating resin 21a is a jig whose lower surface is a flat surface. However, in the second modification, the jig 50a is disposed on the lower surface thereof. A groove 51 into which the semiconductor chip 24 is fitted is provided, and the fixing position of the upper semiconductor chip 24 is determined by the groove 51. This facilitates subsequent wire bonding. In order to further improve the positioning of the upper semiconductor chip 24, a rectangular recess slightly larger than the semiconductor chip 24 is provided on the lower surface of the jig 50a, and the semiconductor chip 24 is placed in this recess to position the semiconductor chip 24. You may make it do. In this case, the positioning of the semiconductor chip 24 can be performed more accurately if the inner walls of the four sides of the depressions are inclined so that the width of the depressions gradually decreases toward the upper side.

According to the first embodiment, the following effects are obtained. (1) After connecting the lower chip (lower semiconductor chip) 17 in the face-up state, wire bonding is performed, and then the coating resin layer 21 is formed so as to protect the wire. Since it is formed, it is possible to prevent a short circuit between adjacent wires. As a result, the reliability of the semiconductor device 1 is improved.

  (2) Since the surface of the insulating resin 21a is flattened and the upper chip (upper semiconductor chip) 24 is fixed to the flat surface 22, the upper chip 24 can be fixed with high accuracy.

  (3) The lower chip 17 and the upper chip 24 can be mounted face up. The lower chip 17 can be incorporated even if the electrode arrangement is a center pad structure. Further, since the lower chip 17 and the upper chip 24 are the same type of semiconductor chip, the lengths of the wires 20 and 26 connected to the lower chip 17 and the upper chip 24 are substantially the same, and the characteristics are matched. Can be performed well. As a result, the present invention can be applied to high-speed products.

  (4) At the stage of the insulating resin 21a for forming the coating resin layer 21, the lower part of the upper chip 24 is submerged in the insulating resin 21a using the jigs 50 and 50a, and the insulating resin 21a is cured. By adopting the method of fixing the upper chip 24 with the coating resin layer 21, the manufacturing cost of the semiconductor device 1 can be reduced.

  21 and 22 are diagrams related to a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 21 is a plan view in which a part of the semiconductor device is cut out. FIG. It is sectional drawing which follows the XX line of 21.

  In the semiconductor device 1 according to the second embodiment, as shown in FIGS. 21 and 22, the lower semiconductor chip 17 has a center pad structure in the electrode arrangement, and the upper semiconductor chip 24 has a peripheral pad structure in the electrode arrangement. The lower semiconductor chip 17 has a center pad structure similar to that of the first embodiment. The upper semiconductor chip 24 has a structure in which electrodes 25 are arranged along the short sides of a rectangular semiconductor chip. Accordingly, the wire connection pads 5 connected to these electrodes via the wires 20 and 26 are arranged along each side of the rectangular wiring board 2. Other structural parts are the same as those of the semiconductor device 1 of the first embodiment.

  The second embodiment can be applied when the size of the upper semiconductor chip 24 in the peripheral pad structure is equal to or smaller than the size of the lower semiconductor chip 17 in the center pad structure. If the size of the spacer chip on the lower stage becomes too small, the chip disposed on the spacer chip cannot be disposed sufficiently stably. In such a case, the present embodiment is an effective structure.

  23 and 24 are diagrams relating to a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 23 is a plan view in which a part of the semiconductor device is cut away. FIG. It is sectional drawing which follows the XX line of 23.

In the semiconductor device 1 according to the third embodiment, the semiconductor chips incorporated in two stages on the first surface 2a side of the wiring board 2 are examples in which the electrode arrangement is a peripheral pad arrangement. The semiconductor device 1 of the third embodiment has the same structure as that of the semiconductor device 1 of the first embodiment except that the electrode arrangement of the lower semiconductor chip 17 and the upper semiconductor chip 24 is a peripheral pad arrangement. Yes.
The structure of the third embodiment is an effective structure when the normal chip stack and the spacer chip cannot be used.

  25 and 26 are diagrams relating to a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIG. 25 is a plan view in which a part of the semiconductor device is cut out. FIG. It is sectional drawing which follows the XX line of 25.

  The semiconductor device 1 according to the fourth embodiment is an example in which a middle semiconductor chip 55 is stacked between a lower semiconductor chip 17 and an upper semiconductor chip 24. The lower semiconductor chip 17 and the middle semiconductor chip 55 have a center pad structure, and the upper semiconductor chip 24 has a peripheral pad structure. A middle semiconductor chip 55 is fixed on the flat surface 22 of the coating resin layer 21 covering the lower semiconductor chip 17 with an adhesive 56. The middle semiconductor chip 55 is fixed face up. The electrodes of the middle semiconductor chip 55 are connected to the wire connection pads 5 by wires 57. The lower semiconductor chip 17, the middle semiconductor chip 55, and the wire bonding structure are the same as those in the first embodiment. That is, the wire 20 connected to the electrode of the lower semiconductor chip 17 is connected to the inner side of the elongated wire connection pad 5 outside the chip, and the wire 57 connected to the electrode of the middle semiconductor chip 55 is connected to the outer side of the chip. It is connected to the outside of the elongated wire connection pad 5.

  A coating resin layer 58 similar to the coating resin layer 21 is formed on the middle semiconductor chip 55. Since the upper semiconductor chip 24 is fixed on the coating resin layer 58, a recess 59 is also provided on the upper surface side of the coating resin layer 58. The bottom of the recess 59 is a flat surface 60. A wire 57 connected to the middle semiconductor chip 55 extends in the coating resin layer 58. An upper semiconductor chip 24 is fixed on the flat surface 60 via an adhesive 23. The electrode 25 of the upper semiconductor chip 24 is connected to the wire connection pad 5 provided on the first surface 2 a of the wiring substrate 2 via the wire 26. A sealing body 3 is formed on the first surface 2 a of the wiring board 2. On the first surface 2 a side of the wiring substrate 2, the whole including the upper semiconductor chip 24 and the wires 26 is covered with the sealing body 3.

  In the fourth embodiment, it becomes possible to further stack semiconductor chips, and it is possible to further increase functions and increase capacities. In the fourth embodiment, an example in which the middle semiconductor chips 55 are stacked in one stage is used. However, a plurality of middle semiconductor chips 55 may be mounted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
The present invention can be applied at least to the manufacture of a small and highly integrated semiconductor device.

It is the top view which notched a part of semiconductor device which is Example 1 of this invention. It is sectional drawing which follows the XX line of FIG. FIG. 6 is a bottom view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic perspective view of a wiring mother board used in the method for manufacturing a semiconductor device according to the first embodiment. It is a top view which shows the 1st surface of the product formation part of the said wiring mother board. It is sectional drawing which follows the XX line of FIG. It is sectional drawing which shows the other structural example of the said product formation part. In the manufacture of the semiconductor device of the first embodiment, it is a plan view of a state where chip bonding and wire bonding are performed on a first surface of a product forming portion. It is sectional drawing which follows the XX line of FIG. In the manufacture of the semiconductor device of Example 1, it is a plan view showing a state in which a semiconductor chip or the like mounted on a product forming portion is covered with a coating resin layer. It is sectional drawing which follows the XX line of FIG. It is sectional drawing which shows the state which planarizes the surface of the said coating resin layer. It is a top view of the product formation part by which the surface of the said coating resin layer was planarized. It is a top view of the state which carried out chip bonding and wire bonding on the said flat surface. It is sectional drawing which follows the XX line of FIG. It is a perspective view which shows the state which formed the insulating resin layer in the 1st surface of the wiring motherboard. It is sectional drawing of the product formation part covered with the said resin layer. It is sectional drawing which shows the state which formed the external electrode terminal in the 2nd surface of a product formation part. 7 is a cross-sectional view showing a first modification of the method for manufacturing a semiconductor device according to the first embodiment. FIG. It is sectional drawing which shows the modification 2 of the manufacturing method of the semiconductor device of the present Example 1. FIG. It is explanatory drawing which shows the wiring structure which leads to a connection electrode. It is a top view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which is Example 2 of this invention. It is sectional drawing which follows the XX line of FIG. It is a top view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which is Example 3 of this invention. It is sectional drawing which follows the XX line of FIG. It is a top view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which is Example 4 of this invention. It is sectional drawing which follows the XX line of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Wiring board, 2a ... 1st surface, 2b ... 2nd surface, 3 ... Sealing body, 4 ... External electrode terminal, 5 ... Wire connection pad, 6 ... Base electrode, 7, 8 Insulating film (solder resist film), 9 ... conductor layer, 10 ... conductor, 15 ... dam, 16 ... adhesive, 17 ... semiconductor chip (lower semiconductor chip), 18 ... electrode, 20 ... wire, 21 ... coating resin Layer 21a ... insulating resin 22 ... flat surface 23 ... adhesive body 24 ... semiconductor chip (upper semiconductor chip) 25 ... electrode 26 ... wire 30 ... wiring mother board 31 ... product forming part 33 ... chip mounting region, 34 ... jig, 35 ... convex portion, 36 ... flat surface, 37 ... depression, 40 ... resin layer, 50 ... jig, 51 ... groove, 55 ... middle semiconductor chip, 56 ... adhesive, 57 ... Wire, 58 ... Coating resin layer, 59 ... Dimple, 60 ... Flat surface

Claims (5)

(A) A wiring board having product formation portions in a matrix, having a semiconductor chip mounting portion and a wire connection pad on a first surface of the product formation portion, opposite to the first surface of the product formation portion Preparing a wiring mother board having a plurality of base electrodes electrically connected to the wire connection pads on a second surface to be a surface;
(B) fixing the semiconductor chip to the semiconductor chip mounting portion of the product forming portion in a state where the surface having the electrodes is exposed;
(C) connecting the predetermined electrode of the semiconductor chip and the predetermined wire connection pad with a conductive wire;
(D) applying an insulating resin so as to cover the semiconductor chip and the wire without covering the wire connection pad;
(E) forming a coating resin layer in which a predetermined region of the upper surface is a flat surface by bringing a jig whose contact surface is flat into contact with the surface of the coated insulating resin;
(F) fixing the semiconductor chip on the flat surface of the coating resin layer in a state where a surface having an electrode is exposed;
(G) connecting the predetermined electrode of the semiconductor chip on the flat surface and the predetermined wire connection pad with a conductive wire;
(H) forming an insulating resin layer on the first surface of the wiring motherboard so as to cover the coating resin layer and the semiconductor chip and wires on the coating resin layer;
(I) forming an external electrode terminal on the base electrode on the second surface of the wiring motherboard;
(J) A method of manufacturing a semiconductor device, comprising the step of cutting the wiring mother board and the resin layer so as to separate the product forming portion. Between the step (e) and the step (f),
(K) fixing the semiconductor chip on the flat surface of the coating resin layer in a state where a surface having an electrode is exposed;
(L) connecting the predetermined electrode of the semiconductor chip on the flat surface and the predetermined wire connection pad with a conductive wire;
(M) applying an insulating resin so as to cover the semiconductor chip and the wire on the flat surface;
(N) A step of forming a coating resin layer in which a predetermined region on the upper surface is a flat surface by bringing a jig having a flat contact surface into contact with the surface of the coated insulating resin is performed one or more times. The method of manufacturing a semiconductor device according to claim 1. In the step of preparing the wiring mother board, a dam that is one step higher than the mounting surface of the semiconductor chip mounting portion is provided so as to surround the semiconductor chip mounting portion,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of applying the insulating resin, the dam stops the flow of the applied insulating resin. In the step of preparing the wiring mother board, it is formed in a size that allows a plurality of wires to be connected to the wire connection pad,
The method of manufacturing a semiconductor device according to claim 1, wherein a wire connected to each of the semiconductor chips is connected to each of the wire connection pads. A semiconductor chip having a center pad structure in which electrodes are arranged along the center is fixed to the chip mounting portion of the wiring motherboard,
The semiconductor chip of the center pad structure and / or the semiconductor chip of the peripheral pad structure in which the electrode is arranged in the periphery are fixed on the flat surface of the coating resin layer. A method for manufacturing a semiconductor device.

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