KR20060072985A - Stacked package and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a stack package, comprising: a first semiconductor chip having a first solder bump formed on a first bonding pad, a metal plate formed on the first solder bump and patterned to extend outward, and a second bonding A second semiconductor chip having a second solder bump formed on a pad and having a metal plate formed thereon, the second semiconductor chip being stacked so that the second solder bump faces outward, and a second solder of the stacked second semiconductor chip formed thereon; A space is formed where a bump surface is bonded, and a third solder bump connected to the metal plate is formed at an upper end of the bump surface, and a molding is formed on the bottom of the substrate to which the solder balls are attached, and the first and second semiconductor chip products on the substrate. And an adhesive tape interposed between the first semiconductor chip and the second semiconductor chip and between the upper portion of the substrate and the stacked first semiconductor chip.

Description

Stacked package and method for manufacturing the same

1 is a cross-sectional view of a stack package according to a first embodiment of the present invention.

2A through 2E are cross-sectional views of processes of a stack package according to a first embodiment of the present invention.

3 is a cross-sectional view of a stack package according to a second embodiment of the present invention.

4 is a cross-sectional view of a stack package according to a third embodiment of the present invention.

5 is a cross-sectional view of a stack package according to a fourth embodiment of the present invention.

6 is a cross-sectional view of a stack package according to the fifth embodiment of the present invention.

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a stack package using a flip chip and a method for manufacturing the same.

Recently, according to the development of the semiconductor industry and the needs of users, electronic devices are becoming smaller and lighter, and packages, which are core components of electronic devices, are also becoming smaller and lighter. As a package type developed according to such a trend, a multilayer chip package implemented as one unit semiconductor chip package including a plurality of semiconductor chips stacked vertically is known. Such a laminated chip package is advantageous in size and weight in terms of size, weight, and mounting area, rather than using a plurality of unit semiconductor chip packages containing one semiconductor chip.

However, in the prior art, when stacking packages, at least one semiconductor chip is attached using wire bonding. However, as the length of the wire becomes longer, there are problems such as the wires falling in the mold flow process, and the height of the package due to the wire. In addition, due to the long electrical path of the wire there is a problem that the characteristics of the device operating at high speed is degraded.

Accordingly, in order to solve the above problems, an object of the present invention is to apply a flip chip technology to exclude the bonding wire process to solve the stack collapse and the height increase of the package due to the wire in the mold flow process and its manufacture To provide a way.

In order to achieve the above object, the stack package according to the present invention comprises a first semiconductor chip having a first solder bump formed on the first bonding pad, a metal plate formed on the first solder bump and patterned to extend outward, A second semiconductor chip having a second solder bump formed on a second bonding pad and having a metal plate formed thereon, the second semiconductor chip stacked so that a second solder bump faces outwardly; 2 A solder bump surface is provided, and a third solder bump connected to the metal plate is formed at an upper edge thereof, and a lower solder substrate is attached to a lower portion thereof, and the first and second semiconductor chip products are formed on the upper portion of the substrate. Including a molding covering the,

Adhesive tapes are interposed between the first semiconductor chip and the second semiconductor chip, and between the upper portion of the substrate and the stacked first semiconductor chip.

The metal plate is plated with Cu on a flexible polymer film.

A groove is formed in the upper space of the substrate, and the adhesive tape is formed to have the same thickness as the groove of the substrate.

The stack package according to the present invention comprises providing a first semiconductor chip having a first solder bump formed on a first bonding pad and a second semiconductor chip having a second solder bump formed on a second bonding pad, respectively; Forming a metal plate in an outwardly extending shape, stacking the second semiconductor chip on a surface on which the first solder bump of the first semiconductor chip is formed, and the second solder bump of the second semiconductor chip facing outward; And a space to which a surface on which the second solder bumps of the stacked second semiconductor chips are formed is attached, a third solder bump is formed on an upper edge of the stacked second semiconductor chip, and a substrate on which a solder ball is attached Providing a surface, bonding a surface on which the second solder bump of the stacked second semiconductor chip is formed in the upper space of the substrate, connecting the metal plate and the second solder bump, And forming moldings covering the first and second semiconductor chip products.

In the stacking process of the first semiconductor chip and the second semiconductor chip, an adhesive tape is interposed between the first semiconductor chip and the second semiconductor chip.

An adhesive tape is interposed between the upper space of the substrate and the stacked first and second semiconductor chips.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a stack package according to a first embodiment of the present invention. Hereinafter, the stack package according to the first embodiment of the present invention will be described with reference to FIG. 1.

As shown in FIG. 1, a first semiconductor chip 10 having a first solder bump 13 formed on a first bonding pad 11 and a second solder bump formed on a second bonding pad 21. A second semiconductor chip 20 is formed on the surface of the first solder bump 13 of the first semiconductor chip 10 so that the second solder bumps 23 face outwardly. Here, the first solder bump 13 is connected to a metal plate 51 patterned in an externally extending form. Here, the metal plate 51 is used that is plated with Cu on a flexible polymer film.

In addition, a plurality of first bonding pads 11 and second bonding pads 21 are formed at edge portions of the first and second semiconductor chips 10 and 20.

The substrate 30 has a space in which a second solder bump 23 surface of the stacked second semiconductor chip 20 is bonded at an upper portion thereof, and a third sole double bump connected to the metal plate 51 at an upper edge thereof. 33 is formed, and a solder ball 35 is attached to the lower portion of the substrate 30. Here, the groove C is formed in the upper space of the substrate 30 by the thickness of the first solder bumps 13.

A molding member 61 is formed on the substrate 30 to cover the first and second semiconductor chip products.

Meanwhile, a first adhesive tape 41 is interposed between the stacked first semiconductor chip 10 and the second semiconductor chip 20, and between the upper space of the substrate 30 and the stacked first semiconductor chip 10. The second adhesive tape 43 is interposed therebetween. Here, the first and second adhesive tapes 41 and 43 may be used in a B-stage state after the stencil printing of the epoxy.

2A through 2E are cross-sectional views of processes of a stack package according to a first embodiment of the present invention.

The method of manufacturing the stack package according to the first embodiment of the present invention described above, as shown in Figure 2a, the first semiconductor chip 10 and the second bonding pad (with the first bonding pad 11) ( Each of the second semiconductor chips 20 provided with 21 is provided. Subsequently, the first solder bumps 13 and the second solder bumps 23 are soldered to the first bonding pads 11 and the second bonding pads 21, respectively.

Then, a metal plate film (not shown) is formed on the first semiconductor chip 10 provided with the first solder bumps 13, and then the metal plate film is patterned to cover the first solder bumps 13 and partially cover the first solder bumps 13. The metal plate 51 is formed to extend to the outside. In this case, as the metal plate film, a copper plated Cu film is used. Thereafter, the second semiconductor chip 20 is stacked on the first semiconductor chip 10 provided with the metal plate 51. At this time, the first adhesive tape 41 is restarted between the first semiconductor chip 10 and the second semiconductor chip 20 to increase the adhesive force therebetween. On the other hand, in the stacking process, the second solder bump 23 surface of the second semiconductor chip 20 is directed toward the outside direction rather than the contact surface with the first semiconductor chip.

As shown in FIG. 2B, a space C to which the stacked first and second semiconductor chips are attached is provided at an upper portion thereof, a third solder bump 33 is formed at an upper edge thereof, and a solder ball ( Provided is a substrate 30 to which 35 is attached.

As shown in FIG. 2C, the second adhesive tape 43 is attached to the upper space C of the substrate 30. In this case, the second adhesive tape 43 is a state in which a portion corresponding to the second solder bump 23 of the second semiconductor chip 20 to be attached to the upper space C of the substrate is exposed.

As shown in FIG. 2D, the surface on which the second solder bumps 23 of the second semiconductor chip 20 stacked on the second adhesive tape 43 are formed is bonded. At this time, when the bonding, the first solder bump 33 formed on the substrate 20 should have a higher melting point than the first and second solder bumps 13 and 23 and the first and second solder chips soldered between the first and second semiconductor chips. Damage due to remelting of the second solder bumps can be prevented.

Subsequently, the metal plate 51 and the second solder bump 33 are bonded.

As shown in FIG. 2E, a molding 61 is formed on the substrate 20 to cover the first and second semiconductor chip products, thereby completing package fabrication.

3 is a view illustrating a second semiconductor chip bonded to an upper space of a substrate when a pad is formed at an edge portion and a first semiconductor chip has a pad formed at a center portion thereof. (Backside on which the second solder bump is formed) The metal plate 51a is formed on the whole and connected to the first solder bump and the third solder bump.

4 is a third embodiment of the present invention, when the second semiconductor chip bonded to the upper space of the substrate, the pad is formed in the center portion, the first semiconductor chip is formed in the pad portion on the edge portion, the first and the first on the substrate It shows a structure in which two semiconductor chips are stacked. Here, the third solder bump is connected by the first solder bump and the metal plate 51b.

FIG. 5 shows a fourth embodiment of the present invention, in which a pad is formed at an edge portion of a second semiconductor chip bonded to an upper space of a substrate and a pad is formed at a center portion of the first semiconductor chip. It shows a structure in which two semiconductor chips are stacked. Here, the metal plate 51c is formed on the entire back surface of the second semiconductor chip (the back surface on which the second solder bump is formed) and connected to the first solder bump and the third solder bump.

FIG. 6 illustrates a fifth embodiment of the present invention, in which a pad is formed at a center of a second semiconductor chip bonded to an upper space of a substrate, and a pad is formed at a center of a first semiconductor chip. It shows a structure in which two semiconductor chips are stacked. Here, the metal plate 51d is formed on the entire back surface of the second semiconductor chip (the back surface on which the second solder bump is formed) and is connected to the first solder bump and the third solder bump.

As described above, the present invention uses flip chip bonding to form a stack package, which eliminates the need for bonding wires, shortens the electrical path, and has higher responsiveness. In addition, problems such as the wire swept during molding and the height of the package due to the wire are solved. On the other hand, the problem that the characteristics of the device operating at high speed due to the long electrical path of the wire is also reduced.

In addition, the present invention enables various stacks according to the pattern structure of the substrate and the metal plate regardless of the bonding pad position of the semiconductor chip.

In addition, according to the present invention, the upper space of the substrate on which the second solder bump surface of the stacked second semiconductor chip is bonded is adhered to the adhesive tape, so that the adhesive tape is attached to a height as high as the adhesive tape, thereby minimizing damage to thermal shock and providing an electrical path to the metal plate. By shortening the characteristic can be improved.

Claims (7)

A first semiconductor chip having a first solder bump formed on a first bonding pad, A metal plate formed on the first solder bump and patterned to extend outwardly; A second semiconductor chip having a second solder bump formed on a second bonding pad and stacked on the upper surface of the first semiconductor chip on which the metal plate is formed so that the second solder bump faces outward; A space at which a second solder bump surface of the stacked second semiconductor chip is bonded is provided at an upper portion thereof, a third solder bump connected to the metal plate is formed at an upper edge thereof, and a substrate having a solder ball attached at a lower portion thereof; A molding covering the first and second semiconductor chip products on the substrate; The stack package, characterized in that the adhesive tape is interposed between the first semiconductor chip and the second semiconductor chip, and between the upper portion of the substrate and the stacked first semiconductor chip. The stack package of claim 1, wherein the metal plate is plated with Cu on a flexible polymer film. The stack package of claim 1, wherein a groove is formed in an upper space of the substrate. The stack package of claim 3, wherein the adhesive tape has the same thickness as the groove of the substrate. Providing a first semiconductor chip having a first solder bump formed on a first bonding pad and a second semiconductor chip having a second solder bump formed on a second bonding pad, respectively; Forming a metal plate on the first solder bump in an outward form; Stacking the second semiconductor chip on a surface on which the first solder bump of the first semiconductor chip is formed, wherein the second solder bump of the second semiconductor chip is directed outward; Providing a substrate to which a surface on which a second solder bump of the stacked second semiconductor chip is formed is attached, a third solder bump formed on an upper edge thereof, and a solder ball attached to a lower portion thereof; , Bonding a surface on which the second solder bump of the stacked second semiconductor chip is formed in an upper space of the substrate; Connecting the metal plate and the second solder bump; Forming a molding covering the first and second semiconductor chip products on the substrate. The stack package manufacturing method of claim 1, wherein the stacking process of the first semiconductor chip and the second semiconductor chip includes an adhesive tape interposed between the first semiconductor chip and the second semiconductor chip. The method of claim 1, wherein an adhesive tape is interposed between the upper space of the substrate and the stacked first and second semiconductor chips.

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