CN113488396B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN113488396B CN113488396B CN202111041020.XA CN202111041020A CN113488396B CN 113488396 B CN113488396 B CN 113488396B CN 202111041020 A CN202111041020 A CN 202111041020A CN 113488396 B CN113488396 B CN 113488396B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
Abstract
The invention relates to a semiconductor device and a preparation method thereof, wherein first, second, third and fourth blind holes are respectively formed in first, second, third and fourth grooves of first, second, third and fourth chips, first, second, third and fourth bulges are respectively formed on the back surfaces of the fifth, sixth, seventh and eighth chips, through holes are respectively formed on the side surfaces of the first, second, third and fourth bulges, then in the subsequent bonding process, adhesive materials are arranged in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, then the fifth, sixth, seventh and eighth chips are respectively correspondingly arranged in the first, second, third and fourth grooves, and the first, second, third and fourth bulges are respectively embedded into the corresponding first, second, third and fourth grooves, And a fourth blind hole, and a part of the bonding material in each blind hole is embedded into each through hole of each protrusion.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
In the conventional semiconductor stack package technology, an adhesive material is generally directly disposed between a first semiconductor chip and a second semiconductor chip to complete bonding of the first semiconductor chip and the second semiconductor chip, and the bonded first semiconductor chip and the bonded second semiconductor chip are then encapsulated by a resin material. However, in an actual packaging process, since the bonding stability of the first semiconductor chip and the second semiconductor chip is not high, peeling and dislocation between the first semiconductor chip and the second semiconductor chip are easily caused in a process of packaging with resin, which further affects the stability of the semiconductor stacked package structure, and further causes an increase in manufacturing cost.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies of the prior art and to provide a semiconductor device and a method for fabricating the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method of manufacturing a semiconductor device, comprising the steps of:
step (1): providing a first carrier plate, arranging a first elastic bonding layer on the first carrier plate, arranging a first chip, a second chip, a third chip and a fourth chip on the first elastic bonding layer, wherein the active surfaces of the first chip, the second chip, the third chip and the fourth chip face the first elastic bonding layer, and parts of the first chip, the second chip, the third chip and the fourth chip are all embedded into the first elastic bonding layer.
Step (2): then, a first groove, a second groove, a third groove and a fourth groove are respectively formed on the back surfaces of the first chip, the second chip, the third chip and the fourth chip, and a first blind hole, a second blind hole, a third blind hole and a fourth blind hole are respectively formed in the first groove, the second groove, the third groove and the fourth groove, wherein the depth of the first blind hole is smaller than that of the second blind hole, the depth of the second blind hole is smaller than that of the third blind hole, and the depth of the third blind hole is smaller than that of the fourth blind hole.
And (3): providing a second carrier plate, arranging a second elastic bonding layer on the second carrier plate, arranging a fifth chip, a sixth chip, a seventh chip and an eighth chip on the second elastic bonding layer, wherein the active surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip face the second elastic bonding layer, and parts of the fifth chip, the sixth chip, the seventh chip and the eighth chip are all embedded into the second elastic bonding layer, wherein the thickness of the fifth chip is smaller than that of the sixth chip, the thickness of the sixth chip is smaller than that of the seventh chip, and the thickness of the seventh chip is smaller than that of the eighth chip.
And (4): and then forming a first bump, a second bump, a third bump and a fourth bump on the back surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip respectively, wherein the height of the first bump is less than that of the second bump, the height of the second bump is less than that of the third bump, and the height of the third bump is less than that of the fourth bump.
And (5): a through hole penetrating the first protrusion is formed in a side surface of the first protrusion, a through hole penetrating the second protrusion is formed in a side surface of the second protrusion, a through hole penetrating the third protrusion is formed in a side surface of the third protrusion, and a through hole penetrating the fourth protrusion is formed in a side surface of the fourth protrusion.
And (6): and then, arranging bonding materials in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, correspondingly arranging the fifth, sixth, seventh and eighth chips in the first, second, third and fourth grooves respectively, embedding the first, second, third and fourth protrusions into the corresponding first, second, third and fourth blind holes respectively, and embedding a part of the bonding materials in the blind holes into the through holes of the protrusions.
And (7): and then removing the second carrier plate, and forming an organic packaging layer on the first carrier plate, wherein the organic packaging layer wraps each chip.
And (8): and then forming a first wiring layer on the upper surface of the organic packaging layer, removing the first carrier plate, and then forming a second wiring layer on the lower surface of the organic packaging layer.
In a more preferable technical solution, in the step (1), before the first elastic bonding layer is disposed on the first carrier, four first grooves respectively corresponding to the first, second, third, and fourth chips are formed on the first carrier, and then in the process of disposing the first elastic bonding layer, a part of the first elastic bonding layer is embedded into the first grooves, and further a part of each of the first, second, third, and fourth chips is respectively embedded into the corresponding first grooves.
In a more preferred embodiment, in the step (2), the first, second, third, and fourth trenches have the same depth, and the first, second, third, and fourth trenches and the first, second, third, and fourth blind holes are formed by wet etching, laser ablation, or mechanical cutting.
In a more preferable technical solution, in the step (3), before the second elastic bonding layer is disposed on the second carrier, four second grooves respectively corresponding to the fifth, sixth, seventh, and eighth chips are formed on the second carrier, and then in the process of disposing the second elastic bonding layer, a part of the second elastic bonding layer is embedded into the second grooves, and further a part of each of the fifth, sixth, seventh, and eighth chips is respectively embedded into the corresponding second grooves.
In a more preferred embodiment, in the step (4): forming the first, second, third and fourth protrusions by wet etching, laser ablation or mechanical cutting; in the step (5), the perforation is formed by a laser ablation process.
In a more preferred embodiment, in the step (6): a part of the bonding material in each blind hole is embedded into each through hole of each protrusion through a hot pressing process.
In a more preferred embodiment, in the step (7): the organic encapsulation layer includes an epoxy resin and a thermally conductive filler.
In a more preferred embodiment, in the step (8): conductive bumps are formed on the first wiring layer and the second wiring layer, respectively.
In a more preferred embodiment, the present invention further provides a semiconductor device manufactured according to the above manufacturing method.
Compared with the prior art, the semiconductor device and the preparation method thereof have the following beneficial effects: forming first, second, third and fourth blind holes in the first, second, third and fourth grooves of the first, second, third and fourth chips, respectively, forming first, second, third and fourth protrusions on the back surfaces of the fifth, sixth, seventh and eighth chips, respectively, forming through holes penetrating the first, second, third and fourth protrusions on the side surfaces of the first, second, third and fourth protrusions, respectively, and disposing adhesive materials in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, respectively, and disposing the fifth, sixth, seventh and eighth chips in the first, second, third and fourth grooves, respectively, and embedding the first, second, third and fourth protrusions into the corresponding first, second, third and fourth grooves, respectively, The second, third and fourth blind holes, and part of the bonding material in each blind hole is embedded into each through hole of each bump, the arrangement of the structure can improve the bonding stability of the stacked chips, and the stacked chips are effectively prevented from being peeled off. And the height difference of adjacent stacked chip structures can be adjusted by optimizing the thickness of each upper chip, the depth of each groove and the height of each protrusion, so that the diversity of the semiconductor device is enriched.
In the semiconductor device of the application, before the elastic bonding layer is arranged on the corresponding carrier plate, four first grooves respectively corresponding to the first chip, the second chip, the third chip and the fourth chip are formed on the carrier plate, and then in the process of arranging the first elastic bonding layer, a part of the first elastic bonding layer is embedded into the first grooves, so that a part of each of the first chip, the second chip, the third chip and the fourth chip is respectively embedded into the corresponding first grooves.
Drawings
FIG. 1 is a schematic structural diagram of step (1) in the fabrication of a semiconductor device according to the present invention;
FIG. 2 is a schematic structural diagram of step (2) in the fabrication of a semiconductor device according to the present invention;
FIG. 3 is a schematic structural diagram of step (3) in the process of manufacturing a semiconductor device according to the present invention;
FIG. 4 is a schematic structural diagram of step (4) in the process of manufacturing a semiconductor device according to the present invention;
FIG. 5 is a schematic diagram illustrating the structure of step (5) in the fabrication process of a semiconductor device according to the present invention;
FIG. 6 is a schematic diagram illustrating the structure of step (6) in the fabrication process of a semiconductor device according to the present invention;
FIG. 7 is a schematic diagram illustrating the structure of step (7) in the fabrication of a semiconductor device according to the present invention;
fig. 8 is a schematic structural diagram of step (8) in the process of manufacturing a semiconductor device according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
step (1): providing a first carrier plate, arranging a first elastic bonding layer on the first carrier plate, arranging a first chip, a second chip, a third chip and a fourth chip on the first elastic bonding layer, wherein the active surfaces of the first chip, the second chip, the third chip and the fourth chip face the first elastic bonding layer, and parts of the first chip, the second chip, the third chip and the fourth chip are all embedded into the first elastic bonding layer.
Step (2): then, a first groove, a second groove, a third groove and a fourth groove are respectively formed on the back surfaces of the first chip, the second chip, the third chip and the fourth chip, and a first blind hole, a second blind hole, a third blind hole and a fourth blind hole are respectively formed in the first groove, the second groove, the third groove and the fourth groove, wherein the depth of the first blind hole is smaller than that of the second blind hole, the depth of the second blind hole is smaller than that of the third blind hole, and the depth of the third blind hole is smaller than that of the fourth blind hole.
And (3): providing a second carrier plate, arranging a second elastic bonding layer on the second carrier plate, arranging a fifth chip, a sixth chip, a seventh chip and an eighth chip on the second elastic bonding layer, wherein the active surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip face the second elastic bonding layer, and parts of the fifth chip, the sixth chip, the seventh chip and the eighth chip are all embedded into the second elastic bonding layer, wherein the thickness of the fifth chip is smaller than that of the sixth chip, the thickness of the sixth chip is smaller than that of the seventh chip, and the thickness of the seventh chip is smaller than that of the eighth chip.
And (4): and then forming a first bump, a second bump, a third bump and a fourth bump on the back surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip respectively, wherein the height of the first bump is less than that of the second bump, the height of the second bump is less than that of the third bump, and the height of the third bump is less than that of the fourth bump.
And (5): a through hole penetrating the first protrusion is formed in a side surface of the first protrusion, a through hole penetrating the second protrusion is formed in a side surface of the second protrusion, a through hole penetrating the third protrusion is formed in a side surface of the third protrusion, and a through hole penetrating the fourth protrusion is formed in a side surface of the fourth protrusion.
And (6): and then, arranging bonding materials in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, correspondingly arranging the fifth, sixth, seventh and eighth chips in the first, second, third and fourth grooves respectively, embedding the first, second, third and fourth protrusions into the corresponding first, second, third and fourth blind holes respectively, and embedding a part of the bonding materials in the blind holes into the through holes of the protrusions.
And (7): and then removing the second carrier plate, and forming an organic packaging layer on the first carrier plate, wherein the organic packaging layer wraps each chip.
And (8): and then forming a first wiring layer on the upper surface of the organic packaging layer, removing the first carrier plate, and then forming a second wiring layer on the lower surface of the organic packaging layer.
In the step (1), before the first elastic bonding layer is disposed on the first carrier, four first grooves respectively corresponding to the first, second, third, and fourth chips are formed on the first carrier, and then in the process of disposing the first elastic bonding layer, a portion of the first elastic bonding layer is embedded into the first grooves, and further a portion of each of the first, second, third, and fourth chips is respectively embedded into the corresponding first grooves.
In the step (2), the first, second, third and fourth grooves have the same depth, and the first, second, third and fourth grooves and the first, second, third and fourth blind holes are formed through wet etching, laser ablation or mechanical cutting processes.
In the step (3), before the second elastic bonding layer is disposed on the second carrier, four second grooves respectively corresponding to the fifth, sixth, seventh, and eighth chips are formed on the second carrier, and in the process of disposing the second elastic bonding layer, a part of the second elastic bonding layer is embedded into the second grooves, and a part of each of the fifth, sixth, seventh, and eighth chips is embedded into the corresponding second grooves.
Wherein, in the step (4): forming the first, second, third and fourth protrusions by wet etching, laser ablation or mechanical cutting; in the step (5), the perforation is formed by a laser ablation process.
Wherein, in the step (6): a part of the bonding material in each blind hole is embedded into each through hole of each protrusion through a hot pressing process.
Wherein, in the step (7): the organic encapsulation layer includes an epoxy resin and a thermally conductive filler.
Wherein, in the step (8): conductive bumps are formed on the first wiring layer and the second wiring layer, respectively.
The invention also provides a semiconductor device manufactured and formed according to the manufacturing method.
As shown in fig. 1 to 8, the present embodiment provides a method for manufacturing a semiconductor device, including the steps of:
as shown in fig. 1, in step (1), a first carrier 300 is provided, a first elastic adhesive layer 302 is disposed on the first carrier 300, a first chip 303, a second chip 304, a third chip 305 and a fourth chip 306 are disposed on the first elastic adhesive layer 302, active surfaces of the first, second, third and fourth chips 303 and 306 face the first elastic adhesive layer 302, and a portion of each of the first, second, third and fourth chips 303 and 306 is embedded into the first elastic adhesive layer 302.
In a more specific embodiment, before the first elastic bonding layer 302 is disposed on the first carrier 300, four first grooves 301 corresponding to the first, second, third, and fourth chips are formed on the first carrier 300, so that a portion of the first elastic bonding layer 302 is embedded into the first grooves 301 in the process of disposing the first elastic bonding layer 302, and a portion of each of the first, second, third, and fourth chips 303 and 306 is embedded into the corresponding first groove 301.
In a more specific embodiment, the first carrier 300 may be one of a glass substrate, a stainless steel substrate, a single crystal silicon substrate, a polycrystalline silicon substrate, a sapphire substrate, a gallium nitride substrate, and a plastic substrate, the first carrier 300 may be a circular substrate or a square substrate, the area of the first carrier 300 is greater than the sum of the areas of the first, second, third, and fourth chips 303 and 306, and a certain distance is provided between every two of the first, second, third, and fourth chips 303 and 306, so as to facilitate the smooth performance of the following steps.
In a specific embodiment, the first elastic adhesive layer 302 is an elastic resin material, and may be a suitable material such as silicone, acrylic, rubber, and the like. Since four first grooves 301 respectively corresponding to the first, second, third and fourth chips are formed on the first carrier 300, the first elastic bonding layer 302 is embedded in the first grooves 301, and the first elastic bonding layer has a buffering performance, and a part of each of the first, second, third and fourth chips 303 and 306 is embedded in the first elastic bonding layer 302, so that the active surface of the chip can be effectively protected and the chip can be prevented from being damaged.
As shown in fig. 2, in step (2): then, a first trench 307, a second trench 308, a third trench 309 and a fourth trench 310 are respectively formed on the back surfaces of the first, second, third and fourth chips 303 and 306, and then a first blind hole 3071, a second blind hole 3081, a third blind hole 3091 and a fourth blind hole 3101 are respectively formed in the first, second, third and fourth trenches 307 and 310, wherein the depth of the first blind hole 3071 is smaller than that of the second blind hole 3081, the depth of the second blind hole 3081 is smaller than that of the third blind hole 3091, and the depth of the third blind hole 3091 is smaller than that of the fourth blind hole 3101.
In a specific embodiment, in the step (2), the first, second, third and fourth trenches 307 and 310 and the first, second, third and fourth blind holes 3071 and 3101 are formed by wet etching, laser ablation or mechanical cutting process, wherein the depths of the first, second, third and fourth trenches 307 and 310 are the same.
In a specific embodiment, since a portion of the first elastic adhesive layer 302 covers the side surfaces of the first, second, third and fourth chips 303 and 306, it can be ensured that the chips do not shift during the subsequent formation of the first, second, third and fourth trenches 307 and 310 and the first, second, third and fourth blind holes 3071 and 3101.
In another embodiment, the depths of the first, second, third and fourth trenches 307 and 310 may be different, further, the depth of the first trench 307 is smaller than the depth of the second trench 308, the depth of the second trench 308 is smaller than the depth of the third trench 309, the depth of the third trench 309 is smaller than the depth of the fourth trench 310, and by adjusting the size relationship between the depths of the trenches and the blind holes, the height difference between adjacent stacked chip structures can be adjusted, thereby enriching the diversity of the semiconductor device.
As shown in fig. 3, in step (3): providing a second carrier 400, disposing a second elastic adhesive layer 402 on the second carrier 400, disposing a fifth chip 403, a sixth chip 404, a seventh chip 405 and an eighth chip 406 on the second elastic adhesive layer 402, wherein active surfaces of the fifth, sixth, seventh and eighth chips 403 and 406 face the second elastic adhesive layer 402, and a portion of each of the fifth, sixth, seventh and eighth chips 403 and 406 is embedded in the second elastic adhesive layer 402, wherein the thickness of the fifth chip 403 is smaller than that of the sixth chip 404, the thickness of the sixth chip 404 is smaller than that of the seventh chip 405, and the thickness of the seventh chip 405 is smaller than that of the eighth chip 406.
In a specific embodiment, in the step (3), before the second elastic bonding layer 402 is disposed on the second carrier 400, four second grooves 401 respectively corresponding to the fifth, sixth, seventh and eighth chips 403 and 406 are formed on the second carrier 400, and in the process of disposing the second elastic bonding layer 402, a portion of the second elastic bonding layer 402 is embedded into the second grooves 401, and a portion of each of the fifth, sixth, seventh and eighth chips 403 and 406 is respectively embedded into the corresponding second groove 401.
In a more specific embodiment, the second carrier 400 may be one of a glass substrate, a stainless steel substrate, a single crystal silicon substrate, a polycrystalline silicon substrate, a sapphire substrate, a gallium nitride substrate, and a plastic substrate, the second carrier 400 may be a circular substrate or a square substrate, the area of the second carrier 400 is larger than the sum of the areas of the fifth, sixth, seventh, and eighth chips 403 and 406, and a certain distance is provided between every two of the fifth, sixth, seventh, and eighth chips 403 and 406, so as to facilitate the smooth performance of the following steps.
In a specific embodiment, the second elastic adhesive layer 402 is an elastic resin material, and may be a suitable material such as silicone, acrylic, rubber, and the like. Since four second grooves 401 respectively corresponding to the fifth, sixth, seventh and eighth chips 403 and 406 are formed on the second carrier 400, the second elastic bonding layer 402 is embedded in the second grooves 401, and has a buffering performance, and a part of each of the fifth, sixth, seventh and eighth chips 403 and 406 is embedded in the second elastic bonding layer 402, so that the active surface of the chip can be effectively protected and the chip can be prevented from being damaged.
As shown in fig. 4, in step (4): then, a first bump 407, a second bump 408, a third bump 409 and a fourth bump 510 are respectively formed on the respective back surfaces of the fifth, sixth, seventh and eighth chips 403 and 406, wherein the height of the first bump 407 is less than the height of the second bump 408, the height of the second bump 408 is less than the height of the third bump 409, and the height of the third bump 409 is less than the height of the fourth bump 410.
In a specific embodiment, in the step (4): the first, second, third and fourth protrusions 407 and 410 are formed by wet etching, laser ablation or mechanical cutting process.
In a more specific embodiment, a suitable mask such as photoresist is used to cover the respective back surfaces of the fifth, sixth, seventh, and eighth chips 403 and 406, and the mask is used to perform etching or cutting processing on the respective back surfaces of the fifth, sixth, seventh, and eighth chips 403 and 406, thereby forming the first, second, third, and fourth protrusions 407 and 410.
As shown in fig. 5, in step (5): a through hole 411 penetrating the first protrusion 407 is formed at a side surface of the first protrusion 407, a through hole 411 penetrating the second protrusion 408 is formed at a side surface of the second protrusion 408, a through hole 411 penetrating the third protrusion 409 is formed at a side surface of the third protrusion 409, and a through hole 411 penetrating the fourth protrusion 410 is formed at a side surface of the fourth protrusion 410.
In a specific embodiment, in the step (5), the through-hole 411 is formed by a laser ablation process.
As shown in fig. 6, in step (6): then, an adhesive material (not shown) is disposed in the first, second, third and fourth trenches 307-.
In a specific embodiment, in the step (6): a portion of the adhesive material in each of the blind holes 3071-3101 is embedded into each of the through holes 411 of each of the protrusions 407-410 by a thermal compression process.
In a specific embodiment, the adhesive material is an adhesive material commonly used in the art, and the adhesive material flows and is embedded into each through hole 411 through a hot pressing process.
As shown in fig. 7, in step (7): then, the second carrier 400 is removed, and then an organic encapsulation layer 500 is formed on the first carrier 300, wherein the organic encapsulation layer 500 wraps each chip.
In a specific embodiment, in the step (7): the organic encapsulation layer 500 includes an epoxy resin and a thermally conductive filler.
In a particular embodiment, the organic encapsulation layer 500 is formed by a suitable process such as transfer molding, injection molding, hot pressing, vacuum molding, drop coating, and the like.
More specifically, the heat conductive filler is suitable filler such as alumina, aluminum nitride, graphite, graphene, carbon nanotube, silicon carbide, and the like.
As shown in fig. 8, in step (8): then, a first wiring layer 600 is formed on the upper surface of the organic encapsulation layer 500, then the first carrier 300 is removed, and then a second wiring layer 700 is formed on the lower surface of the organic encapsulation layer 500.
In a specific embodiment, in the step (8): conductive bumps 800 are formed on the first wiring layer 600 and the second wiring layer 700, respectively.
In a specific embodiment, the first and second wiring layers 600 and 700 are redistribution layers including dielectric layers and metal wirings, and the conductive bump 800 is a conductive solder ball or a metal copper pillar.
As shown in fig. 8, the present invention also provides a semiconductor device manufactured according to the above-mentioned manufacturing method.
Compared with the prior art, the semiconductor device and the preparation method thereof have the following beneficial effects: forming first, second, third and fourth blind holes in the first, second, third and fourth grooves of the first, second, third and fourth chips, respectively, forming first, second, third and fourth protrusions on the back surfaces of the fifth, sixth, seventh and eighth chips, respectively, forming through holes penetrating the first, second, third and fourth protrusions on the side surfaces of the first, second, third and fourth protrusions, respectively, and disposing adhesive materials in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, respectively, and disposing the fifth, sixth, seventh and eighth chips in the first, second, third and fourth grooves, respectively, and embedding the first, second, third and fourth protrusions into the corresponding first, second, third and fourth grooves, respectively, The second, third and fourth blind holes, and part of the bonding material in each blind hole is embedded into each through hole of each bump, the arrangement of the structure can improve the bonding stability of the stacked chips, and the stacked chips are effectively prevented from being peeled off. And the height difference of adjacent stacked chip structures can be adjusted by optimizing the thickness of each upper chip, the depth of each groove and the height of each protrusion, so that the diversity of the semiconductor device is enriched.
In the semiconductor device of the application, before the elastic bonding layer is arranged on the corresponding carrier plate, four first grooves respectively corresponding to the first chip, the second chip, the third chip and the fourth chip are formed on the carrier plate, and then in the process of arranging the first elastic bonding layer, a part of the first elastic bonding layer is embedded into the first grooves, so that a part of each of the first chip, the second chip, the third chip and the fourth chip is respectively embedded into the corresponding first grooves.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for manufacturing a semiconductor device, comprising: the method comprises the following steps:
step (1): providing a first carrier plate, arranging a first elastic bonding layer on the first carrier plate, arranging a first chip, a second chip, a third chip and a fourth chip on the first elastic bonding layer, wherein the active surfaces of the first chip, the second chip, the third chip and the fourth chip face the first elastic bonding layer, and parts of the first chip, the second chip, the third chip and the fourth chip are embedded into the first elastic bonding layer;
step (2): then, respectively forming a first groove, a second groove, a third groove and a fourth groove on the back surfaces of the first chip, the second chip, the third chip and the fourth chip, and respectively forming a first blind hole, a second blind hole, a third blind hole and a fourth blind hole in the first groove, the second groove, the third groove and the fourth groove, wherein the depth of the first blind hole is smaller than that of the second blind hole, the depth of the second blind hole is smaller than that of the third blind hole, and the depth of the third blind hole is smaller than that of the fourth blind hole;
and (3): providing a second carrier plate, arranging a second elastic bonding layer on the second carrier plate, arranging a fifth chip, a sixth chip, a seventh chip and an eighth chip on the second elastic bonding layer, wherein the active surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip face the second elastic bonding layer, and parts of the fifth chip, the sixth chip, the seventh chip and the eighth chip are all embedded into the second elastic bonding layer, wherein the thickness of the fifth chip is smaller than that of the sixth chip, the thickness of the sixth chip is smaller than that of the seventh chip, and the thickness of the seventh chip is smaller than that of the eighth chip;
and (4): then, respectively forming a first bump, a second bump, a third bump and a fourth bump on the back surfaces of the fifth chip, the sixth chip, the seventh chip and the eighth chip, wherein the height of the first bump is smaller than that of the second bump, the height of the second bump is smaller than that of the third bump, and the height of the third bump is smaller than that of the fourth bump;
and (5): forming a through hole penetrating the first protrusion on a side surface of the first protrusion, forming a through hole penetrating the second protrusion on a side surface of the second protrusion, forming a through hole penetrating the third protrusion on a side surface of the third protrusion, and forming a through hole penetrating the fourth protrusion on a side surface of the fourth protrusion;
and (6): then, arranging bonding materials in the first, second, third and fourth grooves and the first, second, third and fourth blind holes, further correspondingly arranging the fifth, sixth, seventh and eighth chips in the first, second, third and fourth grooves respectively, embedding the first, second, third and fourth protrusions into the corresponding first, second, third and fourth blind holes respectively, and embedding a part of the bonding materials in the blind holes into the through holes of the protrusions;
and (7): removing the second carrier plate, and forming an organic packaging layer on the first carrier plate, wherein the organic packaging layer wraps each chip;
and (8): and then forming a first wiring layer on the upper surface of the organic packaging layer, removing the first carrier plate, and then forming a second wiring layer on the lower surface of the organic packaging layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (1), before the first elastic bonding layer is disposed on the first carrier, four first grooves corresponding to the first, second, third, and fourth chips are formed on the first carrier, and then a portion of the first elastic bonding layer is embedded into the first grooves during the process of disposing the first elastic bonding layer, and further a portion of each of the first, second, third, and fourth chips is embedded into the corresponding first grooves.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (2), the first, second, third and fourth grooves have the same depth, and the first, second, third and fourth grooves and the first, second, third and fourth blind holes are formed through wet etching, laser ablation or mechanical cutting processes.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (3), before the second elastic bonding layer is disposed on the second carrier, four second grooves corresponding to the fifth, sixth, seventh, and eighth chips, respectively, are formed on the second carrier, and in the process of disposing the second elastic bonding layer, a portion of the second elastic bonding layer is embedded into the second grooves, and a portion of each of the fifth, sixth, seventh, and eighth chips is embedded into the corresponding second groove, respectively.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (4): forming the first, second, third and fourth protrusions by wet etching, laser ablation or mechanical cutting; in the step (5), the perforation is formed by a laser ablation process.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (6): a part of the bonding material in each blind hole is embedded into each through hole of each protrusion through a hot pressing process.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (7): the organic encapsulation layer includes an epoxy resin and a thermally conductive filler.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: in the step (8): conductive bumps are formed on the first wiring layer and the second wiring layer, respectively.
9. A semiconductor device formed by the manufacturing method according to any one of claims 1 to 8.
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