CN113471083B - Semiconductor stack packaging structure and preparation method thereof - Google Patents
Semiconductor stack packaging structure and preparation method thereof Download PDFInfo
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- CN113471083B CN113471083B CN202111029055.1A CN202111029055A CN113471083B CN 113471083 B CN113471083 B CN 113471083B CN 202111029055 A CN202111029055 A CN 202111029055A CN 113471083 B CN113471083 B CN 113471083B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Abstract
The invention relates to a semiconductor stack packaging structure and a preparation method thereof. And forming a plurality of second bumps arranged in parallel on four side surfaces of the second semiconductor chip, forming a first bonding bump on the upper surface of each second bump, and bonding the second semiconductor chip to the first semiconductor chip so that the first bonding bumps are embedded into the corresponding first bonding grooves. The arrangement of the structure can improve the bonding strength of the first semiconductor chip and the second semiconductor chip, and further can improve the stability of the semiconductor stack packaging structure.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor stacked packaging structure and a preparation method thereof.
Background
In the conventional semiconductor package on package structure, one surface of one semiconductor chip is directly bonded to another surface of another semiconductor chip, and the stacked semiconductor chips are packaged by using a resin packaging material to form the semiconductor package on package structure. In the process of practical application, because the semiconductor chips can generate heat in the working process, heat transfer can occur between the adjacent semiconductor chips, and then the adjacent semiconductor chips can be influenced mutually, and the heat can not be dissipated quickly. There is a great deal of attention on how to eliminate the thermal influence of adjacent semiconductor chips in the semiconductor package on package structure and to improve the heat dissipation performance of the semiconductor package on package structure.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art and to provide a semiconductor package on package structure and a method for fabricating the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for preparing a semiconductor stack packaging structure comprises the following steps:
step (1): providing a first carrier substrate, and arranging a first semiconductor chip on the carrier substrate, wherein an active functional surface of the first semiconductor chip faces the first carrier substrate.
Step (2): and then, etching the first semiconductor chip, forming a plurality of first bulges which are arranged in parallel on four side surfaces of the first semiconductor chip respectively, forming a first groove on the upper surface of the first semiconductor chip, and forming four first groove extending parts which extend from the first groove to the four side surfaces of the first semiconductor chip respectively.
And (3): and then etching the upper surface of each first protrusion to form a first bonding groove on the upper surface of each first protrusion.
And (4): a first thermally conductive layer is then formed in the first recess and the first recess extension, and a first thermally insulating layer is then formed over the first thermally conductive layer.
And (5): providing a second carrier substrate, and arranging a second semiconductor chip on the carrier substrate, wherein the active functional surface of the second semiconductor chip faces the second carrier substrate.
And (6): and then, etching the second semiconductor chip, forming a plurality of second bulges which are arranged in parallel on four side surfaces of the second semiconductor chip respectively, forming a second groove on the upper surface of the second semiconductor chip, and forming four second groove extending parts which extend from the second groove to the four side surfaces of the second semiconductor chip respectively.
And (7): and then etching the upper surface of each second bump and the upper surface of the second semiconductor chip to form a first bonding bump on the upper surface of each second bump.
And (8): a second thermally conductive layer is then formed in the second recess and the second recess extension, and a second thermally insulating layer is then formed on the second thermally conductive layer.
And (9): the second semiconductor chip is then bonded to the first semiconductor chip such that the first bonding bumps are embedded in the respective first bonding grooves.
Step (10): a first encapsulation layer is then formed, the first encapsulation layer wrapping around the underside of the first semiconductor chip, and then a first heat-conducting member is formed on the first encapsulation layer, the first heat-conducting member being embedded in a gap between adjacent first bumps to contact the first heat-conducting layer.
Step (11): and then forming a second heat insulating encapsulation layer covering the upper surface of the first heat conductive member, then forming a second heat conductive member on the second heat insulating encapsulation layer, the second heat conductive member being embedded in a gap between adjacent second protrusions to contact the second heat conductive layer, then forming a third encapsulation layer on the second heat insulating encapsulation layer, the third encapsulation layer covering the second heat conductive member.
In a more preferable technical solution, in the step (2), the etching process is a wet etching or a dry etching, the first groove and the first groove extension portion are formed in the same etching process by using a mask, and a depth of the first groove extension portion is greater than a depth of the first groove.
In a more preferred embodiment, in the step (3), the first bonding groove is formed by a laser ablation process, and a ratio of a depth of the first bonding groove to a thickness of the first protrusion is 0.3 to 0.5.
In a more preferred embodiment, in the steps (4) and (8), the material of the first and second heat conduction layers is one of copper, aluminum, silver, graphene, and carbon nanotubes, and the material of the first and second thermal insulation layers is one of silicon dioxide, epoxy resin, polystyrene, polyvinyl alcohol, polyethylene, and polymethyl methacrylate.
In a more preferable technical solution, in the step (6), the etching process is a wet etching or a dry etching, the second groove and the second groove extension portion are formed in the same etching process by using a mask, and a depth of the second groove extension portion is greater than a depth of the second groove.
In a more preferred embodiment, in the step (7), a ratio of a height of the first bonding protrusion to a depth of the first bonding groove is 0.8 to 0.95.
In a more preferred embodiment, in the step (10), the first encapsulation layer includes an epoxy resin and a thermally conductive filler, and a material of the first thermally conductive member is copper or aluminum.
In a more preferable technical solution, in the step (11), the second heat insulation encapsulation layer is an epoxy resin layer, the second heat conducting member is made of copper or aluminum, and the third encapsulation layer includes epoxy resin and a heat conducting filler.
In a more preferable technical scheme, the invention further provides a semiconductor stack package structure which is prepared and formed by adopting the preparation method.
Compared with the prior art, the semiconductor stack packaging structure and the preparation method thereof have the following beneficial effects:
first, a plurality of first bumps arranged in parallel are respectively formed on four side surfaces of the first semiconductor chip, and a first bonding groove is formed on the upper surface of each first bump. And forming a plurality of second bumps arranged in parallel on four side surfaces of the second semiconductor chip, forming a first bonding bump on the upper surface of each second bump, and bonding the second semiconductor chip to the first semiconductor chip so that the first bonding bumps are embedded into the corresponding first bonding grooves. The arrangement of the structure can improve the bonding strength of the first semiconductor chip and the second semiconductor chip, and further can improve the stability of the semiconductor stack packaging structure.
Secondly, forming a first groove on the upper surface of the first semiconductor chip, forming four first groove extending parts respectively extending from the first groove to four side surfaces of the first semiconductor chip, then forming a first heat conduction layer on the first groove and the first groove extending parts, and then forming a first heat insulation layer on the first heat conduction layer; a second groove is formed on the upper surface of the second semiconductor chip, four second groove extending portions extending from the second groove to four side surfaces of the second semiconductor chip are formed, a second heat conduction layer is formed on the second groove and the second groove extending portions, and a second heat insulation layer is formed on the second heat conduction layer. The arrangement of the structure can facilitate the heat dissipation of each semiconductor chip on one hand and reduce the heat influence between the adjacent semiconductor chips on the other hand.
Drawings
FIG. 1 is a schematic structural diagram of step (1) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 2 is a schematic structural diagram of step (2) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 3 is a schematic structural diagram of step (3) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 4 is a schematic structural diagram of step (4) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 5 is a schematic structural diagram of step (5) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 6 is a schematic structural diagram of step (6) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 7 is a schematic structural diagram of step (7) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 8 is a schematic structural diagram of step (8) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 9 is a schematic structural diagram of step (9) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 10 is a schematic structural diagram of step (10) in the process of manufacturing a semiconductor package on package structure according to the present invention;
FIG. 11 is a schematic structural diagram of step (11) in the process of manufacturing a semiconductor package on package structure according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a preparation method of a semiconductor stack packaging structure, which comprises the following steps:
step (1): providing a first carrier substrate, and arranging a first semiconductor chip on the carrier substrate, wherein an active functional surface of the first semiconductor chip faces the first carrier substrate.
Step (2): and then, etching the first semiconductor chip, forming a plurality of first bulges which are arranged in parallel on four side surfaces of the first semiconductor chip respectively, forming a first groove on the upper surface of the first semiconductor chip, and forming four first groove extending parts which extend from the first groove to the four side surfaces of the first semiconductor chip respectively.
And (3): and then etching the upper surface of each first protrusion to form a first bonding groove on the upper surface of each first protrusion.
And (4): a first thermally conductive layer is then formed in the first recess and the first recess extension, and a first thermally insulating layer is then formed over the first thermally conductive layer.
And (5): providing a second carrier substrate, and arranging a second semiconductor chip on the carrier substrate, wherein the active functional surface of the second semiconductor chip faces the second carrier substrate.
And (6): and then, etching the second semiconductor chip, forming a plurality of second bulges which are arranged in parallel on four side surfaces of the second semiconductor chip respectively, forming a second groove on the upper surface of the second semiconductor chip, and forming four second groove extending parts which extend from the second groove to the four side surfaces of the second semiconductor chip respectively.
And (7): and then etching the upper surface of each second bump and the upper surface of the second semiconductor chip to form a first bonding bump on the upper surface of each second bump.
And (8): a second thermally conductive layer is then formed in the second recess and the second recess extension, and a second thermally insulating layer is then formed on the second thermally conductive layer.
And (9): the second semiconductor chip is then bonded to the first semiconductor chip such that the first bonding bumps are embedded in the respective first bonding grooves.
Step (10): a first encapsulation layer is then formed, the first encapsulation layer wrapping around the underside of the first semiconductor chip, and then a first heat-conducting member is formed on the first encapsulation layer, the first heat-conducting member being embedded in a gap between adjacent first bumps to contact the first heat-conducting layer.
Step (11): and then forming a second heat insulating encapsulation layer covering the upper surface of the first heat conductive member, then forming a second heat conductive member on the second heat insulating encapsulation layer, the second heat conductive member being embedded in a gap between adjacent second protrusions to contact the second heat conductive layer, then forming a third encapsulation layer on the second heat insulating encapsulation layer, the third encapsulation layer covering the second heat conductive member.
In the step (2), the etching process is a wet etching process or a dry etching process, the first groove and the first groove extension portion are formed in the same etching process by using a mask, and the depth of the first groove extension portion is greater than that of the first groove.
Wherein, in the step (3), the first bonding groove is formed through a laser ablation process, and a ratio of a depth of the first bonding groove to a thickness of the first protrusion is 0.3-0.5.
In the steps (4) and (8), the first and second heat conduction layers are made of one of copper, aluminum, silver, graphene and carbon nanotubes, and the first and second heat insulation layers are made of one of silicon dioxide, epoxy resin, polystyrene, polyvinyl alcohol, polyethylene and polymethyl methacrylate.
In the step (6), the etching process is a wet etching process or a dry etching process, and the second groove extension portion are formed in the same etching process by using a mask, wherein the depth of the second groove extension portion is greater than that of the second groove.
Wherein, in the step (7), a ratio of a height of the first bonding protrusion to a depth of the first bonding groove is 0.8-0.95.
In the step (10), the first encapsulation layer includes epoxy resin and a heat conductive filler, and the first heat conductive member is made of copper or aluminum.
In the step (11), the second heat insulation packaging layer is an epoxy resin layer, the second heat conducting member is made of copper or aluminum, and the third packaging layer includes epoxy resin and a heat conducting filler.
The invention also provides a semiconductor stack packaging structure which is prepared by the preparation method.
As shown in fig. 1 to 11, the present embodiment provides a method for manufacturing a semiconductor package on package structure, the method includes the following steps:
as shown in fig. 1, in step (1), a first carrier substrate 100 is provided, a first semiconductor chip 101 is disposed on the carrier substrate 100, and an active functional surface of the first semiconductor chip 101 faces the first carrier substrate 100.
In a specific embodiment, the first semiconductor chip is bonded to the first carrier substrate 100 for 101 years.
As shown in fig. 2, in step (2): then, the first semiconductor chip is etched, a plurality of first protrusions 102 arranged in parallel are formed on four side surfaces of the first semiconductor chip 101, a first groove 103 is formed on an upper surface of the first semiconductor chip 101, and four first groove extensions 104 extending from the first groove 103 to the four side surfaces of the first semiconductor chip 101 are formed.
In a specific embodiment, in the step (2), the etching process is a wet etching or a dry etching, the first groove 103 and the first groove extension 104 are formed in the same etching process by using a mask, and a depth of the first groove extension 104 is greater than a depth of the first groove 103. Thereby facilitating the formation of a thicker thermally conductive layer in the first recess extension 104.
In specific embodiments, the number of the first protrusions 102 arranged in parallel may be two, three or four, and further, the first groove extension 104 is located in a gap between adjacent first protrusions 102.
As shown in fig. 3, in step (3): then, the upper surface of each first protrusion 102 is etched to form a first bonding groove 105 on the upper surface of each first protrusion 102.
In a specific embodiment, in the step (3), the first bonding groove 105 is formed through a laser ablation process, and a ratio of a depth of the first bonding groove 105 to a thickness of the first protrusion 102 is 0.3 to 0.5.
In a more preferred embodiment, the ratio of the depth of the first coupling groove 105 to the thickness of the first protrusion 102 is 0.4.
As shown in fig. 4, said fig. 4 is a schematic cross-sectional view along a-a in fig. 2, in step (4): a first heat conducting layer 106 is then formed in the first recess 103 and said first recess extension 104, followed by a first heat insulating layer 107 formed on said first heat conducting layer 106.
In a specific embodiment, in the step (4), the material of the first thermal conductive layer 106 is one of copper, aluminum, silver, graphene and carbon nanotubes, and the material of the first thermal insulation layer 107 is one of silicon dioxide, epoxy resin, polystyrene, polyvinyl alcohol, polyethylene and polymethyl methacrylate.
In a specific embodiment, the first thermal conductive layer 106 may be specifically a metal copper layer and is further formed by an electroplating process, and the first thermal insulation layer 107 may be specifically a silicon dioxide layer and is further deposited on the first thermal conductive layer 106 by a PECVD process.
As shown in fig. 5, in step (5): a second carrier substrate 200 is provided, a second semiconductor chip 201 is arranged on the carrier substrate 200, and the active functional surface of the second semiconductor chip 201 faces the second carrier substrate 200.
In a specific embodiment, the second semiconductor chip 201 is bonded to the second carrier substrate 200.
As shown in fig. 6, in step (6): then, the second semiconductor chip 201 is etched, a plurality of second bumps 202 arranged in parallel are formed on four side surfaces of the second semiconductor chip 201, a second groove 203 is formed on the upper surface of the second semiconductor chip 201, and four second groove extensions 204 extending from the second groove 203 to the four side surfaces of the second semiconductor chip 201 are formed.
In a specific embodiment, in the step (6), the etching process is a wet etching or a dry etching, the second groove 203 and the second groove extension 204 are formed in the same etching process by using a mask, and a depth of the second groove extension 204 is greater than a depth of the second groove 203. Thereby facilitating the formation of a thicker thermally conductive layer in the second groove extension 204.
In a specific embodiment, the plurality of second protrusions 202 arranged in parallel are in one-to-one correspondence with the plurality of first protrusions 102 arranged in parallel, more specifically, the plurality of second protrusions 202 arranged in parallel may also be two, three, or four, and further, the second groove extension 204 is also located in a gap between adjacent second protrusions 202.
As shown in fig. 7, in step (7): then, the upper surface of each second bump 202 and the upper surface of the second semiconductor chip 201 are etched, so as to form a first bonding bump 205 on the upper surface of each second bump 202.
In a specific embodiment, in the step (7), the first bonding bump 205 is formed by a wet etching process.
In a more specific embodiment, in the step (7), a ratio of the height of the first bonding protrusion 205 to the depth of the first bonding groove 105 is 0.8-0.95, and more preferably, a ratio of the height of the first bonding protrusion 205 to the depth of the first bonding groove 105 is 0.9.
As shown in fig. 8, said fig. 8 is a schematic cross-sectional view along B-B in fig. 6, in step (8): a second heat conducting layer 206 is then formed in the second recess 203 and said second recess extension 204, and a second thermally insulating layer 207 is then formed on said second heat conducting layer 206.
In a specific embodiment, in the step (8), the material of the second thermal conductive layer 206 is one of copper, aluminum, silver, graphene and carbon nanotubes, and the material of the second thermal insulation layer 207 is one of silicon dioxide, epoxy resin, polystyrene, polyvinyl alcohol, polyethylene and polymethyl methacrylate.
In a specific embodiment, the second thermal conductive layer 206 may be a metal copper layer, and is further formed by an electroplating process, and the second thermal insulation layer 207 may be a silicon dioxide layer, and is further deposited on the second thermal conductive layer 206 by a PECVD process.
As shown in fig. 9, which is a schematic cross-sectional view along the first protrusion 102 in fig. 9, in step (9): the second semiconductor chip 201 is then bonded to the first semiconductor chip 101 such that the first bonding bumps 205 are embedded into the respective first bonding grooves 105, and then the second carrier substrate 200 is removed.
In a specific embodiment, the arrangement of the bonding structure can effectively improve the stability of the semiconductor stack package structure.
As shown in fig. 10, said fig. 10 is a schematic cross-sectional view along B-B, in step (10): next, a first encapsulation layer 301 is formed, the first encapsulation layer 301 wrapping the lower side of the first semiconductor chip 101, and then a first heat conduction member 302 is formed on the first encapsulation layer 301, the first heat conduction member 302 being embedded in a gap between adjacent first protrusions 102 to contact the first heat conduction layer 106.
In a specific embodiment, in the step (10), the first encapsulation layer 301 includes epoxy resin and a thermal conductive filler, and the material of the first thermal conductive member 302 is copper or aluminum.
In a more preferred embodiment, a through hole may be formed in the first package layer 301, so that the first heat conduction member 302 formed subsequently is exposed from the bottom surface of the first package layer 301, so as to facilitate rapid heat dissipation.
As shown in fig. 11, in step (11): next, a second heat insulating encapsulation layer 303 is formed, the second heat insulating encapsulation layer 303 covers the upper surface of the first heat conductive member 302, next, a second heat conductive member 304 is formed on the second heat insulating encapsulation layer 303, the second heat conductive member 304 is embedded into a gap between adjacent second protrusions 202 to contact the second heat conductive layer 206, next, a third encapsulation layer 305 is formed on the second heat insulating encapsulation layer 303, the third encapsulation layer 305 covers the second heat conductive member 304, and then, the first carrier substrate 100 is removed.
In a specific embodiment, in the step (11), the second thermal insulation packaging layer 303 is an epoxy resin layer, the second thermal conduction member 304 is made of copper or aluminum, and the third packaging layer 305 includes epoxy resin and a thermal conduction filler.
In a more preferred embodiment, the second thermal conduction member 304 has a portion embedded in the third encapsulation layer 305 and exposed from the upper surface of the third encapsulation layer 305, so as to facilitate rapid heat dissipation.
As shown in fig. 11, the present invention further provides a semiconductor package on package structure, which is formed by the above manufacturing method.
Compared with the prior art, the semiconductor stack packaging structure and the preparation method thereof have the following beneficial effects:
first, a plurality of first bumps arranged in parallel are respectively formed on four side surfaces of the first semiconductor chip, and a first bonding groove is formed on the upper surface of each first bump. And forming a plurality of second bumps arranged in parallel on four side surfaces of the second semiconductor chip, forming a first bonding bump on the upper surface of each second bump, and bonding the second semiconductor chip to the first semiconductor chip so that the first bonding bumps are embedded into the corresponding first bonding grooves. The arrangement of the structure can improve the bonding strength of the first semiconductor chip and the second semiconductor chip, and further can improve the stability of the semiconductor stack packaging structure.
Secondly, forming a first groove on the upper surface of the first semiconductor chip, forming four first groove extending parts respectively extending from the first groove to four side surfaces of the first semiconductor chip, then forming a first heat conduction layer on the first groove and the first groove extending parts, and then forming a first heat insulation layer on the first heat conduction layer; a second groove is formed on the upper surface of the second semiconductor chip, four second groove extending portions extending from the second groove to four side surfaces of the second semiconductor chip are formed, a second heat conduction layer is formed on the second groove and the second groove extending portions, and a second heat insulation layer is formed on the second heat conduction layer. The arrangement of the structure can facilitate the heat dissipation of each semiconductor chip on one hand and reduce the heat influence between the adjacent semiconductor chips on the other hand.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A preparation method of a semiconductor stack packaging structure is characterized by comprising the following steps: the method comprises the following steps:
step (1): providing a first carrier substrate, and arranging a first semiconductor chip on the carrier substrate, wherein an active functional surface of the first semiconductor chip faces the first carrier substrate;
step (2): then, etching the first semiconductor chip, forming a plurality of first bulges which are arranged in parallel on four side surfaces of the first semiconductor chip respectively, forming a first groove on the upper surface of the first semiconductor chip, and forming four first groove extending parts which extend from the first groove to the four side surfaces of the first semiconductor chip respectively;
and (3): etching the upper surface of each first protrusion to form a first bonding groove on the upper surface of each first protrusion;
and (4): then forming a first heat conducting layer in the first groove and the first groove extending part, and then forming a first heat insulating layer on the first heat conducting layer;
and (5): providing a second carrier substrate, and arranging a second semiconductor chip on the carrier substrate, wherein the active functional surface of the second semiconductor chip faces the second carrier substrate;
and (6): then, etching the second semiconductor chip, forming a plurality of second bulges which are arranged in parallel on four side surfaces of the second semiconductor chip respectively, forming a second groove on the upper surface of the second semiconductor chip, and forming four second groove extending parts which extend from the second groove to the four side surfaces of the second semiconductor chip respectively;
and (7): etching the upper surface of each second bump and the upper surface of the second semiconductor chip to form a first bonding bump on the upper surface of each second bump;
and (8): then forming a second heat conducting layer on the second groove and the second groove extending part, and then forming a second heat insulating layer on the second heat conducting layer;
and (9): then bonding the second semiconductor chip to the first semiconductor chip such that the first bonding bumps are embedded in the corresponding first bonding grooves;
step (10): then forming a first encapsulation layer that wraps around the underside of the first semiconductor chip, then forming a first heat-conducting member on the first encapsulation layer, the first heat-conducting member being embedded in a gap between adjacent first bumps to contact the first heat-conducting layer;
step (11): and then forming a second heat insulating encapsulation layer covering the upper surface of the first heat conductive member, then forming a second heat conductive member on the second heat insulating encapsulation layer, the second heat conductive member being embedded in a gap between adjacent second protrusions to contact the second heat conductive layer, then forming a third encapsulation layer on the second heat insulating encapsulation layer, the third encapsulation layer covering the second heat conductive member.
2. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the step (2), the etching process is a wet etching process or a dry etching process, and the first groove extension portion are formed in the same etching process by using a mask, wherein the depth of the first groove extension portion is greater than that of the first groove.
3. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the step (3), the first bonding groove is formed through a laser ablation process, and a ratio of a depth of the first bonding groove to a thickness of the first protrusion is 0.3-0.5.
4. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the steps (4) and (8), the first and second heat conduction layers are made of one of copper, aluminum, silver, graphene and carbon nanotubes, and the first and second heat insulation layers are made of one of silicon dioxide, epoxy resin, polystyrene, polyvinyl alcohol, polyethylene and polymethyl methacrylate.
5. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the step (6), the etching process is a wet etching process or a dry etching process, and the second groove extension portion are formed in the same etching process by using a mask, wherein the depth of the second groove extension portion is greater than that of the second groove.
6. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the step (7), a ratio of a height of the first bonding projection to a depth of the first bonding groove is 0.8 to 0.95.
7. The method of manufacturing a semiconductor package on package structure of claim 1, wherein: in the step (10), the first encapsulation layer includes an epoxy resin and a thermally conductive filler, and the material of the first thermally conductive member is copper or aluminum.
8. The method of manufacturing a semiconductor package on package structure of claim 7, wherein: in the step (11), the second heat insulating encapsulation layer is an epoxy resin layer, the second heat conducting member is made of copper or aluminum, and the third encapsulation layer includes epoxy resin and a heat conducting filler.
9. A semiconductor package on package structure formed by the method of any one of claims 1-8.
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| US10141391B2 (en) * | 2017-02-23 | 2018-11-27 | International Business Machines Corporation | Microstructure modulation for 3D bonded semiconductor containing an embedded resistor structure |
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| CN110494975A (en) * | 2017-05-16 | 2019-11-22 | 雷索恩公司 | Aoxidize the die package in the stacked wafer of engagement |
| CN112470270A (en) * | 2018-06-13 | 2021-03-09 | 伊文萨思粘合技术公司 | Offset pads on TSV |
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| US8314483B2 (en) * | 2009-01-26 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | On-chip heat spreader |
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| US10141391B2 (en) * | 2017-02-23 | 2018-11-27 | International Business Machines Corporation | Microstructure modulation for 3D bonded semiconductor containing an embedded resistor structure |
| CN110494975A (en) * | 2017-05-16 | 2019-11-22 | 雷索恩公司 | Aoxidize the die package in the stacked wafer of engagement |
| CN109285825A (en) * | 2017-07-21 | 2019-01-29 | 联华电子股份有限公司 | The manufacturing method of chip stack structure and die-stack structure |
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