CN219716861U

CN219716861U - Stacked chip packaging structure

Info

Publication number: CN219716861U
Application number: CN202321139600.7U
Authority: CN
Inventors: 陈一杲; 汤勇; 苏玉燕; 郑莹莹; 刘皓
Original assignee: Tianxin Electronic Technology Nanjing Co ltd
Current assignee: Tianxin Electronic Technology Nanjing Co ltd
Priority date: 2023-05-12
Filing date: 2023-05-12
Publication date: 2023-09-19
Anticipated expiration: 2033-05-12

Abstract

The utility model belongs to the technical field of chip packaging and manufacturing, and particularly relates to a stacked chip packaging structure, which comprises a substrate and a first chip, wherein the first chip is electrically connected with the substrate through a first bulge; the substrate is provided with a first bulge and a second bulge, the first bulge is arranged on the two sides of the first chip, and the upper surface of each first bulge is electrically connected with a first chip; each second chip is provided with a third chip, and each third chip is electrically connected with the substrate through a bonding wire; the chip packaging mode reduces the plane area of the chip packaging structure and the volume of the packaging structure, realizes the miniaturization of chip packaging, simultaneously, the first chip, the second chip and the third chip are respectively and independently connected with the substrate, and reduces the resistance value between the upper chip and the substrate, thereby reducing the power consumption.

Description

Stacked chip packaging structure

Technical Field

The utility model relates to the technical field of chip packaging and manufacturing, in particular to a stacked chip packaging structure.

Background

The stacked packaging chip is widely applied to the fields of mobile equipment, servers, artificial intelligence and the like, wherein the stacked chip packaging refers to stacking a plurality of chips together, and the chip interlayer connection technology is divided into wired connection and wireless connection; in the existing part of stacked chip packaging structure, a plurality of chips are paved on the same surface of a substrate, and the packaging mode enables the plane area of the packaging structure to be continuously increased along with the increase of the number of the chips; the packaging mode of arranging a plurality of chips on the substrate from bottom to top leads the resistance between the uppermost chip and the substrate to be overlarge, thereby affecting the efficiency of the packaging structure.

Disclosure of Invention

The utility model aims to provide a stacked chip packaging structure, which is used for solving the problem of the existing part of stacked chip packaging structure, and a plurality of chips are paved on the same surface of a substrate; the packaging mode of arranging a plurality of chips on the substrate from bottom to top leads to overlarge resistance value between the uppermost chip and the substrate, thereby influencing the efficiency of the packaging structure.

In order to achieve the above-mentioned objective, the present utility model provides a stacked chip package structure, which includes a substrate and a first chip, wherein a groove is formed on the substrate, a first bump is electrically connected in the groove, the first chip is disposed on an upper surface of the first bump, and the first chip is electrically connected with the substrate through the first bump;

the upper surface of the substrate is respectively provided with a second bulge at two sides of the first chip, the upper surface of each second bulge is respectively and electrically connected with a second chip, and the lower surface of each second chip is fixedly connected with the upper surface of the first chip;

and each second chip is respectively provided with a third chip, and each third chip is electrically connected with the substrate through a bonding wire.

Preferably, the upper surface of the first bump is provided with a first wiring layer, and the first chip is electrically connected with the substrate through the first wiring layer.

Preferably, the upper surface of each second bump is respectively provided with a second wiring layer, and the second chip is electrically connected with the second bumps through the second wiring layers.

Preferably, the first protrusion and the second protrusion are both ladder-shaped.

Preferably, at least one through groove is formed at two ends of the first protrusion and the second protrusion respectively.

Preferably, the grooves and the bottoms of the second protrusions are filled with heat-conducting glue.

Preferably, glue containing grooves are formed in two sides of the second protrusion.

Compared with the prior art, the utility model has the remarkable advantages that:

1. compared with the existing partial stacked chip packaging structure, the packaging mode enables the plane area of the packaging structure to be continuously increased along with the increase of the number of chips, and the mode that the second chip and the third chip are stacked on the first chip reduces the plane area of the chip packaging structure, reduces the volume of the packaging structure and achieves the miniaturization of chip packaging;

2. compared with the existing partial stacked chip packaging structure, which is formed by arranging a plurality of chips on a substrate from bottom to top, the resistance between the uppermost chip and the substrate is overlarge, so that the efficiency of the packaging structure is affected.

Drawings

FIG. 1 is a cross-sectional view of the present utility model;

fig. 2 is a schematic view of the structure of the first bump of the present utility model.

In the figure: the chip comprises a first chip 1, a second chip 2, a third chip 3, a groove 4, a first protrusion 5, a second protrusion 6, a substrate 7, a through groove 8, heat conducting glue 9, a first bonding member 10, a second bonding member 11, bonding wires 12 and a glue containing groove 13.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which are obtained by a person skilled in the art based on the described embodiments of the utility model, fall within the scope of protection of the utility model.

As shown in fig. 1, the utility model provides a stacked chip package structure, which comprises a substrate 7 and a first chip 1, wherein a groove 4 is formed on the substrate 7, a first protrusion 5 is electrically connected in the groove 4, the first chip 1 is arranged on the upper surface of the first protrusion 5, and the first chip 1 is electrically connected with the substrate 7 through the first protrusion 5; the upper surface of the substrate 7 and two sides of the first chip 1 are respectively provided with a second bulge 6, the upper surface of each second bulge 6 is respectively and electrically connected with a second chip 2, and the lower surface of each second chip 2 is fixedly connected with the upper surface of the first chip 1; each second chip 2 is provided with a third chip 3, and each third chip 3 is electrically connected with the substrate 7 through a bonding wire 12; compared with the existing partial chip packaging, the multi-chip tiling mode is adopted on the same horizontal plane on the substrate 7, so that the packaging area fluctuates along with the number of chips, and the larger the number of chips is, the larger the required use area is; meanwhile, compared with the prior partial chip packaging structure which stacks chips from bottom to top, the resistance value between the uppermost chip and the substrate 7 is larger, and meanwhile, the heat dissipation of the chips is also influenced, in the utility model, the mode of stacking the second chip 2 and the third chip 3 on the first chip 1 is adopted, the plane area of the chip packaging structure is reduced, the volume of the packaging structure is also reduced, and the miniaturization of the chip packaging is realized, meanwhile, in the utility model, the first chip 1 and the second chip 2 are respectively electrically connected with the substrate 7 through the first bulge 5 and the second bulge 6, and the third chip 3 is electrically connected with the substrate 7 through the bonding wire 12, so that the connection path between the chip and the substrate 7 is shortened, the resistance value is reduced, and the chip efficiency is improved; according to the utility model, the distance between the first chip 1, the second chip 2 and the substrate 7 is respectively increased by additionally arranging the first bulge 5 and the second bulge 6, and at least one through groove 8 is respectively formed at two ends of the first bulge 5 and the second bulge 6, so that the heat dissipation of the packaging structure is improved.

In one embodiment, a first adhesive member 10 is disposed between the first chip 1 and the first bump 5, so as to fix the first chip 1 to the upper surface of the first bump 5; the second chip 2 and the second bulge 6 are fixed through a second adhesive piece 11; the lower surface of the third chip 3 and the upper surface of the second chip 2 are fixed by a third adhesive piece; as an alternative embodiment in this case, the second adhesive layer is provided at a position where the second chip 2 contacts the upper surface of the second bump 6 and the upper surface of the first chip 1.

In one embodiment, the upper surface of the first bump 5 is provided with a first wiring layer, and the first chip 1 is electrically connected with the substrate 7 through the first wiring layer; the upper surface of each second bulge 6 is respectively provided with a second wiring layer, and the second chip 2 is electrically connected with the second bulge 6 through the second wiring layers; meanwhile, the first wiring layer and the second wiring layer are respectively arranged at two ends of the first bulge 5 and the second bulge 6, so that the first chip 1 and the second chip 2 are respectively electrically connected with the substrate 7.

As shown in fig. 2, in one embodiment, the first bump 5 and the second bump 6 are both ladder-shaped, but the shapes of the first bump 5 and the second bump 6 are not limited thereto, for example, the first bump 5 and the second bump 6 are configured as inverted concave shapes, so as to support and fix the first chip 1 and the second chip 2 respectively.

In one embodiment, the first bump 5 and the second bump 6 are made of bare silicon material, so that the heat generated by the chip is quickly transferred due to the high heat conduction efficiency of the bare silicon material, and the heat dissipation efficiency of the chip is improved.

In one embodiment, the heat conducting glue 9 is filled in the groove 4 and at the bottom of the second protrusion 6, so that heat dissipation of the chip is further realized.

In one embodiment, the two sides of the second protrusion 6 are provided with glue containing grooves 13, and when the heat conducting glue 9 is filled, the glue containing grooves 13 can effectively prevent the heat conducting glue 9 from overflowing.

It will be evident to those skilled in the art that the utility model is not limited to the details of the foregoing illustrative embodiments, and that the present utility model may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. The utility model provides a stacked chip packaging structure, includes base plate (7) and first chip (1), its characterized in that: the substrate (7) is provided with a groove (4), a first bulge (5) is electrically connected in the groove (4), the first chip (1) is arranged on the upper surface of the first bulge (5), and the first chip (1) is electrically connected with the substrate (7) through the first bulge (5);

the upper surface of the substrate (7) is provided with a second bulge (6) respectively positioned at two sides of the first chip (1), the upper surface of each second bulge (6) is electrically connected with a second chip (2) respectively, and the lower surface of each second chip (2) is fixedly connected with the upper surface of the first chip (1);

each second chip (2) is provided with a third chip (3), and each third chip (3) is electrically connected with the substrate (7) through bonding wires (12).

2. The stacked chip package structure of claim 1, wherein: the upper surface of the first bulge (5) is provided with a first wiring layer, and the first chip (1) is electrically connected with the substrate (7) through the first wiring layer.

3. The stacked chip package structure of claim 1, wherein: the upper surface of each second bulge (6) is respectively provided with a second wiring layer, and the second chip (2) is electrically connected with the second bulge (6) through the second wiring layers.

4. The stacked chip package structure of claim 1, wherein: the first bulge (5) and the second bulge (6) are ladder-shaped.

5. The stacked chip package structure of claim 4, wherein: at least one through groove (8) is formed in two ends of the first bulge (5) and the second bulge (6) respectively.

6. The stacked chip package structure of claim 1, wherein: and heat conducting glue (9) is filled in the grooves (4) and at the bottoms of the second bulges (6).

7. The stacked chip package structure of claim 1, wherein: glue containing grooves (13) are formed in two sides of the second bulge (6).