JP2007287944A - Pop用の半導体装置の製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 129
- 239000011347 resin Substances 0.000 claims abstract description 79
- 229920005989 resin Polymers 0.000 claims abstract description 79
- 239000000919 ceramic Substances 0.000 claims description 35
- 239000007788 liquid Substances 0.000 claims description 33
- 238000000465 moulding Methods 0.000 claims description 21
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- 239000010949 copper Substances 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 11
- 229910000831 Steel Inorganic materials 0.000 description 5
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- 229920006362 Teflon® Polymers 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
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- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
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- 239000004416 thermosoftening plastic Substances 0.000 description 1
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
【解決手段】 半導体装置の製造方法は、表面に複数の半導体チップ410と複数の半導体チップに供給された液状樹脂434とを含む基板400を、電気的に絶縁されるように下部金型200により支持させる。複数の型形成部(キャビティ)112が形成された上部金型110を可撓性リリースフィルム300を介して下部金型200に対して押圧し、基板上の液状樹脂434をモールドする。
【選択図】 図1
Description
110:上部金型
112:キャビティ
114:押圧部材
116:バネ
118:脚部
120:吸気孔
200:下部金型
210:金型本体
220:セラミックプレート
230:オーリング
240:吸気孔
300:リリースフィルム
310、320:リール
400:多層配線基板
402:ダイアタッチ
404:銅パターン
406:ランド
408:銅パターン
409:ビアコンタクト
410:半導体チップ
420:ボンディングワイヤ
430:供給部
432:ノズル
434:液状樹脂
Claims (27)
- 基板上に搭載された複数の半導体素子に供給された樹脂をモールドするための半導体製造装置であって、
複数の半導体素子が搭載された基板を支持する下部金型と、
可撓性フィルムを介して基板上の複数の半導体素子の樹脂をモールドする上部金型とを含み、
前記下部金型は、電気的絶縁領域を含み、当該電気的絶縁領域を介して前記基板を支持する、半導体製造装置。 - 前記電気的絶縁領域は、セラミック部材を含む、請求項1に記載の半導体製造装置。
- 前記セラミック部材は、下部金型に取り付けられたセラミックプレートである、請求項2に記載の半導体製造装置。
- 前記セラミックプレートは、下部金型に形成された空洞内に収容される、請求項3に記載の半導体製造装置。
- 前記電気的絶縁領域は、下部金型上に配された絶縁フィルムを含む、請求項1に記載の半導体製造装置。
- 前記絶縁フィルムは、下部金型の表面に接着剤を介して取り付けられる、請求項5に記載の半導体製造装置。
- 前記電気的絶縁領域は、載置される基板の面積よりも大きい、請求項1ないし6いずれか1つに記載の半導体製造装置。
- 前記下部金型は、前記電気的絶縁領域を取り囲むようにシール部材を含み、前記シール部材は上部金型に接圧される、請求項1に記載の半導体製造装置。
- 前記下部金型は、前記シール部材に囲まれた領域内に複数の吸気孔を含み、前記複数の吸気孔からの吸気により真空状態で樹脂をモールドする、請求項8に記載の半導体製造装置。
- 前記上部金型は、基板上に搭載された複数の半導体素子に対応する複数の凹部と、前記可撓性フィルムを前記複数の凹部に密着させるための吸着孔とを含む、請求項1に記載の半導体製造装置。
- 前記基板は、半導体素子を搭載する第1の主面と、第1の主面に対向する第2の主面を含み、第1の主面に露出された第1の導電性領域を含み、第1の導電性領域は、半導体素子に電気的に接続されている、請求項1に記載の半導体製造装置。
- 前記第1の導電性領域は、モールドされる樹脂よりも外側において露出されている、請求項11に記載の半導体製造装置。
- 前記基板は、第2の主面に露出された第2の導電性領域を含み、第2の導電性領域は、第1の導電性領域または半導体素子に電気的に接続されている、請求項11または12に記載の半導体製造装置。
- 前記基板は、多層配線基板である、請求項1ないし13いずれか1つに記載の半導体製造装置。
- 前記可撓性フィルムは、高分子フィルムである、請求項1に記載の半導体製造装置。
- 第1の主面および第1の主面に対向する第2の主面を含む基板であって、第1の主面上において半導体素子が樹脂モールドされた半導体装置を製造するための製造方法であって、
第1の主面上に複数の半導体素子および複数の半導体素子に供給された液状樹脂を含む基板を、第2の主面が電気的に絶縁されるように下部金型により支持し、
複数の型形成部が形成された上部金型を可撓性フィルムを介して下部金型に対して押圧し、前記複数の型形成部により基板上の液状樹脂をモールドする、
ステップを含む製造方法。 - 前記下部金型は、セラミック部材を含み、前記基板の第2の主面がセラミック部材上に載置される、請求項16に記載の製造方法。
- 前記下部金型は、絶縁フィルムを含み、前記基板の第2の主面が絶縁フィルム上に載置される、請求項16に記載の製造方法。
- 前記セラミック部材または前記絶縁フィルムは、基板の第2の主面よりも大きな載置面を有する、請求項17または18に記載の製造方法。
- 可撓性フィルムは、上部金型に形成された吸気孔から吸気することにより複数の型形成部に吸着される、請求項16に記載の製造方法。
- 前記基板は、第1の主面に露出された第1の導電性領域を含み、第1の導電性領域は、半導体素子に電気的に接続されている、請求項15に記載の製造方法。
- 前記第1の導電性領域は、モールドされる樹脂よりも外側において露出されている、請求項21に記載の半導体製造装置。
- 前記基板は、第2の主面に露出された第2の導電性領域を含み、第2の導電性領域は、第1の導電性領域または半導体素子に電気的に接続されている、請求項21または22に記載の製造方法。
- 前記基板は、多層配線基板である、請求項16ないし23いずれか1つに記載の製造方法。
- 前記製造方法はさらに、上部金型を下部金型から離脱するステップと、基板を個々の半導体素子に切断するステップとを有する、請求項16ないし24いずれか1つに記載の製造方法。
- 前記製造方法はさらに、基板の第2の主面に露出した第2の導電性領域に端子を接続するステップを含む、請求項16ないし25いずれか1つに記載の製造方法。
- 前記製造方法はさらに、基板の第1の主面に露出した第1の導電性領域に、他の半導体装置の端子を積層するステップを含む、請求項16ないし26いずれか1つ記載の製造方法。
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011124319A (ja) * | 2009-12-09 | 2011-06-23 | Renesas Electronics Corp | 半導体パッケージ製造装置及び半導体パッケージの製造方法 |
CN104742293A (zh) * | 2013-12-27 | 2015-07-01 | 东和株式会社 | 树脂成型装置及树脂成型方法 |
KR101545194B1 (ko) * | 2015-03-26 | 2015-08-19 | 김기열 | 반도체 패키지용 몰딩 다이 및 그 제조방법 |
JP2016168688A (ja) * | 2015-03-11 | 2016-09-23 | 住友ベークライト株式会社 | 離型フィルム |
JP6467488B1 (ja) * | 2017-11-29 | 2019-02-13 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP2020098887A (ja) * | 2018-12-19 | 2020-06-25 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP2020107621A (ja) * | 2018-12-26 | 2020-07-09 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
WO2021241116A1 (ja) * | 2020-05-25 | 2021-12-02 | Towa株式会社 | 樹脂成形装置、カバープレート及び樹脂成形品の製造方法 |
CN115084059A (zh) * | 2022-08-16 | 2022-09-20 | 杭州飞仕得科技有限公司 | 一种绝缘基板的制备方法及功率器件封装方法 |
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2006
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011124319A (ja) * | 2009-12-09 | 2011-06-23 | Renesas Electronics Corp | 半導体パッケージ製造装置及び半導体パッケージの製造方法 |
CN104742293A (zh) * | 2013-12-27 | 2015-07-01 | 东和株式会社 | 树脂成型装置及树脂成型方法 |
CN104742293B (zh) * | 2013-12-27 | 2017-05-10 | 东和株式会社 | 树脂成型装置及树脂成型方法 |
JP2016168688A (ja) * | 2015-03-11 | 2016-09-23 | 住友ベークライト株式会社 | 離型フィルム |
KR101545194B1 (ko) * | 2015-03-26 | 2015-08-19 | 김기열 | 반도체 패키지용 몰딩 다이 및 그 제조방법 |
WO2019107137A1 (ja) * | 2017-11-29 | 2019-06-06 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP6467488B1 (ja) * | 2017-11-29 | 2019-02-13 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP2019102551A (ja) * | 2017-11-29 | 2019-06-24 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP2020098887A (ja) * | 2018-12-19 | 2020-06-25 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
JP2020107621A (ja) * | 2018-12-26 | 2020-07-09 | アサヒ・エンジニアリング株式会社 | 電子部品の実装装置 |
WO2021241116A1 (ja) * | 2020-05-25 | 2021-12-02 | Towa株式会社 | 樹脂成形装置、カバープレート及び樹脂成形品の製造方法 |
TWI796685B (zh) * | 2020-05-25 | 2023-03-21 | 日商Towa股份有限公司 | 樹脂成形裝置、蓋板及樹脂成形品的製造方法 |
CN115084059A (zh) * | 2022-08-16 | 2022-09-20 | 杭州飞仕得科技有限公司 | 一种绝缘基板的制备方法及功率器件封装方法 |
CN115084059B (zh) * | 2022-08-16 | 2022-12-02 | 杭州飞仕得科技有限公司 | 一种绝缘基板的制备方法及功率器件封装方法 |
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