JP2007286155A - Plasma display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in a plasma display with a large screen, since current path lengths from the sustaining voltage output ends of a driving circuit to electrodes are different from each other, display property becomes uneven at the top and bottom parts and the center part of the screen. <P>SOLUTION: In the plasma display, threaded terminals of a driving circuit arranged at the right and left sides and performing sustaining discharge are arranged at different positions with the longitudinal direction of a panel as a reference, or sustaining switch elements on a high side and sustaining switch elements on a low side are arranged separately in an upper portion and in a lower portion to make the position line-symmetric between a left-side circuit and a right-side circuit. As a result, difference in the current path length of each electrode becomes smaller, and light emission property becomes even and display quality is improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display used for a wall-mounted television or a large monitor.

  An AC surface discharge type plasma display panel (hereinafter abbreviated as “PDP”) representative of an AC type includes a front plate made of a glass substrate formed by arranging scan electrodes and sustain electrodes for performing surface discharge, and data electrodes. And a back plate made of a glass substrate formed by arranging the electrodes in parallel so as to form a discharge space in the gap so that both electrodes form a matrix, and the outer periphery thereof is a sealing material such as glass frit It is comprised by sealing by. Discharge cells partitioned by barrier ribs are provided between both the front and back substrates, and a phosphor layer is formed in the cell space between the barrier ribs. In the PDP having such a configuration, ultraviolet light is generated by gas discharge, and phosphors of each color of red (R), green (G), and blue (B) are excited by the ultraviolet light to emit light, thereby performing color display. Is going.

  FIG. 11 is a perspective view showing the structure of the PDP 10. On the glass front plate 20 which is the first substrate, a plurality of display electrodes which are paired with a stripe-shaped scan electrode 22 and a stripe-shaped sustain electrode 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24.

  A plurality of stripe-shaped data electrodes 32 covered with a dielectric layer 33 are formed on the back plate 30 as the second substrate so as to three-dimensionally intersect the scan electrodes 22 and the sustain electrodes 23. A plurality of barrier ribs 34 are disposed on the dielectric layer 33 in parallel with the data electrodes 32, and a phosphor layer 35 is provided on the dielectric layer 33 between the barrier ribs 34. Further, the data electrode 32 is disposed at a position between the adjacent partition walls 34.

  The front plate 20 and the back plate 30 are arranged to face each other with a minute discharge space so that the scan electrode 22, the sustain electrode 23, and the data electrode 32 are orthogonal to each other, and the outer peripheral portion thereof is made of glass frit or the like. It is sealed with a sealing material. In the discharge space, for example, a mixed gas of neon (Ne) and xenon (Xe) is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and phosphor layers 35 that emit red (R), green (G), and blue (B) light are sequentially disposed in each section. A discharge cell is formed at a portion where the scan electrode 22 and the sustain electrode 23 intersect with the data electrode 32, and one adjacent pixel is formed by three adjacent discharge cells on which the phosphor layers 35 that emit light of each color are formed. The An area where the discharge cells constituting this pixel are formed becomes an image display area, and the periphery of the image display area becomes a non-display area where image display is not performed, such as an area where glass frit is formed.

  FIG. 12 is an electrode array diagram of the PDP 10. N rows of scan electrodes SC1 to SCn (scan electrode 22 in FIG. 11) and n rows of sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 11) are alternately arranged in the row direction, and m columns in the column direction. Data electrodes D1 to Dm (data electrode 32 in FIG. 11) are arranged. Discharge cells Ci, j including a pair of scan electrodes SCi, sustain electrodes SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) are formed in the discharge space, and the discharge cell C The total number of is (m × n).

  In the PDP 10 having such a configuration, color display is performed by generating ultraviolet rays by gas discharge and exciting the phosphors of R, G, and B colors with the ultraviolet rays to emit light. Further, the PDP 10 divides one field period into a plurality of subfields, and performs gradation display by being driven by a combination of subfields that emit light. Each subfield includes an initialization period, an address period, and a sustain period. In order to display image data, different signal waveforms are applied to the respective electrodes in the initialization period, the address period, and the sustain period.

  FIG. 13 is a diagram illustrating each drive voltage waveform applied to each electrode of the PDP 10. As shown in FIG. 13, each subfield has an initialization period, an address period, and a sustain period. Each subfield performs substantially the same operation except that the number of sustain pulses in the sustain period is changed in order to change the weight of the light emission period, and the operation principle in each subfield is also substantially the same. The operation will be described for only one subfield.

  First, in the initialization period, for example, a positive pulse voltage is applied to all the scan electrodes SC1 to SCn, and the protective layer 25 and the phosphor on the dielectric layer 24 covering the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn. The necessary wall charge is accumulated on the layer 35. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing the discharge delay and generating the address discharge stably.

  Specifically, in the first half of the initialization period, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and the scan electrodes SC1 to SCn are discharged to the data electrodes D1 to Dm. A ramp waveform voltage that gently rises from a voltage Vi1 equal to or lower than the start voltage toward a voltage Vi2 that exceeds the discharge start voltage is applied. While this ramp waveform voltage rises, the first weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode.

  In the latter half of the initialization period, sustain electrodes SU1 to SUn are kept at positive voltage Ve, and scan electrodes SC1 to SCn have a voltage exceeding discharge start voltage from voltage Vi3 that is lower than discharge start voltage with respect to sustain electrodes SU1 to SUn. A ramp waveform voltage that gently falls toward Vi4 is applied. During this time, a second weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The This completes the initialization operation (hereinafter, the drive voltage waveform applied to each electrode during the initialization period is abbreviated as “initialization waveform”).

  Next, in the address period, scanning is performed by sequentially applying negative scan pulses to all the scan electrodes SC1 to SCn. Then, while scanning the scan electrodes SC1 to SCn, a positive address pulse voltage is applied to the data electrodes D1 to Dm based on the display data. Thus, address discharge is generated between scan electrodes SC1 to SCn and data electrodes D1 to Dm, and wall charges are formed on the surface of protective layer 25 on scan electrodes SC1 to SCn.

  Specifically, in the address period, scan electrodes SC1 to SCn are temporarily held at voltage Vscn. Next, in the address operation of the discharge cells Cp, 1 to Cp, m (p is an integer of 1 to n), the scan pulse voltage −Vad is applied to the scan electrode SCp, and the pth row of the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to the data electrode Dq (Dq is a data electrode selected based on the video signal among D1 to Dm) corresponding to the video signal to be displayed. Thus, an address discharge is generated in the discharge cells Cp, q corresponding to the intersection between the data electrode Dq to which the address pulse voltage is applied and the scan electrode SCP to which the scan pulse voltage is applied. By this address discharge, a positive voltage is accumulated on the scan electrode SCp of the discharge cells Cp, q, a negative voltage is accumulated on the sustain electrode SUp, and the address operation is completed. Thereafter, the same address operation is performed until the discharge cells Cn, q in the n-th row, and the address operation is completed.

  In the subsequent sustain period, a voltage sufficient to maintain the discharge is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn for a certain period. Accordingly, discharge plasma is generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the phosphor layer is excited and emitted for a certain period. At this time, in the discharge space where the address pulse voltage is not applied in the address period, no discharge occurs and excitation light emission of the phosphor layer 35 does not occur.

  Specifically, in the sustain period, scan electrodes SC1 to SCn are once returned to 0 (V), and then sustain electrodes SU1 to SUn are returned to 0 (V). Thereafter, positive sustain pulse voltage Vsus is applied to scan electrodes SC1 to SCn. At this time, the voltage between scan electrode SCp and sustain electrode SUp above discharge cell Cp, q in which address discharge has occurred is in addition to positive sustain pulse voltage Vsus, and scan electrode SCp above and sustain electrode in the address period. The wall voltage accumulated in the upper part of the SUp is added and becomes larger than the discharge start voltage, and the first sustain discharge is generated. In discharge cells Cp and q that have undergone sustain discharge, a negative voltage is accumulated on scan electrode SCp so as to cancel the potential difference between scan electrode SCP and sustain electrode SUp at the time of occurrence of sustain discharge, and positive voltage is applied on sustain electrode SUp. Voltage is accumulated. Thus, the first sustain discharge is completed. After the first sustain discharge, scan electrodes SC1 to SCn are returned to 0 (V), and then Vsus is applied to sustain electrodes SU1 to SUn. At this time, the voltage between the upper portion of the scan electrode SCp and the upper portion of the sustain electrode SUp in the discharge cells Cp, q in which the first sustain discharge has occurred is scanned in the first sustain discharge in addition to the positive sustain pulse voltage Vsus. The wall voltage accumulated in the upper part of the electrode SCp and the upper part of the sustain electrode SUp is added and becomes larger than the discharge start voltage, and the second sustain discharge is generated. In the same manner, by applying sustain pulses alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, sustain discharge continues for the number of sustain pulses for discharge cells Cp and q in which address discharge has occurred. Done.

  FIG. 14 is a block diagram showing an electrical configuration of a plasma display in which the PDP 10 is incorporated. The plasma display shown in FIG. 14 includes an AD converter 1, a video signal processing circuit 2, a subfield processing circuit 3, a data electrode drive circuit 4, a scan electrode drive circuit 5, a sustain electrode drive circuit 6, and a PDP 10.

  The AD converter 1 converts the input analog video signal into a digital video signal. The video signal processing circuit 2 emits and displays the input digital video signal on the PDP 10 by a combination of a plurality of subfields having different light emission period weights, and controls each subfield from the video signal of one field. Convert to data.

  The subfield processing circuit 3 generates a data electrode drive circuit control signal, a scan electrode drive circuit control signal, and a sustain electrode drive circuit control signal from the subfield data created by the video signal processing circuit 2, and drives the data electrode Output to the circuit 4, the scan electrode drive circuit 5, and the sustain electrode drive circuit 6, respectively.

  In the PDP 10, as described above, n rows of scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 11) and n rows of sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 11) are alternately arranged. M columns of data electrodes D1 to Dm (data electrodes 32 in FIG. 11) are arranged in the column direction. Then, (m × n) discharge cells Ci, j including a pair of scan electrodes SCi, sustain electrodes SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) are included in the discharge space. One pixel is formed by three discharge cells that are formed and emit light in red, green, and blue colors.

  The data electrode drive circuit 4 drives each data electrode Dj independently based on the data electrode drive circuit control signal.

  Scan electrode drive circuit 5 can drive each of scan electrodes SC1 to SCn independently. Then, each of the scan electrodes SC1 to SCn is independently driven based on the scan electrode drive circuit control signal.

  Sustain electrode drive circuit 6 can drive all sustain electrodes SU1 to SUn of PDP 10 together. Then, sustain electrodes SU1 to SUn are driven based on the sustain electrode drive circuit control signal.

  A specific circuit configuration of a plasma display panel driving circuit for applying such a driving voltage is shown in FIG. Scan electrode drive circuit 5 includes sustain circuit 51, initialization circuit 52, write circuit 53, and recovery circuit 54.

  The sustain circuit 51 includes a first high-side sustain switch element S5, a first low-side sustain switch element S6, and a voltage source V1 having a voltage value Vsus. The recovery circuit 54 includes a first inductor L1, a first recovery capacitor C1, a first high side recovery switch element S1, a first low side recovery switch element S2, a first high side recovery diode D1, and a first low side. And a recovery diode D2. The recovery circuit 54 recovers and supplies power by performing LC resonance between the capacitive load of the PDP 10 (capacitive load generated in the scan electrodes SC1 to SCn) and the first inductor L1. At the time of power recovery, the power stored in the capacitive load generated in scan electrodes SC1 to SCn is moved to first recovery capacitor C1 via first low-side recovery diode D2 and first low-side recovery switch element S2. Let When power is supplied, the power stored in the first recovery capacitor C1 is moved to the PDP 10 (scan electrodes SC1 to SCn) via the first high-side recovery switch element S1 and the first high-side recovery diode D1. . Thus, scan electrodes SC1 to SCn are driven in the sustain period. Therefore, since the recovery circuit 54 drives the scan electrodes SC1 to SCn by LC resonance without supplying power from the power source in the sustain period, the power consumption is theoretically zero.

  On the other hand, sustain circuit 51 supplies power to scan electrodes SC1 to SCn from voltage source V1 having voltage value Vsus via first high-side sustain switch element S5, and clamps scan electrodes SC1 to SCn to voltage value Vsus. Further, the scan electrodes SC1 to SCn are driven by clamping the scan electrodes SC1 to SCn to the ground potential via the first low-side sustain switch element S6. Accordingly, when scan electrodes SC1 to SCn are driven by sustain circuit 51, the power supply impedance is very small, and the rise and fall of the sustain pulse are steep, but power consumption occurs due to the supply of power from the power supply. To do.

  Thus, sustain circuit 51 and recovery circuit 54 switch the operation of power recovery and voltage clamp by switching each switch element S1, S2, S5, S6, and generate a sustain pulse to be applied to scan electrodes SC1 to SCn. . At this time, the recovery circuit 54 using the LC resonance supplies power until the sustain pulse voltage reaches a maximum value, and then switches to the voltage clamp operation of the sustain circuit 51 to drive the power recovery to the maximum. Thus, the power consumption of the scan electrode driving circuit 5 can be reduced.

  Each of the switch elements S1, S2, S5, and S6 is a generally known element that performs a switch operation such as a MOSFET. A MOSFET is generally a parasitic diode called a body diode (a diode generated parasitically in the MOSFET structure) in parallel to the part that performs the switching operation, and the anode and cathode that are opposite to the part that performs the switching operation. (Hereinafter, such a configuration is referred to as “reverse parallel”). For this reason, the switch element can flow a forward current with respect to the body diode even when the switch operation is cut off. These switch elements may be provided with an antiparallel diode separately by using an element that performs a switch operation such as an IGBT instead of a MOSFET.

  The initialization circuit 52 is formed of a generally known element that performs a switching operation such as a MOSFET or an IGBT. A high-side initialization switch element S11, a low-side initialization switch element S12, a first separation switch element S9, a second separation switch element S10, a voltage source V3 having a voltage value Vset, and a voltage source V2 having a negative voltage value −Vad have. Then, power is supplied from voltage source V3 to scan electrodes SC1 to SCn via high-side initialization switch element S11, and negative voltage is applied to scan electrodes SC1 to SCn from voltage source V2 via low-side initialization switch element S12. Electric power to be a potential is supplied to generate an initialization waveform. The second separation switch element S10 is connected to the main discharge path from the voltage source V3 when the high-side initialization switch element S11 is conducting (hereinafter, abbreviated as “on” to make the switch element conducting). (Maintenance circuit 51, initialization circuit 52, write circuit 53, recovery circuit 54, and write voltage generation circuit 55 are connected in common, and the power supplied to scan electrodes SC1 to SCn and the recovered power from scan electrodes SC1 to SCn are Current is prevented from flowing into the voltage source V1 through the body diode of the first sustain switch element S5 (in the case of IGBT, a diode connected in antiparallel) through the flow path). That is, the second separation switch element S10 is arranged to cut off the current as described above (hereinafter abbreviated as “off” to cut off the switch element), and the high-side initialization switch element S11 becomes conductive. During this period, the second separation switch element S10 is turned off. Similarly, the first separation switch element S9 passes through the body diode of the first low-side sustain switch element S6 when the low-side initialization switch element S12 is on, and then goes from the ground potential to the voltage source V2 through the discharge path. Prevent current from flowing in. That is, the first separation switch element S9 is arranged to turn off the current as described above, and the first separation switch element S9 is turned off while the low-side initialization switch element S12 is conducting.

  Thus, the initialization circuit 52 generates an initialization waveform as shown in FIG. In the first half of the initialization period, a ramp waveform that gently rises from the voltage Vi1 below the discharge start voltage to the voltage Vi2 exceeding the discharge start voltage, that is, Vset, is generated for the data electrodes D1 to Dm. In the second half, a sustain waveform SU1 to SUn is generated with a ramp waveform that gently falls from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage, that is, toward −Vad.

  The write circuit 53 has two input ports, IC1 that is a scan driver that generates a scan pulse waveform by outputting any one of the powers input to the two input ports by a switch operation, and a voltage value Vscn. The voltage source V4 is connected to one end of the input of the scan driver IC1. In the address period, scanning is performed by sequentially applying a negative scan pulse to all the scan electrodes SC1 to SCn. For this purpose, the low-side initialization switch element S12 of the initialization circuit 52 is turned on, and the negative voltage value −Vad power is input from the voltage source V2 to the other input port of the scan driver IC1. Then, either one of the power supplied from the voltage source V4 and the power supplied from the voltage source V2 is selected by the scan driver IC1 and supplied to the scan electrodes SC1 to SCn. That is, the scan driver IC1 performs a switching operation so as to supply the power from the voltage source V2 to the scan electrodes SC1 to SCn at the timing of applying the negative scan pulse and at other times the power from the voltage source V4.

  In order to electrically isolate sustain circuit 51 from initialization circuit 52 as described above, first separation switch element S9 and second separation switch are provided between maintenance circuit 51 and initialization circuit 52. The element S10 is inserted in series and the body diodes are placed in opposite directions (hereinafter referred to as “back-to-back connection”). With this configuration, if the first separation switch S9 and the second separation switch S10 are simultaneously turned off, the high-side initialization switch element S11 and the low-side initialization switch of the initialization circuit 52 to the maintenance circuit 51 are switched. Any of the current flowing to the element S12 and the current flowing from the high-side initialization switch element S11 and the low-side initialization switch element S12 of the initialization circuit 52 to the sustain circuit 51 can be cut off.

  This is for preventing the influence of the voltage source V1 of the sustain circuit 51 having a lower potential when the power is supplied from the voltage source V3 of the initialization circuit 52. This is for preventing the influence of a higher potential, that is, the ground potential (hereinafter abbreviated as “GND”) of the clamp portion of the sustain circuit 51, when power is supplied from the voltage source V2.

  When power is supplied from the voltage source V3, current may flow from the voltage source V3 having the voltage value Vset to the voltage source V1 having a lower potential through the main discharge path. In such a case, the potential of the main discharge path Becomes lower than the potential Vset of the voltage source V3, and it becomes difficult to generate the original drive voltage waveform. Further, when power is supplied from the voltage source V2 having a negative voltage value −Vad, current may flow from the GND of the clamp unit having a higher potential than the voltage source V2 to the voltage source V2 via the main discharge path. In this case, the potential of the main discharge path rises higher than the negative voltage value −Vad of the voltage source V2, and it becomes difficult to generate the original drive voltage waveform.

  However, in the initialization period in which the scan electrodes SC1 to SCn are driven by the initialization circuit 52, the first separation switch S9 and the second separation switch S10 are turned off, so that the maintenance circuit 51 is initialized. The voltage source V2 and the voltage source V3 can be electrically separated from each other, and such a current flow can be cut off. Therefore, the first separation switch element S9 and the second separation switch S10 are turned on only during the period in which the sustain electrodes 51 drive the scan electrodes SC1 to SCn, and are turned off during other initialization periods.

  During the period in which scan electrodes SC1 to SCn are driven by sustain circuit 51, voltage source V2 and voltage source V3 are connected to the main discharge path by turning off high-side initialization switch element S11 and low-side initialization switch element S12. It can be electrically separated from. This is because the high-side initialization switch element S11 is arranged so that the voltage source V3 has a higher potential than the voltage source V1, and the body diode blocks the current flowing from the voltage source V3 to the main discharge path. This is also because the low-side initialization switch element S12 is arranged so that the voltage source V2 has a potential lower than GND and the body diode blocks the current flowing from the main discharge path to the voltage source V2.

  Note that the sustain electrode drive circuit 6 also has the same sustain circuit and recovery circuit as the scan electrode drive circuit 5. That is, the second recovery inductor L2, the second recovery capacitor C2, the second high-side recovery switch element S3, the second low-side recovery switch element S4, the second high-side recovery diode D3, the second low-side recovery diode And a recovery circuit including a second high-side sustain switch element, a second low-side sustain switch element S8, and a voltage source V1 having a voltage value Vsus, and a capacitive load (sustain electrode) of the PDP 10 (Capacitive load generated in SU1 to SUn) and the inductance of the second inductor L2 are made to resonate, and the power is recovered in the second recovery capacitor C2. The operation is the maintenance circuit 51 and the recovery circuit. The description is omitted because it is the same as 54.

  The arrangement of each circuit will be described with reference to FIG. FIG. 16 is a plan view showing an example of the arrangement of a conventional plasma display viewed from the back side.

  A flexible wiring board 21 as a display electrode wiring member connected to the electrode lead portions of the scan electrode 22 and the sustain electrode 23 is provided on both side edges of the PDP 10, and is routed to the back side through the outer peripheral portion of the chassis member 26. Is done. The flexible wiring board 21 connected to the scan electrode 22 is connected to the writing circuit 53 of the scan electrode driving circuit 5, and the flexible wiring board 21 connected to the sustain electrode 23 is connected to the sustain electrode driving circuit 6.

  On the other hand, the lower and upper edges of the PDP 10 are provided with a flexible wiring board 31 as a data electrode wiring member connected to the electrode lead-out portion of the data electrode 32, and the flexible wiring board 31 is a data electrode driving circuit. 4 are electrically connected to a plurality of data drivers (not shown), routed to the back side through the outer periphery of the chassis member 26, and disposed at the lower and upper positions on the back side of the chassis member 26. The data electrode drive circuit 4 is connected.

  As shown in FIG. 13, the subfield processing circuit 3 is electrically connected to the respective drive circuits to supply signals to the data electrode drive circuit 4, the scan electrode drive circuit 5, and the sustain electrode drive circuit 6. . Note that the power supply circuit, AD converter 1, and video signal processing circuit 2 for driving each drive circuit are not shown in the plan view of FIG. The AD converter 1 and the video signal processing circuit 2 may be included in the circuit board of the subfield processing circuit 3.

  Scan electrode drive circuit 5 and sustain electrode drive circuit 6 in the plasma display described above are electrically connected to the screw holes at the ground potential of each circuit. Each circuit is fastened to the chassis member 26 with a conductive screw through a screw hole. Accordingly, the discharge current flowing during the sustain period flows between the screw of each circuit and the chassis member 26. That is, the first high-side sustain switch element S5 of the scan electrode drive circuit 5 is turned on to maintain the sustain voltage Vsus on the scan electrode 22, and the second low-side sustain switch element S8 of the sustain electrode drive circuit 6 is turned on and maintained. When supplying a ground potential to each of the electrodes 23 to cause a discharge current to flow, scanning is performed from the voltage source V1 that supplies the virtual sustain voltage Vsus of the scan electrode driving circuit 5 via each switch element S5, S9, S10, and IC1. A current flows through the electrode 22, a current flows through the sustain electrode 23 by discharge, and then flows from the screw of the sustain electrode drive circuit 6 to the chassis member 26 through the switch element S 8 of the sustain electrode drive circuit 6. Thereafter, a closed circuit is formed in which it flows from the chassis member 26 to the voltage source V <b> 1 via the screw of the scan electrode driving circuit 5. Therefore, the discharge current flows through the screws that fasten the chassis member and each circuit.

  Therefore, when the inductance of the chassis member or the discharge path is large, the voltage applied to the scan electrode 22 and the sustain electrode 23 may be distorted due to the influence of the inductance. In particular, since the discharge current is large and is a pulsed current mainly including a frequency of about several megahertz, a voltage drop is generated even by a small inductance existing in the discharge path. Therefore, the influence of the inductance becomes ringing and is superimposed on the applied voltage, which causes a phenomenon that the voltage applied to the scan electrode and the sustain electrode is unexpectedly increased. In addition, the applied voltage oscillates up and down, causing a phenomenon that a constant voltage is not applied to each electrode. As described above, the phenomenon in which the voltage increases unexpectedly or the applied voltage oscillates up and down significantly reduces the display quality. That is, when a voltage higher than the desired voltage is applied to the electrodes, the electric field strength applied to the discharge cells increases, so that a strong discharge occurs, and unintentionally, lighting with high luminance is achieved. Further, if the voltage applied to the electrode vibrates after the discharge, wall charges necessary for the next discharge cannot be uniformly formed in the discharge cell, and the next discharge intensity becomes non-uniform. Furthermore, since the scan electrode drive circuit 5 and the sustain electrode drive circuit 6 are arranged at the center in the vertical side direction of the PDP 10, in the case of a PDP having a large screen size, from the output terminal of each circuit to each electrode. The distance is longer at the top and bottom of the screen and shorter at the center. Therefore, the inductance in the discharge path is also different between the upper and lower portions of the screen and the central portion. As a result, there is a difference in luminance due to the reasons described above, resulting in uneven display in which light is emitted brightly at the top and bottom of the screen and darkly at the center of the screen. Therefore, a technique for reducing the inductance of the discharge path length itself has been disclosed. Alternatively, a technique for reducing the difference in path length between the upper and lower discharge path lengths of the screen and the central discharge path length is disclosed.

  The first prior art changes the electrode connection structure of the PDP, and by simultaneously carrying out two ways of flowing current from the scan electrode to the sustain electrode and flowing from the sustain electrode to the scan electrode, The current flowing to the potential side, that is, the current flowing to the chassis member is canceled out. As a result, the current flowing through the chassis member cancels and becomes smaller, so that a voltage drop due to the inductance of the chassis member can be reduced (for example, Patent Document 1).

In the second conventional technique, the position of the switch element of the scan electrode drive circuit and the switch element of the sustain electrode drive circuit are made different in the vertical side direction of the PDP (see, for example, Patent Document 2). In order to solve the problem of non-uniform brightness between the upper and lower electrodes and the central part of the electrode arranged in the PDP, the arrangement of the switch elements is devised, the discharge path length to the upper and lower parts, and the central part The difference from the discharge path length is reduced. As a result, since the difference in inductance to each electrode of the PDP is reduced, the luminance difference in the plane of the PDP is reduced.
Japanese Patent Laid-Open No. 11-85098 JP 2005-316133 A

  In the first prior art, currents in both directions are supplied simultaneously unless a drive circuit for flowing current from the scan electrode to the sustain electrode and a drive circuit for flowing current from the sustain electrode to the scan electrode are not provided independently. It is not possible. Therefore, since the configuration of the drive circuit is about twice that of a general plasma display panel drive circuit, there is a problem that the circuit is increased in size, the weight is increased, and the cost is increased. .

  The second prior art assumes that the switch element is directly connected to the chassis member. When the switch element is connected to the chassis member, the temperature of the chassis member at the connection portion of the switch element rises, and the temperature of the PDP rises locally due to the heat. As a result, the light emission state of the PDP changes, which adversely affects the image quality. Further, the number of switch elements is one. However, it is difficult to realize the operation of conducting or blocking the PDP discharge current with one switch element because the PDP discharge current is too large. Even if one switch element can cover the discharge current, if the current is concentrated on one switch element, the current concentrates on the terminal part of the switch element, so the voltage drop due to inductance at the terminal part increases. As a result, the inductance of the discharge path length is increased.

  In view of the above problems, the present invention reduces the difference in inductance existing in the discharge path for each electrode by reducing the difference in the discharge path length for each electrode of the PDP, and superimposes it on the applied voltage as a result. An object of the present invention is to provide a plasma display in which display quality is improved by reducing a difference such as ringing. It is another object of the present invention to provide a plasma display with high display quality without locally increasing the temperature of the PDP. It is another object of the present invention to provide a plasma display that realizes a means for improving display quality by such a method in a small size, light weight, and low cost.

  The plasma display according to the present invention is extended in the horizontal direction of the plasma display panel and is drawn out to the vertical side of one end and the vertical side of the other end different from the vertical side of the first electrode. A plasma display panel having a second electrode; a conductive plate supporting the plasma display panel; and a fastening hole connected to the first electrode and electrically connected to a ground potential. A first driving circuit board; and a second driving circuit board having a fastening hole connected to the second electrode and electrically connected to a ground potential, the hole of the first driving circuit board The first driving circuit board and the second driving circuit board are made of conductive connecting material on the plate so that the holes of the second driving circuit board and the vertical side direction of the plasma display panel are different from each other. Characterized in that fastened to the serial plate.

  According to the present invention, since the difference between the electrodes arranged in the row direction in the current path length through which the discharge current flows in the sustain period is reduced, the distortion of the voltage at the upper and lower portions and the central portion of the PDP is reduced. As a result, the difference in luminance is reduced, so that uniform luminance characteristics can be obtained and display quality can be improved.

  In the plasma display of the present invention, at least one of the first drive circuit board and the second drive circuit board is connected to a voltage source and to supply or cut off the voltage of the voltage source to the first electrode. A first switch element, and a second switch element connected to the first switch element and connected to disconnect or connect the first electrode to a ground potential. The drive circuit board or the second drive circuit board is close to a hole included in the drive circuit board.

  According to the present invention, since the discharge current flows from the second switch element to the hole, the discharge path length from the switch element to the hole can be shortened, so that the inductance of the discharge path length is reduced. Therefore, since the magnitude of the voltage waveform distortion itself can be reduced, the PDP can be driven with a more preferable driving waveform. As a result, the magnitude of ringing or the like is reduced, and circuit loss can be reduced.

  In the plasma display of the present invention, at least either the first drive circuit board or the second drive circuit board has the first switch element arranged at the center of the board and the second switch element is divided into the upper and lower parts of the board. It is arranged. Alternatively, the first drive circuit board or the second drive circuit board is characterized in that the second switch element is arranged at the center of the board and the first switch element is divided and arranged on the upper and lower sides of the board. Alternatively, the first drive circuit board or the second drive circuit board is characterized in that the first switch element is disposed on the upper part of the substrate and the second switch element is disposed on the lower part of the substrate.

  In the plasma display of the present invention, the positions of the holes of the first drive circuit board and the second drive circuit board are arranged symmetrically with respect to the center in the horizontal direction of the plasma display panel.

  According to the present invention, since the difference between the electrodes arranged in the row direction in the current path length through which the discharge current flows in the sustain period is reduced, the distortion of the voltage at the upper and lower portions and the central portion of the PDP is reduced. As a result, the difference in luminance is reduced, so that uniform luminance characteristics can be obtained and display quality can be improved.

  As described above, the plasma display according to the present invention has a discharge path length passing through each electrode arranged in the row direction of the PDP by changing the position of the hole of the drive circuit board and the mounting position of each switch of each circuit. The difference can be reduced. As a result, the difference in luminance between the upper and lower portions and the central portion of the PDP can be reduced, and a plasma display with high display quality that can be lit uniformly over the entire screen can be provided. In addition, since the plasma display according to the present invention can be realized with almost the same number of parts as the conventional driving circuit, the weight does not increase and the circuit cost does not increase. A display can be provided. In addition, the plasma display according to the present invention does not radiate heat generated by the electrical conduction loss of each switch to the chassis member, so that the temperature of the PDP is not increased locally. Therefore, a plasma display with high display quality can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view showing an arrangement of a plasma display according to Embodiment 1 of the present invention viewed from the back side. The scan electrode drive circuit 5 is roughly composed of a sustain circuit 51, an initialization circuit 52, a write circuit 53, and a recovery circuit 54. The writing circuit 53 is connected to the flexible wiring board 21, and the flexible wiring board 21 is connected to the scanning electrode 22 of the PDP 10. That is, since the writing circuit 53 is connected to the entire scanning electrode 22 of the PDP 10, the circuit board having the same length as the vertical side direction of the screen size (hereinafter, the circuit board on which the writing circuit 53 is mounted is referred to as an AD board). Implemented. The number of AD boards is limited by the size of the circuit board in manufacturing, and therefore, depending on the length in the vertical direction of the screen, one is used when the number is small and about four is used when there are many.

  The circuit board manufacturing size is limited by the board size that can be handled by a component mounter for mounting circuit components on the circuit board, and the board size that can be handled by a component inspection machine that inspects whether circuit components are correctly mounted. Often decided. In either case, when the substrate size is increased, warpage caused by thermal stress and stress applied to the substrate are increased. Therefore, it is necessary to add a reinforcing material to the substrate itself. Further, when the board is warped, a defect rate such as failure to mount components correctly is increased. Further, in order to handle a large-sized substrate, these facilities must be enlarged, and power consumption and the like increase. However, these facilities usually also produce small substrates to increase availability. In general, the production volume of small boards is overwhelmingly larger than that of large boards, so when manufacturing small boards with equipment for large boards, it requires a lot of power consumption. Production efficiency of small substrates is reduced. For these reasons, circuit board manufacturing facilities such as component mounters and component inspection machines are limited in the size of circuit boards they can handle. As a result, depending on the length of the screen size of the plasma display in the vertical side direction, the AD substrate may be configured with one sheet as described above, or may require a plurality of sheets.

  Maintenance circuit 51 includes at least two switch elements. These switch elements are the first high-side sustain switch element S5 for supplying the sustain voltage Vsus to the PDP 10 during the sustain period and the first low-side sustain switch element S6 for supplying the ground potential. The connection method and the on / off operation of these switch elements are the same as those in FIG. Unlike the case of the write circuit 53, the maintenance circuit 51, the initialization circuit 52, and the recovery circuit 54 can often be mounted on one circuit board from the viewpoint of the number of necessary components, and many of them are mounted on one sheet. (Hereinafter, a circuit board on which the sustain circuit 51, the initialization circuit 52, and the recovery circuit 54 included in the scan electrode driving circuit 5 are mounted is referred to as an SC board). Therefore, the SC substrate is arranged so as to be at the center when viewed from the vertical side direction of the PDP 10 as shown in FIG. 1, and the connection with the AD substrate differs depending on whether the AD substrate is singular or plural. They are connected by output terminals extending in the vertical direction with the central portion in the longitudinal direction as the center. Taking FIG. 15, which is the prior art, as an example, the circuit component mounted on the SC substrate and disposed closest to the PDP 10 when the discharge current path is considered is the second separation switch element S10. Therefore, the second separation switch element S10 is arranged on the left side of the SC substrate and extending in the vertical direction. The SC board and the AD board may be connected with a connector or a screw. Note that the second separation switch element S10 may be formed by arranging a plurality of switch elements connected in parallel in the vertical direction, or by extending the output terminal of one switch element in the vertical direction.

  On the other hand, the sustain electrode drive circuit 6 includes a second high-side sustain switch element S7 and a second low-side sustain switch element S8 and is mounted on one substrate (hereinafter, the sustain electrode drive circuit 6 is mounted). This substrate is called a SU substrate). The sustain electrode driving circuit 6 may have the same circuit configuration and driving method as those of the prior art. The connection between the output terminal of the sustain electrode drive circuit 6 and the sustain electrode 23 extends in the longitudinal direction and is connected by the flexible wiring board 21 as in the write circuit 53 of the scan electrode drive circuit. Since the substrate size of the SU substrate is limited as described above, as shown in FIG. 1, the SU substrate itself is arranged at the center in the vertical direction, and another output terminal is extended in the vertical direction. Circuit boards 6Y and 6Z may be provided.

  A current path when a discharge current flows through the PDP 10 during the sustain period will be described with reference to FIG. First, a case where the discharge current flows through SC1 and sustain electrode SU1, which are the uppermost portions of scan electrode 22, will be described. A sustain voltage is applied to scan electrode 22 from voltage source V1 that generates sustain voltage Vsus on the SC substrate via first high-side sustain switch element S5. The discharge current passes from the first high-side sustain switch element S5 through the first separation switch element S9, the second separation switch element S10, and the scan driver IC1, and reaches the scan electrode 22 of the PDP 10. The length of the discharge path so far is X1. Subsequently, the current flows through the scan electrode 22 of the PDP 10 and is discharged in the discharge cell selected during the address period, and then reaches the sustain electrode drive circuit 6 from the sustain electrode 23. This discharge path length is X2. Subsequently, the current flows from the terminal of the sustain electrode driving circuit 6 to the ground potential via the second low-side sustain switch element S8. This discharge path length is X3. Subsequently, the screw 8 that fastens the chassis member 26 and the circuit board on which the sustain electrode drive circuit 6 is mounted (hereinafter, the circuit board on which the sustain electrode drive circuit 6 is mounted is referred to as a SU substrate) from the ground potential. A discharge current flows through the chassis member 26 via the. This discharge path length is X4. After passing through the chassis member 26, the ground potential of the scan electrode drive circuit 5 passes through the screw 7 that fastens the SC substrate and the chassis member. This discharge path length is X5. Finally, it reaches the ground potential of the voltage source V1. This discharge path length is X6. When the discharge current is passed through the uppermost scan electrode and sustain electrode in this way, the discharge path length is X1 + X2 + X3 + X4 + X5 + X6. On the other hand, the discharge path length when the discharge current flows from the scan electrode SCi at the center to the sustain electrode SUi is I1 + I2 + I3 + I4 + I5 + I6 in the same manner. Of these discharge path lengths, X2 = I2, X4 = I4, X5 = I5, and X6 = I6. Therefore, the discharge path length differs between the uppermost row and the central portion of the electrodes as X1 and X3. There are only two places. When the length differences (X1-I1) and (X3-I3) are large, a difference occurs in the inductance of the discharge path length, the magnitude of ringing differs, and a difference in luminance occurs. To do. In particular, when the screen size is large, the values of (X1-I1) and (X3-I3) themselves are large, so that the difference in inductance is also large, which occurs remarkably.

  On the other hand, the inductance of the discharge path length is determined by the length of all the discharge paths. That is, the top row is the sum from X1 to X6, and the center portion is the sum from I1 to I6. In the first embodiment of the present invention, the position of the SC substrate screw 7 in the longitudinal direction is different from the position of the SU substrate screw 8 in the longitudinal direction. Therefore, the discharge path X5 (equal to I5) is longer than before. Conventionally, since the position of the screw in the vertical side direction is the same, the discharge path of X5 is not inclined but is in the horizontal side direction as shown in FIG. However, in the present invention, the position of each screw in the longitudinal direction is different, so that it is slanted, and the discharge path length is longer than in the conventional case. As a result, since the entire length of the discharge path becomes longer, the ratio of (X1-I1) and (X3-I3) to the length of the entire discharge path becomes relatively small. Therefore, the difference in inductance between the upper part and the center part of the screen is reduced, and the difference in luminance is also reduced. FIG. 3 is a voltage waveform diagram of the upper and central scan electrodes in the sustain period of the conventional plasma display. ΔVxo is the amplitude of ringing in the voltage waveform of the scan electrode at the top of the screen, and ΔVio is the amplitude of ringing in the voltage waveform of the scan electrode in the center of the screen. On the other hand, FIG. 4 is a voltage waveform diagram of the upper and central scan electrodes in the sustain period of the plasma display according to the first embodiment of the present invention. ΔVxn is the amplitude of ringing in the voltage waveform of the scan electrode at the top of the screen, and ΔVin is the amplitude of ringing in the voltage waveform of the scan electrode in the center of the screen. Compared to the conventional case of FIG. 3, the difference in ringing is smaller in the first embodiment of the present invention as shown in FIG. FIG. 5 is a graph comparing the relative ratios of the luminances of the display screens in the upper part and the central part of the conventional plasma display and the first embodiment of the present invention. As can be seen from this result, when the luminance of the upper part of the screen of the conventional plasma display is set to 1, conventionally, a luminance difference of 9% has occurred between the upper part and the central part. In Embodiment 1 of the present invention, the brightness difference is improved to 7%. Thus, the difference in the inductance of the discharge path between the upper part and the central part is reduced, so that the difference in ringing is also reduced, and as a result, the difference in luminance is reduced. As described above, the present invention can reduce the luminance difference of the screen, and can provide a plasma display with high display quality.

  It should be noted that the luminance difference is ideally 0, but it is sufficient that the luminance difference is reduced to a level at which the luminance difference cannot be visually recognized. The luminance difference can be reduced to the extent shown in the first embodiment of the present invention. That's fine.

  Further, since the discharge current flows both from the scan electrode drive circuit 5 to the sustain electrode drive circuit 6 and from the sustain electrode drive circuit 6 to the scan electrode drive circuit 5, the positions of the screws 7 and 8 are It is preferable to arrange them so as to be in a line-symmetrical position with the horizontal direction at the center of the screen as the center. Moreover, the screw 7 and the screw 8 do not need to be one, and a plurality of screws may be used.

(Embodiment 2)
FIG. 6 is a plan view showing an arrangement of the plasma display according to the second embodiment of the present invention viewed from the back side. Scan electrode driving circuit 5A according to the second embodiment of the present invention is different from the first embodiment in that first low-side sustain switch element S6 is mounted on an AD substrate. That is, a plurality of first low-side sustain switch elements S6 are electrically connected in parallel, and a part is mounted on the upper AD substrate and the rest is mounted on the lower AD substrate.

  In the sustain electrode drive circuit 6A, a plurality of second low-side sustain switch elements S8 are electrically connected in parallel like the scan electrode drive circuit 5A, and the first embodiment is that the sustain electrode drive circuit 6A is divided into upper and lower parts and mounted. And different. That is, the second low-side sustain switch element S8 is mounted on the upper side or the lower side of the vertical direction on the SU substrate. FIG. 6 shows a preferred example in which the first low-side sustain switch element S6 and the second low-side sustain switch element S8 are mounted on both the upper part and the lower part, respectively.

  The discharge path length in Embodiment 2 of this invention is demonstrated using Fig.7 (a) and (b). As in FIG. 2 in the first embodiment of the invention, FIG. 7A shows the discharge path length when the sustain voltage Vsus is applied to the scan electrode side and the ground potential is applied to the sustain electrode side. FIG. 7B shows the discharge path length when the sustain voltage Vsus is applied to and the ground potential is applied to the scan electrode side. First, a case where the sustain voltage Vsus is applied to the scan electrode side and a discharge current is caused to flow from the scan electrode side to the sustain electrode side will be described with reference to FIG. The path when the discharge current flows through the upper scan electrode is represented by the sum from X1 to X4, as in FIG. 2 of the first embodiment. Here, unlike FIG. 2, some discharge paths are omitted. That is, the sum of X3 and X4 in the first embodiment is X3 in the second embodiment, and the sum of X5 and X6 in the first embodiment is X4 in the second embodiment. On the other hand, the path in the case where the discharge current flows through the central scan electrode is represented by the sum of I1 to I4. As is clear from FIG. 7A, in the discharge current path, the lengths of X2 and I2 are the same in the path flowing through the upper part and the path flowing through the central part. Similarly, the lengths of X4 and I4 are the same. Therefore, it is (X1-I1) and (X3-I3) that the discharge path length differs between the path flowing through the upper part and the path flowing through the central part. In the case of the prior art, the second sustain switch element S8 is in the vicinity of the central portion in the SU substrate, and therefore has a relationship X3> I3. Therefore, (X1-I1) and (X3-I3) are both positive values, and the inductance of the X path with the discharge path at the top is larger. According to the second embodiment of the present invention, since the second sustain switch element S8 is above the SU substrate, the relationship X3 <I3 is established. Therefore, X1−I1> 0, but X3−I3 <0, and the difference in the length of the discharge path between the discharge path X and the discharge path I is smaller than in the prior art. As a result, the same effect as in the first embodiment of the invention is obtained. That is, since the difference in inductance caused by the difference in discharge path is reduced, the difference in luminance is reduced, and a plasma display with high display quality can be provided.

  Next, a case where the sustain voltage Vsus is applied to the sustain electrode side and a discharge current is caused to flow from the sustain electrode side to the scan electrode side will be described with reference to FIG. The path when the discharge current flows through the upper sustain electrode is represented by the sum from X1 to X4, as in FIG. 7A. On the other hand, the path in the case where the discharge current flows through the central sustain electrode is represented by the sum from I1 to I4. As apparent from FIG. 7B, in the discharge current path, (X1-I1) and (X3-I3) are different between the path flowing through the upper part and the path flowing through the central part. This current path is the same as that in the case where the current is passed from the scan electrode to the sustain electrode, and in the second embodiment of the present invention, X1-I1> 0, but X3-I3 <0. As a result, the difference in the length of the discharge path between the discharge path X and the discharge path I is smaller than that in the prior art, and thus the same effect as in the first embodiment of the invention is obtained. That is, since the difference in inductance caused by the difference in discharge path is reduced, the difference in luminance is reduced, and a plasma display with high display quality can be provided.

  In the above description, the case where the discharge current passes through the first low-side sustain switch element S6 and the second low-side sustain switch element S8 disposed in the upper part of the vertical side direction has been described as an example. As the path through which the discharge current flowing in the electrode is passed, the amount passing through the low-side sustain switch element arranged at the lower part in the vertical side direction is small because the impedance is large and may be ignored. Conversely, the discharge current flowing through the electrode disposed in the lower portion of the PDP 10 passes through the first low-side sustain switch element and the second low-side sustain switch element disposed in the lower portion in the vertical direction. Absent. In this case, the same can be said when the discharge path described above is considered to be symmetrical with respect to the axis in the horizontal direction of the PDP 10. Therefore, the discharge path length passing through the electrodes arranged in the lower part of the PDP 10 is the same as the discharge path length flowing in the upper electrode described above. Therefore, according to the second embodiment of the present invention, the luminance difference can be reduced over the entire PDP 10, so that a plasma display with high display quality can be provided.

  In the second embodiment, the conductive screw 7A having the voltage source V1 and a screw terminal electrically connected to the ground potential of the circuit in the vicinity of the first high-side sustain switch element S5. Is preferably connected to the chassis member 26. Further, in the vicinity of the first low-side sustain switch element S6, it is preferable to similarly have a screw 7B and a conductive screw 7C that are electrically connected to the ground potential of the circuit and are electrically connected to the chassis member. Similarly, it is preferable to have a voltage source V1 and a conductive screw 8A in the vicinity of the second high-side sustain switch element S7. In addition, it is preferable to have a conductive screw 7B and a conductive screw 7C in the vicinity of the second low-side sustain switch element S8. The method of increasing the inductance by increasing the distance between the screw and the voltage source or each switch element on the SC substrate, AD substrate or SU substrate is not preferable because the amount of increase in inductance per unit length of the circuit board is large. . Since it is easier to make the inductance by the circuit board as small as possible and increase the inductance by the chassis member 26, the screw terminals are preferably arranged near the voltage source or each switch element as described above.

  In the present embodiment, the first high-side sustain switch element S5 and the second high-side sustain switch element S7 are arranged in the center, and the first low-side sustain switch element S6 and the second low-side sustain switch element S8 are arranged. However, the same effect can be obtained by replacing the switch elements. That is, the first low-side sustain switch element S6 is arranged at the center of the SC substrate, the first high-side sustain switch element S5 is divided into an upper part and a lower part, and the second low-side sustain switch element S8 is arranged at the SU. The second high-side sustain switch element S7 may be divided into an upper part and a lower part of the SU substrate.

(Embodiment 3)
FIG. 8 is a plan view showing the arrangement of the plasma display according to the third embodiment of the present invention viewed from the back side. Scan electrode drive circuit 5B according to Embodiment 3 of the present invention is characterized in that first high-side sustain switch element S5 and first low-side sustain switch element S6 are mounted on an AD substrate. And different. That is, the first high-side sustain switch element S5 is mounted on the upper AD substrate, and the first low-side sustain switch element S6 is mounted on the lower AD substrate. In sustain electrode driving circuit 6B according to the third embodiment of the present invention, second high-side sustain switch element S7 is mounted on the upper portion of the SU substrate, and second low-side sustain switch element S8 is mounted on the lower portion. . In addition, as described in the second embodiment, screw terminals 7D, 7E having electrical connection with the ground potential of each circuit and having electrical conductivity with the chassis member are provided near each switch element. Connected by 8D and 8E.

  FIG. 9 shows the discharge path when each sustain switch element is mounted in this way. FIG. 9 shows a discharge path when the sustain voltage Vsus is applied to the scan electrode side and the ground potential is applied to the sustain electrode side. As in the second embodiment, the discharge path length to the upper electrode of the PDP 10 is the sum of X1 to X4, and the discharge path length to the center electrode of the PDP 10 is the sum of I1 to I4. It is. FIG. 9 shows that (X1 + X3) is close to (I1 + I3). Therefore, since the discharge path length of the discharge path X and the discharge path length of the discharge path I are substantially equal, the difference in inductance between the upper part and the center part of the PDP 10 is reduced, and the difference in luminance is also reduced. As a result, a plasma display with high display quality can be provided. Since the same applies to the case where the applied voltage Vsus is applied to the sustain electrode side and the ground potential is applied to the scan electrode side, the description thereof is omitted. In this way, by arranging the high-side sustain switch element and the low-side sustain switch element so as to be different in the vertical side direction of the PDP 10, the brightness difference between the upper part and the central part of the PDP 10 is reduced, and a plasma display with high display quality is provided. can do. In this embodiment, each high-side sustain switch element is disposed on the upper side of the PDP 10 and the low-side sustain switch element is disposed on the lower side of the PDP 10. However, the opposite arrangement may be performed. That is, even if each high-side sustain switch element is disposed below the PDP 10 and the low-side sustain switch element is disposed above the PDP 10, the same effect is obtained.

  The voltage source V1 described in the first to third embodiments may be a capacitive element such as a capacitor. Alternatively, another element that can supply a high-frequency current with low impedance may be used. Each switch element has been described mainly with a MOSFET, but may be a switch element in which an IGBT and an antiparallel diode are connected.

  As described in Embodiments 1 to 3 above, according to the present invention, a specific circuit configuration for reducing the inductance in the discharge path can be provided, so that the luminance difference can be reduced. In addition, a plasma display with low power consumption and high display quality can be provided.

  FIG. 10 is a graph showing, for each screen size, a difference between an upper luminance and a central luminance measured in a conventional plasma display, and the difference divided by an absolute luminance as a relative value. As shown in FIG. 5 in Embodiment 1 of the present invention, the present invention has an effect that the luminance difference is improved by several percent. Therefore, as can be seen from FIG. 10, the larger the screen is, the more noticeable the luminance difference is. Therefore, the effect of the present invention is more remarkable on the large screen. Therefore, it is effective to apply the above-described first to third embodiments to a plasma display having a particularly large screen size. In particular, when it exceeds 60 inches, the effect of the present invention becomes remarkable because the luminance difference in the prior art is large.

  The present invention relates to a plasma display panel, and as described above, has an effect of improving the image quality, and thus is industrially useful.

The top view which shows the arrangement | positioning seen from the back side of the plasma display in Embodiment 1 of this invention The top view which shows the path | route of the discharge current of the plasma display in Embodiment 1 of this invention Voltage waveform diagram of upper and center scan electrodes during sustain period of conventional plasma display Voltage waveform diagram of upper and central scan electrodes in sustain period of plasma display in embodiment 1 of the present invention The graph which compared the relative ratio of the brightness | luminance of the display screen of the upper part of the conventional and the plasma display in Embodiment 1 of this invention, and a center part The top view which shows the arrangement | positioning seen from the back side of the plasma display in Embodiment 2 of this invention The top view which shows the path | route of the discharge current of the plasma display in Embodiment 2 of this invention The top view which shows the arrangement | positioning seen from the back side of the plasma display in Embodiment 3 of this invention The top view which shows the path | route of the discharge current of the plasma display in Embodiment 3 of this invention A graph showing the relative value of the difference between the screen size of the conventional plasma display and the brightness at the top and center of the screen A perspective view showing a configuration of a conventional plasma display panel The figure which shows the electrode arrangement of the conventional plasma display panel Voltage waveform diagram applied to each electrode of a conventional plasma display panel during one subfield period Block diagram showing a conventional plasma display for each functional block Specific circuit diagram of scan electrode drive circuit and sustain electrode drive circuit in a conventional plasma display panel drive circuit The top view which shows an example of the arrangement which looked at the conventional plasma display from the back side

Explanation of symbols

1 A / D converter 2 Video signal processing circuit 3 Sub-field processing circuit 4 Data electrode drive circuit 5, 5A, 5B Scan electrode drive circuit 6, 6A, 6B Sustain electrode drive circuit 7, 7A, 7B, 7C, 7D, 7E Screw 8,8A, 8B, 8C, 8D, 8E Screw 10 PDP
DESCRIPTION OF SYMBOLS 20 Front plate 21 Flexible wiring board 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protective layer 26 Chassis member 30 Back plate 31 Flexible wiring board 32 Data electrode 33 Dielectric layer 34 Partition 35 Phosphor layer 51 Sustain circuit 52 Initialization circuit 53 Write Circuit 54 Recovery Circuit C1 First Recovery Capacitor C2 Second Recovery Capacitor D1 First High Side Recovery Diode D2 First Low Side Recovery Diode D3 Second High Side Recovery Diode D4 Second Low Side Recovery Diode IC1 Scan Driver L1 First inductor L2 Second inductor S1 First high-side recovery switch element S2 First low-side recovery switch element S3 Second high-side recovery switch element S4 Second low-side recovery switch element S5 First C Iside sustain switch element S6 First low side sustain switch element S7 Second high side sustain switch element S8 Second low side sustain switch element S9 First isolation switch element S10 Second isolation switch element S11 High side initialization switch element S12 Low-side initialization switch element

Claims (7)

A plasma display panel;
A first electrode included in the plasma display panel, extending in a horizontal side direction of the plasma display panel and drawn out to a vertical side of one end;
A second electrode that is included in the plasma display panel, extends in a horizontal side direction of the plasma display panel, and is drawn to a vertical side of the other end different from a vertical side of the first electrode;
A conductive plate supporting the plasma display panel;
A first drive circuit board having a fastening hole connected to the first electrode and electrically connected to a ground potential;
A second drive circuit board having a fastening hole connected to the second electrode and electrically connected to a ground potential;
The first driving circuit board and the second driving circuit board are arranged on the plate such that the holes of the first driving circuit board and the holes of the second driving circuit board are different in the vertical direction of the plasma display panel. The plasma display is characterized in that the plate is fastened to the plate with a conductive connecting material. 2. The positions of the holes of the first driving circuit board and the second driving circuit board are arranged symmetrically with respect to the center in the horizontal direction of the plasma display panel. Plasma display. At least one of the first drive circuit board and the second drive circuit board is
A voltage source;
A first switch element connected to supply or cut off the voltage of the voltage source to the first electrode;
A second switch element connected to the first switch element and connected to connect or disconnect the first electrode to a ground potential;
The number of the holes is at least two, at least one of the holes is disposed in proximity to the voltage source, and at least one of the holes is disposed in proximity to the second switch element. Item 3. The plasma display according to item 1 or 2. At least one of the first drive circuit board and the second drive circuit board is
The plasma display according to any one of claims 1 to 3, wherein the first switch element is disposed in the center of the substrate, and the second switch element is divided and disposed above and below the substrate. At least one of the first drive circuit board and the second drive circuit board is
4. The plasma display according to claim 1, wherein the first switch element is disposed on an upper part of the substrate and the second switch element is disposed on a lower part of the substrate. At least one of the first switch element and the second switch element is:
6. The plasma display according to claim 1, wherein a plurality of transistors are connected in parallel. The plasma display according to any one of claims 1 to 6, wherein the plasma display panel has a diagonal length of 60 inches or more.

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