JP2008197426A - Plasma display device and drive circuit for the plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize stable discharge by reducing ringing of a drive voltage waveform, even for a plasma display panel which is turned larger in screen and higher in luminance. <P>SOLUTION: The plasma display device includes a plasma display panel provided with a plurality of discharge cells having a display electrode pair consisting of scanning electrodes and sustain electrodes, an electric power recovery circuit for recovering the electric power accumulated in the inter-electrode capacity of the display electrode pair, and a sustain pulse generation circuit having a clamping circuit provided with a first switching element S1, consisting of an IGBT charged to a power voltage with each of the display electrode pair and a second switching element S2 consisting of IGBT clamped to a base potential. An IC is formed by integrating these IGBTs inside a single package. A diode D 12 for protecting the IGBT which is the second switching element S2 is mounted within the IC, and a diode D 11 for protecting the IGBT which is the first switching element S1 is disposed on the outside of the IC. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor and a driving circuit for the plasma display device.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges. In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

In order to reduce the power consumption of the plasma display device using the panel having such a configuration, various power consumption reduction techniques have been proposed. For example, as one of the techniques for reducing the power consumption in the sustain period, focusing on the fact that each of the display electrode pairs is a capacitive load having an interelectrode capacitance of the display electrode pair, a resonant circuit including an inductor as a component So that the inductor and interelectrode capacitance are LC-resonated, the charge stored in the interelectrode capacitance is collected in a power recovery capacitor, and the collected charge is reused for driving the display electrode pair. A circuit is disclosed (for example, see Patent Document 1).
Japanese Examined Patent Publication No. 7-109542

  However, in recent years, the power required for driving the panel is increasing more and more with the increase in the screen size and the brightness of the panel. Therefore, the amount of current flowing through the drive circuit for driving the panel also increases, thereby causing a problem that ringing generated in the drive voltage applied to the panel increases and discharge becomes unstable.

  The present invention has been made in view of these problems. Even in a panel with a large screen and high brightness, the ringing of the drive voltage waveform is reduced to realize stable discharge, and the image display quality is improved. An object of the present invention is to provide a plasma display device and a driving circuit for the plasma display device that can be made to operate.

  In order to solve this problem, a plasma display apparatus according to the present invention recovers power accumulated in the interelectrode capacitance of a display electrode pair of a plasma display panel and supplies the recovered power to the display electrode pair. The sustain pulse generating circuit includes a first switching element composed of an IGBT for clamping the display electrode pair to a power supply voltage, and a second composed of an IGBT for clamping the display electrode pair to a base potential. A clamp circuit including the switching elements, and the clamp circuit includes the first switching element, the second switching element, and a diode for protecting the second switching element in one package. The semiconductor element configured as described above and the first element are provided separately from the semiconductor element. Characterized by comprising a diode for protecting the switching element.

  With this configuration, it is possible to reduce ringing of the drive voltage waveform, realize stable discharge, and improve image display quality.

  The driving circuit according to the present invention includes a first switching element made of an IGBT for clamping a display electrode pair of a plasma display panel to a power supply voltage, and a second switching element made of an IGBT for clamping the display electrode pair to a base potential. And a diode for protecting the second switching element in a single package, and a diode for protecting the first switching element separately from the semiconductor element And is provided.

  With this configuration, it is possible to reduce ringing of the drive voltage waveform, realize stable discharge, and improve image display quality.

  According to the present invention, there is provided a plasma display device capable of realizing stable discharge by reducing ringing of a drive voltage waveform and improving image display quality even in a panel having a large screen and high brightness. A driving circuit for a plasma display device can be provided.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is the luminance magnification.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows two subfields (first SF and second SF) among a plurality of subfields constituting one field period.

  In the first half of the initializing period of the first SF, 0 (V) is applied to each of the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, and the scan electrodes SC1 to SCn start discharging to the sustain electrodes SU1 to SUn. A ramp waveform voltage that gently rises from a voltage Vi1 equal to or lower than the voltage toward a voltage Vi2 that exceeds the discharge start voltage is applied. While the ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and sustain electrodes SU1 to SUn are applied to scan electrodes SC1 to SCn. On the other hand, a ramp waveform voltage that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the initialization operation for performing the initialization discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and a ramp waveform voltage that gradually decreases from voltage Vi3 ′ to voltage Vi4 is applied to scan electrodes SC1 to SCn. Apply. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Then, a negative scan pulse voltage Va is applied to scan electrode SC1 in the first row, and a positive address pulse voltage Vd is applied to data electrode Dk of the discharge cell to be emitted in the first row among data electrodes D1 to Dm. To do. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative voltage is applied on sustain electrode SU1. A wall voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  Then, after applying a sustain pulse for generating the last sustain discharge to one of the display electrode pairs, a voltage for relaxing the potential difference between the electrodes of the display electrode pair is applied to the display electrode pair at a predetermined time interval. By applying the voltage to the other side, a so-called narrow pulse voltage difference is given, and the wall voltage on the scan electrode SCi and the sustain electrode SUi is erased while leaving the positive wall voltage on the data electrode Dk. . Thus, the maintenance operation in the maintenance period is completed.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks.

  Scan electrode driving circuit 43 has sustain pulse generating circuit 50 for generating sustain pulse voltages to be applied to scan electrodes SC1 to SCn in the sustain period, and drives each of scan electrodes SC1 to SCn based on the timing signal. . Sustain electrode drive circuit 44 has sustain pulse generation circuit 60 for generating a sustain pulse voltage to be applied to sustain electrodes SU1 to SUn during the sustain period, and drives sustain electrodes SU1 to SUn based on a timing signal.

  Next, the details and operation of sustain pulse generating circuits 50 and 60 will be described. FIG. 5 is a circuit diagram of sustain pulse generation circuits 50 and 60 according to an embodiment of the present invention. In FIG. 5, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit for generating the scan pulse and the initialization voltage waveform is omitted.

  The sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 and the clamp circuit 52 include a scan pulse generation circuit (not shown because it is in a short-circuit state during the sustain period). And is connected to scan electrodes SC1 to SCn which are one end of the interelectrode capacitance Cp of the panel 10.

  The power recovery circuit 51 includes a power recovery capacitor C1, switching elements Q1 and Q2, backflow prevention diodes D1 and D2, and a resonance inductor L1. Then, the interelectrode capacitance Cp and the inductor L1 are LC-resonated to cause the sustain pulse to rise and fall.

  The clamp circuit 52 includes a switching element S1 for clamping scan electrodes SC1 to SCn to voltage Vs, and a switching element S2 for clamping scan electrodes SC1 to SCn to 0 (V). Then, scan electrodes SC1 to SCn are connected to power supply VS via switching element S1 and clamped to voltage Vs, and scan electrodes SC1 to SCn are grounded and switched to 0 (V) via switching element S2. Therefore, when a voltage is applied by the clamp circuit 52, a large discharge current due to the sustain discharge flows.

  In this embodiment, the switching elements S1 and S2 are insulated gate bipolar transistors (IGBTs) having a feature of low loss and simple control even during high voltage operation. Thereby, the loss which arises when flowing a large current is reduced.

  The clamp circuit 52 includes a diode D11 for protecting the switching element S1 and a diode D12 for protecting the switching element S2. The diodes D11 and D12 will be described later.

  Sustain pulse generation circuit 60 includes power recovery capacitor C2, switching elements Q3 and Q4, backflow prevention diodes D3 and D4, and power recovery circuit 61 having resonance inductor L2, and sustain electrodes SU1 to SUn at voltage Vs. A switching element S3 for clamping to a ground potential, a diode D13 for protecting the switching element S3, a switching element S4 for clamping the sustain electrodes SU1 to SUn to the ground potential, and a clamping circuit 62 having a diode D14 for protecting the switching element S4 And is connected to sustain electrodes SU1 to SUn which are one end of the interelectrode capacitance Cp of the panel 10.

  Sustain pulse generation circuits 50 and 60 switch power recovery circuits 51 and 61 and clamp circuit 52 by switching between conduction and cutoff of switching elements Q1 to Q4 and S1 to S4 according to a timing signal output from timing generation circuit 45. , 62 are operated to generate the sustain pulse voltage Vs during the sustain period.

  Next, generation of sustain pulse voltage Vs will be described. FIG. 6 is a timing chart for explaining the operation of sustain pulse generating circuit 50 in one embodiment of the present invention. Here, one period of the sustain pulse is divided into four periods indicated by T1 to T4, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”. Although sustain pulse generation circuit 50 on the side of scan electrodes SC1 to SCn will be described here, sustain pulse voltage Vs is similarly generated by operating sustain pulse generation circuit 60 on the side of sustain electrodes SU1 to SUn in the same manner. Can do.

(Period T1)
At time t1, switching element Q1 is turned on. Then, charges start to move from the power recovery capacitor C1 to the scan electrodes SC1 to SCn through the switching element Q1, the diode D1, and the inductor L1, and the voltage of the scan electrodes SC1 to SCn starts to rise. Since inductor L1 and interelectrode capacitance Cp form a resonance circuit, the voltage of scan electrodes SC1 to SCn rises to near Vs at time t2 when about half of the resonance period has elapsed. However, the voltage of scan electrodes SC1 to SCn does not rise to Vs due to power loss due to the resistance component of the resonance circuit.

(Period T2)
Next, the switching element S1 is turned on at time t2. Then, since scan electrodes SC1 to SCn are connected to power supply VS through switching element S1, scan electrodes SC1 to SCn are clamped at voltage Vs.

  When scan electrodes SC1 to SCn are clamped to voltage Vs, the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn exceeds the discharge start voltage in the discharge cell in which the address discharge has occurred, and a sustain discharge is generated. To do. A discharge current flows from power supply VS to scan electrodes SC1 to SCn. This current instantaneously becomes a large current of several hundred amperes although it depends on the number of discharge cells that generate the sustain discharge.

(Period T3)
Next, switching element Q2 is turned on at time t3. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C1 through the inductor L1, the diode D1, and the switching element Q2, and the voltage of the scan electrodes SC1 to SCn starts to decrease. Since the inductor L1 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn drops to near 0 (V) at time t4 when about half of the resonance period has elapsed. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit.

(Period T4)
At time t4, the switching element S2 is turned on. Then, scan electrodes SC1 to SCn are directly grounded through switching element S2, so that voltages of scan electrodes SC1 to SCn are clamped to 0 (V).

  In the sustain period, the operations in the above periods T1 to T4 are repeated according to the required number of pulses. In this manner, a sustain pulse voltage that shifts from 0 (V), which is the base potential, to a voltage Vs, which is a potential for generating a sustain discharge, is alternately applied to each of the display electrode pairs 24 to sustain discharge the discharge cells. .

  Switching element Q1 may be turned off after time t2 and before time t3, and switching element Q2 may be turned off after time t4 and before the next time t1. In order to lower the output impedance of sustain pulse generating circuit 50, switching element S1 is preferably turned off immediately before time t3, and switching element S2 is preferably turned off immediately before time t1. In this embodiment, the switching element Q1 and the switching element S1 are turned off at the same timing, and the switching element Q2 and the switching element S2 are turned off at the same timing.

  Next, the diodes D11 and D12 illustrated in FIG. 5 will be described.

  In a typical MOSFET used as an element for switching, a parasitic diode called a body diode is anti-parallel to a portion that performs a switching operation (a current flows in parallel with a portion that performs a switching operation and by the switching operation). The direction opposite to the direction is the forward direction). Therefore, when a potential difference opposite to the switching current (hereinafter referred to as “reverse bias”) is applied to the MOSFET, this body diode serves as a bypass and causes a current in the direction opposite to the switching current to flow. Can do. This protects the MOSFET from reverse bias.

  However, such a parasitic diode is not generated in the IGBT due to its structure. Therefore, when the IGBT is used as a switching element, it is necessary to separately provide a diode corresponding to the above-described body diode in order to protect the IGBT from reverse bias. That is, the diode D11 described above is a protection diode for the switching element S1, and the diode D12 is also a protection diode for the switching element S2.

  Here, in the present embodiment, the switching elements S1 and S2 are integrated and arranged in one package to form a one-chip semiconductor element (IC) and the diode D12 is also mounted in this IC. In addition, the diode D11 is not mounted in the IC, but is provided outside the IC. As a result, the ringing generated when the sustain pulse is generated is reduced, and a stable sustain discharge is realized. Next, the details will be described.

  FIG. 7 is a diagram showing an outline of an IC in an embodiment of the present invention.

  As shown in FIG. 7, the IC 1 has two IGBTs and one diode inside, and has six terminals LD1 to LD6 outside. Of these, one IGBT and one diode are connected in reverse parallel, with the emitter (E) connected to the anode (A) and the collector (C) connected to the cathode (Ca).

  In this IGBT, the gate (G) is connected to the terminal LD3, the emitter (E) is connected to the terminal LD6, the collector (C) is connected to the emitter (E) of the other IGBT, and the terminals LD2 and LD5 are also connected. ing. In the present embodiment, this IGBT is used as the switching element S2, and this diode is used as the diode D12.

  The other IGBT, to which no diode is connected, has a gate (G) connected to the terminal LD1, a collector (C) connected to the terminal LD4, and an emitter (E) connected to the collector (C) of the IGBT described above. The terminals LD2 and LD5 are also connected. In the present embodiment, this IGBT is used as the switching element S1.

  The terminals LD1 and LD3 of the IC1 are connected to the timing generation circuit 45 (not shown). A signal for controlling the switching element S1 is connected to the terminal LD1, and a signal for controlling the switching element S2 is connected to the terminal LD3. Enter each. The terminal LD2 is connected to the inductor L1 of the power recovery circuit 51, the terminal LD4 is connected to the power source VS, the terminal LD6 is connected to the ground potential, and the terminal LD5 is connected to the scan electrodes SC1 to SC1 through a scan pulse generating circuit (not shown). Connect to SCn. In the present embodiment, the clamp circuit 52 is configured using the IC 1 in this way.

  Furthermore, in the present embodiment, as shown in FIG. 7, a diode D11 for protecting the switching element S1 is provided outside the IC1. Specifically, the cathode (Ca) is connected to the terminal LD4 side and the anode (A) is connected to the terminal LD5 side so that the diode D11 is antiparallel to the IGBT which is the switching element S1. At this time, the diode D11 does not necessarily need to be disposed in the immediate vicinity of the IC1, and may be disposed at a position away from the IC1. In the present embodiment, the ringing that occurs when the sustain pulse is generated is reduced by providing the diode D11 outside the IC1 in this way. This is due to the following reason.

  FIG. 8 is an enlarged view of the rising portion of the sustain pulse waveform in the present embodiment. Note that the periods T1 and T2 illustrated in FIG. 8 are the same as the periods T1 and T2 illustrated in FIG.

  In the period T2 in which the clamp operation by the clamp circuit 52 is performed, the power supply VS and the scan electrodes SC1 to SCn are connected via the switching element S1, and the voltages of the scan electrodes SC1 to SCn rise toward the voltage Vs.

  Here, in IC1, between the emitter (E) of the IGBT, which is the switching element S1, and the terminal LD5, a conductive wire formed on the integrated circuit, an electrode foil, and a metal that connects the electrode foil and the terminal of the IC1 Parasitic inductors are generated by wires (wire bonding) or the like. Since the parasitic inductor and the interelectrode capacitance Cp cause LC resonance, the voltage of the terminal LD5 continues to rise after the voltage of the emitter (E) of the switching element S1 becomes the voltage Vs, and is higher than the voltage Vs. High voltage. As a result, ringing occurs at the rising edge of the sustain pulse waveform as shown by the broken line in FIG.

  However, in this embodiment, the diode D11 is provided outside the IC1, and therefore when the anode (A) voltage of the diode D11 becomes higher than the cathode (Ca) voltage Vs, the diode D11 becomes conductive and the terminal Current can flow from the LD 5 to the power source VS. As a result, the potential of the terminal LD5 can be brought close to the voltage Vs, and ringing can be reduced as shown by the solid line in FIG.

  Note that it is difficult to obtain an effect of reducing such ringing in a configuration (not shown) in which the diode D11 is provided in the IC 1 like the diode D12. This is because the voltage of the emitter (E) of the switching element S1 only rises substantially to the same level as the voltage Vs, so that the cathode (Ca) and the anode (A) of the diode D11 have substantially the same potential, and therefore the diode D11. Is not operated, and the voltage of the terminal LD5 whose voltage is higher than that of the emitter (E) of the switching element S1 due to LC resonance cannot be lowered.

  As described above, in the present embodiment, the IGBT that is the first switching element S1 and the IGBT that is the second switching element S2 are integrated in one package to form the IC1, and the second A diode D12 for protecting the IGBT which is the switching element S2 is mounted in the IC1, and a diode D11 for protecting the IGBT which is the first switching element S1 is provided outside the IC1 to constitute a clamp circuit. Thus, even a panel with a large screen and high brightness can reduce ringing that occurs when a sustain pulse is generated and can realize a stable sustain discharge.

  In the present embodiment, the clamp circuit 52 on the scan electrodes SC1 to SCn side has been described as an example, but the same effect can be obtained with the same configuration in the clamp circuit 62 on the sustain electrodes SU1 to SUn side. it can. In addition, this configuration is not limited to the clamp circuit in the sustain pulse generation circuit. If the data electrode drive circuit has a clamp circuit, the same configuration should be applied to this clamp circuit. Thus, the same effect can be obtained.

  As described above, the present invention can realize stable discharge by reducing the ringing of the drive voltage waveform even in a panel with a large screen and high brightness, and a plasma display device with good image display quality. It is useful as a driving circuit for a plasma display device.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention 1 is a circuit diagram of a sustain pulse generation circuit according to an embodiment of the present invention. Timing chart for explaining the operation of the sustain pulse generation circuit The figure which shows the outline | summary of IC in one embodiment of this invention The figure which expanded and showed the rising part of the sustain pulse waveform in one embodiment of this invention

Explanation of symbols

1 Plasma display device 10 Panel (Plasma display panel)
21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50, 60 Sustain pulse generation circuit 51, 61 Power recovery circuit 52, 62 Clamp circuit Q1, Q2, Q3, Q4 switching element S1, S2, S3, S4 switching element ( IGBT)
C1, C2 Capacitor L1, L2 Inductor D1, D2, D3, D4, D11, D12, D13, D14 Diode

Claims (2)

A sustain pulse generating circuit having a power recovery circuit that recovers the power accumulated in the interelectrode capacitance of the display electrode pair of the plasma display panel and supplies the recovered power to the display electrode pair, the sustain pulse generating circuit, A clamp circuit having a first switching element made of an IGBT for clamping the display electrode pair to a power supply voltage and a second switching element made of an IGBT for clamping the display electrode pair to a base potential; and A semiconductor element in which the first switching element and the second switching element and a diode for protecting the second switching element are arranged in one package, and the semiconductor element is provided separately. A diode for protecting the first switching element; That the plasma display device. A first switching element comprising an IGBT for clamping a display electrode pair of a plasma display panel to a power supply voltage, a second switching element comprising an IGBT for clamping the display electrode pair to a base potential, and the second switching element A semiconductor element having a diode for protection arranged in one package is provided, and a diode for protecting the first switching element is provided separately from the semiconductor element. Driving circuit for plasma display device.

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