JP2008008980A - Driving circuit of plasma display panel and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To drive a plasma display panel (PDP) with high light emission efficiency by optimally controlling the relation between a driving waveform to supply electric power for display discharge in a sustaining period and a recovering operation of a charge and discharge current. <P>SOLUTION: A driving circuit of the PDP includes: a sustaining circuit 51 supplying electric power to start and sustain the display discharge of a PDP 10 from a sustaining voltage power supply Vsus through a switching element S5 to a pair of display electrodes; and a recovering circuit 54 having a recovery capacitor C1 which is charged and discharged by the current accompanying the display discharge, at least one inductor L1 connected in series to the recovery capacitor, and switching section S1, S2, D1, D2 controlling charge and discharge by the recover capacitor. The time period T1 from when the recovering circuit starts to supply electric power to the display electrodes by discharge from the recovery capacitor until the switching element is turned on to start to supply discharge power to the display electrodes from the sustaining circuit is controlled to at most 60% of a resonance time determined by the inductor and an electrostatic capacitance of the plasma display panel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display panel drive circuit and a plasma display device used for a wall-mounted television or a large monitor.

  An AC surface discharge type plasma display panel (hereinafter abbreviated as “PDP”) representative of an AC type includes a front plate made of a glass substrate formed by arranging scan electrodes and sustain electrodes for performing surface discharge, and data electrodes. And a back plate made of a glass substrate formed by arranging the electrodes in parallel so as to form a discharge space in the gap so that both electrodes form a matrix, and the outer periphery thereof is a sealing material such as glass frit It is comprised by sealing by. Discharge cells partitioned by barrier ribs are provided between both the front and back substrates, and a phosphor layer is formed in the cell space between the barrier ribs. In the PDP having such a configuration, ultraviolet light is generated by gas discharge, and phosphors of each color of red (R), green (G), and blue (B) are excited by the ultraviolet light to emit light, thereby performing color display. Is going.

  FIG. 9 is a perspective view showing the structure of the PDP 10. On the glass front plate 20 which is the first substrate, a plurality of pairs of display electrodes which are paired with the stripe-shaped scanning electrodes 22 and the stripe-shaped sustain electrodes 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24.

  A plurality of stripe-shaped data electrodes 32 are formed on the back plate 30 serving as the second substrate so as to three-dimensionally intersect the scan electrodes 22 and the sustain electrodes 23, and are covered with a dielectric layer 33. A plurality of barrier ribs 34 are disposed on the dielectric layer 33 in parallel with the data electrodes 32, and a phosphor layer 35 is provided on the dielectric layer 33 between the barrier ribs 34. Further, the data electrode 32 is disposed at a position between the adjacent partition walls 34.

  The front plate 20 and the back plate 30 are arranged to face each other with a minute discharge space so that the scan electrode 22, the sustain electrode 23, and the data electrode 32 are orthogonal to each other, and the outer peripheral portion thereof is made of glass frit or the like. It is sealed with a sealing material. In the discharge space, for example, a mixed gas of neon (Ne) and xenon (Xe) is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and phosphor layers emitting light of red (R), green (G), and blue (B) colors are sequentially provided as the phosphor layers 35 in each section. Has been placed.

  With the above configuration, a discharge cell is formed at a portion where the scan electrode 22, the sustain electrode 23, and the data electrode 32 intersect, and one pixel is formed by three adjacent discharge cells on which the phosphor layers 35 that emit light of each color are formed. Is configured. An area where the discharge cells constituting this pixel are formed becomes an image display area, and the periphery of the image display area becomes a non-display area where image display is not performed, such as an area where glass frit is formed.

FIG. 10 is an electrode array diagram of the PDP 10. In the row direction, n rows of scan electrodes SC _{1 to} SC _n (scan electrode 22 in FIG. 9) and n rows of sustain electrodes SU _{1 to} SU _n (sustain electrode 23 in FIG. 9) are alternately arranged in the column direction. Are arranged in m rows of data electrodes D _{1 to} D _m (data electrode 32 in FIG. 9). A discharge cell C _{i, j} including a pair of scan electrodes SC _i , sustain electrodes SU _i (i = 1 to n) and one data electrode D _j (j = 1 to m) is formed in the discharge space. The total number of discharge cells C is (m × n).

  In the PDP 10 having such a configuration, color display is performed by generating ultraviolet rays by gas discharge and exciting the phosphors of R, G, and B colors with the ultraviolet rays to emit light. Further, the PDP 10 divides one field period into a plurality of subfields, and performs gradation display by being driven by a combination of subfields that emit light. Each subfield includes an initialization period, an address period, and a sustain period, and different signal waveforms are applied to the electrodes in the initialization period, the address period, and the sustain period, respectively, in order to display image data.

  FIG. 11 is a diagram illustrating each drive voltage waveform applied to each electrode of the PDP 10. As shown in FIG. 11, each subfield has an initialization period, an address period, and a sustain period. In addition, in each subfield, almost the same operation is performed except that the number of sustain pulses in the sustain period is different in order to change the weight of the light emission period, and the operation principle in each subfield is almost the same. The operation will be described for only one subfield.

First, in the initialization period, for example, a positive is applied to the pulse voltage all scan electrodes SC ₁ to SC _n and scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to cover the to SU _n on the dielectric layer 24 Necessary wall charges are accumulated on the protective layer 25 and the phosphor layer 35. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing the discharge delay and generating the address discharge stably.

Specifically, in the first half of the initializing period, holds the data electrodes D ₁ to D _m, sustain electrodes SU ₁ to SU _n in each 0 (V), the scan electrodes SC ₁ to SC _n, data electrodes from D ₁ to D discharge start voltage or less voltage to _m Vi1, applying a ramp waveform voltage gradually rises toward the voltage Vi2 exceeding the discharge start voltage. While this ramp waveform voltage rises, the _first weak initializing discharge occurs between scan electrodes SC _{1 to} SC _n and sustain electrodes SU _{1 to} SU _n and data electrodes D _{1 to} D _m , respectively. Negative wall voltage is accumulated on scan electrodes SC _{1 to} SC _n, and positive wall voltage is accumulated on data electrodes D _{1 to} D _m and sustain electrodes SU _{1 to} SU _n . Here, the wall voltage at the top of the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode.

In the latter half of the initializing period, maintaining the sustain electrodes SU ₁ to SU _n to a positive voltage Ve, the scan electrodes SC ₁ to SC _n, equal to or less than the discharge start voltage with respect to sustain electrodes SU ₁ to SU _n voltage Vi3 Is applied with a ramp waveform voltage that gradually falls toward voltage Vi4 exceeding the discharge start voltage. During this period, a second weak initializing discharge occurs between the scan electrodes SC _{1 to} SC _n and the sustain electrodes SU _{1 to} SU _n and the data electrodes D _{1 to} D _m , respectively. Then, the negative wall voltage above scan electrodes SC ₁ -SC _n and the positive wall voltage above sustain electrodes SU ₁ -SU _n are weakened, and the positive wall voltage above data electrodes D ₁ -D _m is used for the write operation. It is adjusted to a suitable value. This completes the initialization operation (hereinafter, the drive voltage waveform applied to each electrode during the initialization period is abbreviated as “initialization waveform”).

Next, in the address period, scanning is performed by sequentially applying negative scan pulses to all the scan electrodes SC _{1 to} SC _n . Then, while scanning the scan electrodes SC _{1 to} SC _n , a positive address pulse voltage is applied to the data electrodes D _{1 to} D _m based on the display data. Thus, an address discharge is generated between scan electrodes SC _{1 to} SC _n and data electrodes D _{1 to} D _m, and wall charges are formed on the surface of protective layer 25 on scan electrodes SC _{1 to} SC _n .

Specifically, in the address period, scan electrodes SC _{1 to} SC _n are temporarily held at voltage Vscn. Next, in the address operation of the discharge cells C _{p, 1 to} C _{p, m} (p is an integer of ₁ to n), a scan pulse voltage (−Vad) is applied to the scan electrode SC _p and the data electrodes D ₁ to applying a positive write pulse voltage Vd to the D data electrode corresponding to a video signal to be displayed on the p-th row of the _m D _q (D _q data electrodes selected based on the video signal of the D ₁ to D _m) To do. Thus, an address discharge is generated in the discharge cells C _p and _q corresponding to the intersection between the data electrode D _q to which the address pulse voltage is applied and the scan electrode SC _p to which the scan pulse voltage is applied. By this address discharge, a positive voltage is accumulated on the scan electrode SC _p of the discharge cell C _{p, q} and a negative voltage is accumulated on the sustain electrode SU _p , and the address operation is completed. Thereafter, the same address operation is performed until the discharge cell C _{n, q} in the _n- th row _, and the address operation is completed.

In the subsequent sustain period, applying a sufficient voltage to maintain the discharge between the fixed period, the scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to SU _n. Thus, the scan electrodes SC ₁ discharge plasma between to SC _n and sustain electrodes SU ₁ to SU _n are generated, a period of time, to excite the phosphor to emit light layer. At this time, in the discharge space where the address pulse voltage is not applied in the address period, no discharge occurs and excitation light emission of the phosphor layer 35 does not occur.

Specifically, in the sustain period, scan electrodes SC _{1 to} SC _n are once returned to 0 (V), and then sustain electrodes SU _{1 to} SU _n are returned to 0 (V). Thereafter, positive sustain pulse voltage Vsus is applied to scan electrodes SC _{1 to} SC _n . At this time, the voltage between the discharge cell C _p having generated the address _discharge, the scan electrode SC _p upper part of _q and sustain electrode SU _p top, in addition to the positive sustain pulse voltage Vsus, scanning in the address periods electrode SC _p It is subject to and sustain electrode SU _p accumulated wall voltage in the upper, larger than the discharge start voltage, first sustain discharge is generated. In discharge cell C _{p, q} in which the sustain discharge has occurred, a negative voltage is accumulated on scan electrode SC _p so as to cancel the potential difference between scan electrode SC _p and sustain electrode SU _p when the sustain discharge occurs. A positive voltage is accumulated on the top of SU _p . Thus, the first sustain discharge is completed.

After the first sustain discharge, scan electrodes SC _{1 to} SC _n are returned to 0 (V), and then Vsus is applied to sustain electrodes SU _{1 to} SU _n . At this time, the voltage between the upper part of scan electrode SC _{p and} upper part of sustain electrode SU _p in discharge cell C _{p, q} in which the first sustain discharge has occurred is maintained for the first time in addition to positive sustain pulse voltage Vsus. In discharge, the wall voltage accumulated on scan electrode SC _p and sustain electrode SU _p is added to become higher than the discharge start voltage, and a second sustain discharge is generated. Hereinafter, similarly, by applying a sustain pulse alternately to the scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to SU _n, the discharge cell C _p having generated the address _discharge, the number of times of sustain pulses to _q The sustain discharge is continuously performed. Note that since no wall charges exist in the discharge cells in which no address discharge has occurred, the voltage in the discharge space does not reach the discharge start voltage even when the sustain pulse voltage Vsus is applied. Therefore, no discharge occurs.

  FIG. 12 is a block diagram showing an electrical configuration of a plasma display device incorporating the PDP 10. The plasma display device shown in FIG. 12 includes an AD converter 1, a video signal processing circuit 2, a subfield processing circuit 3, a data electrode drive circuit 4, a scan electrode drive circuit 5, a sustain electrode drive circuit 6, and a PDP 10. .

  The AD converter 1 converts the input analog video signal into a digital video signal. The video signal processing circuit 2 emits and displays the input digital video signal on the PDP 10 by a combination of a plurality of subfields having different light emission period weights, and controls each subfield from the video signal of one field. Convert to data. The subfield processing circuit 3 generates a data electrode drive circuit control signal, a scan electrode drive circuit control signal, and a sustain electrode drive circuit control signal from the subfield data created by the video signal processing circuit 2, and generates a data electrode Output to the drive circuit 4, the scan electrode drive circuit 5, and the sustain electrode drive circuit 6, respectively.

As described above, the PDP 10 includes n rows of scan electrodes SC _{1 to} SC _n (scan electrodes 22 in FIG. 9) and n rows of sustain electrodes SU _{1 to} SU _n (sustain electrodes 23 in FIG. 9) alternately. And m rows of data electrodes D _{1 to} D _m (data electrodes 32 in FIG. 9) are arranged in the column direction. A discharge cell C _{i, j} including a pair of scan electrodes SC _i , sustain electrodes SU _i (i = 1 to n) and one data electrode D _j (j = 1 to m) is formed in the discharge space (m Xn) One pixel is composed of three discharge cells that are formed and emit light in red, green, and blue colors.

The data electrode drive circuit 4 drives each data electrode Dj independently based on the data electrode drive circuit control signal. Scan electrode drive circuit 5 can drive each of scan electrodes SC _{1 to} SC _n independently. Then, each of the scan electrodes SC _{1 to} SC _n is independently driven based on the scan electrode drive circuit control signal. Sustain electrode drive circuit 6 can drive all sustain electrodes SU _{1 to} SU _n of PDP 10 together. Then, driving the sustain electrodes SU ₁ to SU _n based on the control signal the sustain electrode driving circuit.

  A specific circuit configuration of a plasma display panel (PDP) driving circuit for applying the driving voltage as described above will be described with reference to FIG. FIG. 13 shows a scan electrode drive circuit 5 and a sustain electrode drive circuit 6 which are part of the PDP drive circuit.

  Scan electrode driving circuit 5 includes sustain circuit 51, initialization circuit 52, write circuit 53, and recovery circuit 54. The sustain circuit 51 includes a first high-side sustain switch element S5, a first low-side sustain switch element S6, and a voltage source V1 having a voltage value Vsus. The recovery circuit 54 includes a first inductor L1, a first recovery capacitor C1, a first high-side recovery switch element S1, a first low-side recovery switch element S2, and a first high-side recovery diode D1. And a first low-side recovery diode D2.

The recovery circuit 54 performs power recovery and supply by causing LC resonance between the capacitive load of the PDP 10 (capacitive load generated in the scan electrodes SC _{1 to} SC _n ) and the first inductor L 1. During recovery of the power, the scan electrodes SC ₁ to SC _n the electric power stored in the capacitive load generated in a first recovery capacitor C1 through the first low side recovery diode D2 and the first low side recovery switch element S2 Move to. When power is supplied, the power stored in the first recovery capacitor C1 is transferred to the PDP 10 (scan electrodes SC _{1 to} SC _n ) via the first high-side recovery switch element S1 and the first high-side recovery diode D1. Move. Thus, scan electrodes SC _{1 to} SC _n are driven in the sustain period. Therefore, since the recovery circuit 54 drives the scan electrodes SC _{1 to} SC _n by LC resonance without supplying power from the power source during the sustain period, the power consumption is theoretically zero.

On the other hand, the sustain circuit 51 supplies power to the scan electrodes SC _{1 to} SC _n from the voltage source V 1 having the voltage value Vsus via the first high-side sustain switch element S 5 so that the scan electrodes SC _{1 to} SC _n have the voltage value. clamped Vsus, also by clamping to the ground potential scan electrodes SC ₁ to SC _n through the first low-side sustain switch element S6, to drive the scan electrodes SC ₁ to SC _n. Therefore, when driving scan electrodes SC _{1 to} SC _n by sustain circuit 51, the power supply impedance is very small and the rise and fall of the sustain pulse are steep, but the power consumption due to the power supplied from the power supply Occurs.

Thus, the sustain circuit 51 and the recovery circuit 54 switch the operation of the power recovery and the voltage clamp by switching each of the switch elements S1, S2, S5, and S6, and apply a sustain pulse to be applied to the scan electrodes SC _{1 to} SC _n. appear.

  Each of the switch elements S1, S2, S5, and S6 is a generally known element that performs a switch operation such as a MOSFET. A MOSFET is generally a parasitic diode called a body diode (a diode generated parasitically in the MOSFET structure) in parallel to the part that performs the switching operation, and the anode and cathode that are opposite to the part that performs the switching operation. (Hereinafter, such a configuration is referred to as “reverse parallel”). For this reason, the switch element can flow a current in the forward direction with respect to the body diode even when the switch operation is in a cut-off state. These switch elements may be provided with an antiparallel diode separately by using an element that performs a switch operation such as an IGBT instead of a MOSFET.

The initialization circuit 52 includes a high-side initialization switch element S11, a low-side initialization switch element S12, a first separation switch element S9, and a second separation switch element S10, which are composed of generally known elements similar to the above. , A voltage source V3 having a voltage value Vset, and a voltage source V2 having a negative voltage value (−Vad). Then, supplies power to the scan electrodes SC ₁ to SC _n through the high-side initialization switch element S11 from the voltage source V3, also the scanning electrodes SC ₁ to SC from the voltage source V2 through the low-side initialization switch element S12 _An electric power having a negative potential is supplied to _n to generate an initialization waveform.

The second separation switch element S10 is connected to the main discharge path from the voltage source V3 when the high-side initialization switch element S11 is conducting (hereinafter, the conduction state of the switch element is abbreviated as “ON”). The current is prevented from flowing into the voltage source V1 through the body diode (an antiparallel diode in the case of IGBT) of the first sustain switch element S5. The main discharge path, maintaining circuit 51, the initialization circuit 52, a write circuit 53, recovery circuit 54 is commonly connected, from the power and the scan electrodes SC ₁ to SC _n supplied to the scan electrodes SC ₁ to SC _n The path through which the recovered power flows. That is, the second separation switch element S10 is arranged to cut off the current as described above (hereinafter, the cut-off state of the switch element is abbreviated as “off”), and the high-side initialization switch element S11 is on. During the period, the second separation switch element S10 is turned off. Similarly, when the low side initialization switch element S12 is turned on, the first separation switch element S9 passes through the body diode of the first low side sustain switch element S6 and passes through the main discharge path from the ground potential. To prevent current from flowing into the. That is, the first separation switch element S9 is arranged to turn off the current as described above, and the first separation switch element S9 is turned off while the low-side initialization switch element S12 is on.

Thus, the initialization circuit 52 generates an initialization waveform as shown in FIG. That is, in the first half of the initializing period, generating a discharge start voltage below the voltage Vi1 to the data electrodes D ₁ to D _m, the voltage Vi2 exceeding the discharge start voltage, i.e. the ramp waveform gently rising towards the Vset is, the ramp waveform in the second half portion, the sustain electrodes SU ₁ to SU _n voltage exceeds the breakdown voltage from the voltage Vi3 to the discharge start voltage or less with respect to Vi4, namely that gently decreases to -Vad the initialization period generate.

  The write circuit 53 has two input ports, and has an IC 1 that is a scan driver that generates a scan pulse waveform by outputting any one of the powers input to the two input ports by a switch operation.

In the address period, scanning is performed by sequentially applying negative scan pulses to all the scan electrodes SC _{1 to} SC _n . Therefore, in the address period, the power of the voltage value Vscn supplied from the voltage source V4 is input to one input port of the scan driver IC1. Further, the low-side initialization switch element S12 of the initialization circuit 52 is turned on, and a negative voltage (−Vad) power is input from the voltage source V2 to the other input port of the scan driver IC1. One of the power supplied from the voltage source V4 and the power supplied from the voltage source V2 is selected by the scan driver IC1 and supplied to the scan electrodes SC1 to SCn. That is, the scan driver IC1 is a timing of applying negative scan pulse power from the voltage source V2, switches operative to supply power from the voltage source V4 is at other times to scan electrodes SC ₁ to SC _n .

  In order to electrically isolate sustain circuit 51 from initialization circuit 52 as described above, first separation switch element S9 and second separation switch are provided between maintenance circuit 51 and initialization circuit 52. The element S10 is inserted in series and the body diodes are opposite to each other (hereinafter, such a connection in which the diodes are opposite to each other is referred to as “back-to-back connection”). . With this configuration, if the first separation switch S9 and the second separation switch S10 are simultaneously turned off, the high-side initialization switch element S11 and the low-side initialization switch of the initialization circuit 52 to the maintenance circuit 51 are switched. Any of the current flowing to the element S12 and the current flowing from the high-side initialization switch element S11 and the low-side initialization switch element S12 of the initialization circuit 52 to the sustain circuit 51 can be cut off.

  This is for preventing the influence of the voltage source V1 of the sustain circuit 51 having a lower potential when the power is supplied from the voltage source V3 of the initialization circuit 52. This is for preventing the influence of a higher potential, that is, the ground potential (hereinafter abbreviated as “GND”) of the clamp portion of the sustain circuit 51, when power is supplied from the voltage source V2.

  When power is supplied from the voltage source V3, current may flow from the voltage source V3 having the voltage value Vset to the voltage source V1 having a lower potential through the main discharge path. In such a case, the potential of the main discharge path is lower than the potential Vset of the voltage source V3, and it becomes difficult to generate the original drive voltage waveform. Further, when power is supplied from the voltage source V2 having a negative voltage value (−Vad), current may flow from the GND of the clamp unit having a higher potential than the voltage source V2 to the voltage source V2 via the main discharge path. In such a case, the potential of the main discharge path rises higher than the negative voltage value (−Vad) of the voltage source V2, and it becomes difficult to generate the original drive voltage waveform.

However, the sustain circuit 51 is initialized by turning off the first separation switch S9 and the second separation switch S10 in the initialization period in which the scan electrodes SC _{1 to} SC _n are driven by the initialization circuit 52. The circuit 52 can be electrically isolated from the voltage source V2 and the voltage source V3, and such a current flow can be cut off. Therefore, the first separation switch element S9 and the second separation switch S10 are turned on only during the period when the scan electrodes SC _{1 to} SC _n are driven by the sustain circuit 51, and are turned off during other initialization periods. .

During the period in which scan electrodes SC _{1 to} SC _n are driven by sustain circuit 51, voltage source V2 and voltage source V3 are turned off by turning off high-side initialization switch element S11 and low-side initialization switch element S12. It can be electrically isolated from the main discharge path. This is because the high-side initialization switch element S11 is arranged so that the voltage source V3 has a higher potential than the voltage source V1, and the body diode blocks the current flowing from the voltage source V3 to the main discharge path. This is also because the low-side initialization switch element S12 is arranged so that the voltage source V2 has a potential lower than GND and the body diode blocks the current flowing from the main discharge path to the voltage source V2.

The sustain electrode drive circuit 6 also has a sustain circuit 61 and a recovery circuit 62 similar to the scan electrode drive circuit 5. The sustain circuit 61 includes a first high-side sustain switch element S7, a first low-side sustain switch element S8, and a voltage source V1 having a voltage value Vsus. The recovery circuit 62 includes a first inductor L2, a first recovery capacitor C2, a first high side recovery switch element S3, a first low side recovery switch element S4, and a first high side recovery diode D3. And a first low-side recovery diode D4. PDP10 capacitive load (sustain electrodes SU ₁ to SU _n in the resulting capacitive load) by LC resonance between the first inductor L2, power recovery and supply between a first recovery capacitor C2 and PDP10 It is the structure which performs. Since the operation is the same as that of the sustain circuit 51 and the recovery circuit 54 in the scan electrode drive circuit 5, description thereof will be omitted.

  Regarding the operation of the drive circuit having the above configuration, two types of conventional techniques will be described below. The first prior art is such that the ON / OFF timing of each switch element of the sustain circuit 51 and the recovery circuit 54 in the scan electrode driving circuit 5 recovers the power stored in the capacitive load of the PDP 10 to the maximum, or the recovered power Is set so that the maximum can be supplied to the panel.

FIG. 14 shows ON / OFF timings of the switch elements S1, S2, S5, and S6 of the sustain circuit 51 and the recovery circuit 54 in the sustain period, a voltage waveform applied to the scan electrode SCi, and a current waveform flowing through the first inductor L1. Indicates. In the state of each switch element in FIG. 14, the shaded portion indicates ON and the portion marked with “X” may be either ON or OFF, and the portion without a mark indicates OFF. SC _i is a voltage waveform applied to the scan electrode, and IL is a current waveform flowing in the first inductor L1 in which the direction of flow from the recovery circuit 54 to the sustain circuit 51 is positive. Hereinafter, the operations of sustain circuit 51 and recovery circuit 54 in the sustain period will be described by classifying from mode I to mode IV.

<Mode I>
In mode I, the first high-side recovery switch element S1 is turned on, and the other switch elements are turned off. By turning on the first high-side recovery switch element S1, an LC resonant circuit is formed by the capacitance of the PDP 10 and the first inductor L1, and power is supplied from the first recovery capacitor C1 to the PDP 10, The voltage of scan electrodes SC _{1 to} SC _n of PDP 10 increases. In order to perform the LC resonance operation, the current IL flowing through the first inductor L1 is a sinusoidal current. Since the first high-side recovery diode D1 is connected in series, the resonance current becomes negative, and at the same time, the diode D1 blocks the reverse current and the resonance operation stops.

<Mode II>
In mode II, the first high-side sustain switch element S5 is turned on. The first high-side recovery switch element S1 may be either on or off. By turning on the first high-side sustain switch element S5, the sustain voltage Vsus is supplied from the voltage source V1 to the scan electrodes SC _{1 to} SC _n . In order to supply the power recovered by the first recovery capacitor C1 to the PDP as much as possible, the first high-side sustain switch element S5 is turned on after the resonance operation is stopped. Since the inductance of the first inductor L1 and the capacitance of the PDP 10 are known, the resonance time is also known. Therefore, the timing for turning on the first high-side sustain switching element S5 when the recovered power is supplied to the PDP 10 to the maximum can be determined in advance.

<Mode III>
In mode III, the first high-side sustain switch element S5 is turned off, and the first low-side recovery switch element S2 is turned on. By turning on the first low-side recovery switch element S2, an LC resonance circuit is formed by the capacitance of the PDP 10 and the first inductor L1. Thereby, electric power is supplied from the PDP 10 to the first recovery capacitor C1, and the voltage of the scan electrode SC _i of the PDP 10 decreases. Because of the LC resonance operation, the current IL flowing through the inductor L1 is a sinusoidal current. Since the recovery diode D2 is connected in series, the current IL becomes positive, and at the same time, the diode D2 blocks the reverse current, and the resonance operation stops.

<Mode IV>
In mode IV, the first low-side sustain switch element S6 is turned on. The first low-side recovery switch element S2 may be either on or off. In order to recover the power of the PDP 10 to the maximum extent, the first low-side sustain switch element S6 is turned on after the resonance operation is stopped. Since the resonance time is also known in advance as described above, the timing for turning on the first low-side sustain switch element S6 can be determined in advance.

  In this way, the switch elements of the sustain circuit 51 and the recovery circuit 54 are turned on and off, and the first high-side sustain switch element S5 and the first low-side sustain switch element S6 are turned on at the timing described above. The panel power can be recovered and supplied to the maximum.

  In the mode IV period, sustain circuit 61 and recovery circuit 62 of sustain electrode drive circuit 6 operate in the same manner as modes I to III of scan electrode drive circuit 5. Accordingly, the voltage on the sustain electrode side rises and is clamped at the sustain voltage, and after the discharge current flows from the sustain electrode side to the scan electrode side, the voltage drops to near the ground potential (not shown). As described above, the scan electrode driving circuit 5 and the sustain electrode driving circuit 6 alternately repeat the operation from the mode I to the mode IV, so that the discharge in the sustain period continues and the PDP 10 emits light.

In the second conventional technique, in order to increase the light emission efficiency, control is performed so as to generate a discharge during the recovery operation (see, for example, Patent Document 1). That is, when the recovery circuit is operated and a current is supplied to the PDP by LC resonance, a discharge is generated. Since the LC resonance operation is being performed, the first inductor L1 acts to limit the discharge current. Therefore, the discharge becomes longer in time, and as a result, a plasma display device with high luminous efficiency and stable discharge can be obtained.
JP 2002-215084 A

  In recent years, PDPs with high luminous efficiency have been demanded from the viewpoint of promoting energy saving and reducing power consumption. For this purpose, PDPs with different discharge cell structures and discharge gas components have been developed. In the case of such a PDP that is different from the conventional one, there are cases where the conventional voltage and current supply methods cannot sufficiently exhibit the performance of the PDP, resulting in low luminous efficiency.

  For example, in the case of a PDP in which the luminous efficiency is increased by increasing the xenon partial pressure in the discharge gas, the emission time tends to be shorter than that of a PDP having a low xenon partial pressure. In this case, if the discharge current is limited, the current required for light emission is insufficient. Therefore, in the case of such a PDP, the light emission efficiency of the PDP does not increase as a result of the approach as in the second prior art.

  In addition, in the case of a PDP in which the light emission efficiency is increased by changing the structure of the discharge cell, the initial discharge start voltage is lower than that of the conventional PDP, and the voltage at which all discharge cells are discharged tends to be higher. In this case, since the voltage applied to the discharge cell exceeds the discharge start voltage when the recovery circuit is operating during the sustain period, the discharge starts during the recovery operation. However, if the sustain voltage is set small to avoid this, there arises a problem that all the discharge cells cannot be discharged.

  As described above, in order to drive a PDP having a discharge cell structure and a discharge gas composition different from the conventional one with high luminous efficiency, the conventional voltage and current supply method, that is, the conventional drive waveform is improved. It is necessary to drive the PDP with the generated driving waveform.

  Accordingly, the present invention pays attention to the difference in the structure of the discharge cell of the PDP and the state of the discharge gas as described above, and the display discharge of the PDP having a different relationship with the driving waveform from the conventional light emission efficiency in the sustain period. It is an object of the present invention to provide a plasma display panel drive circuit capable of optimally controlling the relationship between a drive waveform for supplying power and a charge / discharge current recovery operation and capable of being driven with high luminous efficiency. It is another object of the present invention to provide a plasma display device using such a PDP.

  A plasma display panel driving circuit according to the present invention applies a voltage to each electrode of a plasma display panel having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode orthogonal to the display electrode pair, and the display electrode pair And the display cells formed by the data electrodes are configured to cause display discharge, and power for starting and maintaining the display discharge in the plasma display panel is supplied from the sustain voltage power source through the switch element. A sustain circuit for supplying the electrode pair; a recovery capacitor that is charged and discharged by a current accompanying the display discharge; at least one inductor connected in series with the recovery capacitor; and for controlling the charge and discharge by the recovery capacitor And a recovery circuit having a switch part.

  In order to solve the above-mentioned problem, after the recovery circuit starts to supply power to the display electrode due to discharge of the recovery capacitor, the switch element is turned on so that the discharge power from the sustain circuit to the display electrode is reduced. The time until the supply is started is controlled to be 60% or less of the resonance time determined by the inductor and the capacitance of the plasma display panel.

  According to the plasma display panel driving circuit of the present invention having the above-described configuration, the discharge start voltage of the initial discharge cell of the PDP is supplied by turning on the sustain circuit and supplying the sustain voltage at an earlier stage than the resonance time elapses. The sustain voltage can be applied to the PDP without exceeding. As a result, since the impedance of the discharge current path can be reduced already when the discharge starts above the discharge start voltage, the discharge current required by the PDP can be sufficiently supplied. In addition, since the discharge start voltage is not exceeded during the recovery operation, a discharge with low light emission efficiency is not generated by mistake, so that the PDP can always be driven with high light emission efficiency, and the plasma display has low power consumption. Can be provided.

  In the plasma display panel driving circuit of the present invention having the above-described configuration, the switch element of the sustain circuit is turned on after the recovery circuit starts supplying power to the display electrode, and discharge power is supplied to the display electrode. The time until the start is preferably 15% or more of the resonance time determined by the inductor and the capacitance of the plasma display panel.

  The recovery capacitor preferably includes a first recovery capacitor for recovering power from the display electrode and a second recovery capacitor for supplying power to the display electrode. Preferably, the voltage value of the first recovery capacitor is set to be in a range of 30% to 80% of a voltage value for supplying discharge power to the display electrode. Preferably, the voltage value of the second recovery capacitor is set to be in a range of 5% to 40% of a voltage value for supplying discharge power to the display electrode.

  By providing two capacitors, one for collecting panel power and one for collecting panel power, as the capacitors used for the recovery operation in this way, when the panel power is supplied, the PDP can be used without exceeding the discharge start voltage of the initial discharge cell of the PDP. The operation of applying the sustain voltage is ensured. As a result, since the impedance of the discharge current path can be reduced already when the discharge starts above the discharge start voltage, the discharge current required by the PDP can be sufficiently supplied. In addition, the power recovery rate of the PDP can be further increased. As a result, it is possible to obtain a drive circuit that can drive the PDP with high luminous efficiency and can reduce power consumption of the plasma display device.

  The first recovery capacitor performs only the operation of supplying power from the PDP. Therefore, surplus power recovered from the PDP to the first recovery capacitor is regenerated to the sustain voltage power source via the boost converter, consumed by the regulator, or supplied to the second capacitor, It is preferable to stabilize the voltage of the capacitor. In order to fulfill this role, the voltage value of the first recovery capacitor is preferably set as described above.

  The second recovery capacitor performs only the operation of supplying power to the PDP. Therefore, it is preferable to stabilize the voltage of the second recovery capacitor by supplying insufficient power to the second recovery capacitor from the sustain voltage power source or from the address voltage power source. In order to fulfill this role, the voltage value of the second recovery capacitor is preferably set as described above.

  The plasma display apparatus of the present invention has a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode orthogonal to the display electrode pair, and a display cell is formed at each intersection of the display electrode pair and the data electrode. And a plasma display panel drive circuit having any one of the above-described configurations for driving the plasma display panel.

  In addition, the plasma display panel device of the present invention is suitable for using a PDP having higher luminous efficiency than the prior art, and preferably has a configuration having characteristics of a PDP having high luminous efficiency as follows.

  That is, the plasma display panel is preferably filled with a discharge gas having a xenon concentration of 15% or more. Alternatively, the plasma display panel preferably has a discharge current peak value at a maximum load of 100 amperes or more. Alternatively, the plasma display panel preferably has an electrode width of 200 microns or less. Alternatively, the plasma display panel preferably has a capacitance of 0.001 microfarad to 1 microfarad. Alternatively, the plasma display panel is preferably filled with a gas having a discharge gas pressure of 300 Torr to 600 Torr.

  A PDP having at least one of these characteristics is a PDP with high luminous efficiency. In order to drive such a PDP with high luminous efficiency, a plasma display panel driving circuit capable of supplying a discharge current having a high frequency and a high current peak value is required. Since the plasma display panel drive circuit having the above configuration supplies the sustain voltage at the time when discharge starts, it can supply a discharge current having a high frequency and high current peak value. Therefore, since the PDP having the above-described characteristics has sufficient supply capability for driving with high luminous efficiency, the PDP can be driven with high luminous efficiency. In addition, since it is possible to prevent the discharge start voltage from being exceeded in the operation of supplying power from the recovery circuit to the PDP, the PDP does not cause discharge with low light emission efficiency. As a result, it is possible to obtain a plasma display panel device in which the PDP is always driven with high luminous efficiency.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
The PDP drive circuit according to the first embodiment of the present invention has a specific circuit configuration similar to that of the conventional example shown in FIG. Therefore, FIG. 13 is also referred to in the description of this embodiment. The features of this embodiment are shown in the waveform diagram of FIG. FIG. 1 shows on / off timings in the sustain periods of the switch elements S1, S2, S5 and S6 of the sustain circuit 51 and the recovery circuit 54. FIG. In the present embodiment, the on / off timing of each switch element is set differently from that of the prior art.

  In the sustain period, the operation of applying the sustain voltage to the panel and the operation of collecting or resupplying the power stored in the panel capacitance are repeated. Here, one repetitive operation in the sustain period will be described by dividing it from the mode I to the mode IV. In addition, regarding the on / off state of each switch element in FIG. 1, the shaded portion indicates on, x indicates that either may be on or off, and otherwise indicates off.

<Mode I>
In mode I, the first high-side recovery switch element S1 is turned on, and the other switch elements are turned off. By turning on the first high-side recovery switch element S1, an LC resonant circuit is formed by the capacitance of the PDP 10 and the first inductor L1, and power is supplied from the first recovery capacitor C1 to the PDP 10, The voltage of scan electrodes SC _{1 to} SC _n of PDP 10 increases. During the mode I period, the potential of the sustain electrode driving circuit 6 is the ground potential.

<Mode II>
In mode II, the first high-side sustain switch element S5 is turned on. The first high-side recovery switch element S1 may be either on or off, but is turned off before shifting to mode III. By turning on the first high-side sustain switch element S5, the sustain voltage Vsus is supplied from the voltage source V1 to the scan electrodes SC _{1 to} SC _n .

  In the prior art, the timing at which the first high-side sustain switch element S5 is turned on, that is, the time T1 from when the first high-side recovery switch element S1 is turned on to when the first high-side sustain switch element S5 is turned on. Is set to be substantially the same as the resonance time determined by the capacitance of the PDP 10 and the first inductor L1.

On the other hand, in the present embodiment, the first high-side sustain switch element S5 is turned on at a timing when the time T1 is always shorter than the resonance time. That is, the first high-side sustain switching element S5 is turned on before reaching the resonance time as compared with the prior art. In this way, when the voltage supplied to the scan electrodes SC _{1 to} SC _n of the PDP 10 reaches the discharge start voltage, the voltage is supplied from the recovery circuit 54, and when the discharge starts beyond the discharge start voltage, The sustain voltage Vsus is supplied from the voltage source V1 via the first high-side sustain switch element S5. Therefore, unlike the prior art, the current required for the discharge is not limited by the inductor L1 of the recovery circuit 54, so that the discharge current required by the PDP 10 can be supplied. Thereby, since the PDP 10 can always emit light in a state with high light emission efficiency, a plasma display device with high efficiency and low power consumption can be provided. During the period of mode II, the potential of sustain electrode driving circuit 6 is the ground potential.

<Mode III>
In mode III, the first high-side sustain switch element S5 is turned off, and the first low-side recovery switch element S2 is turned on. By turning on the first low-side recovery switch element S2, an LC resonance circuit is formed by the capacitance of the PDP 10 and the first inductor L1, power is supplied from the PDP 10 to the first recovery capacitor C1, and the PDP 10 The voltage of the scan electrode decreases. During the period of mode III, the potential of sustain electrode drive circuit 6 is the ground potential.

<Mode IV>
In mode IV, the first low-side sustain switch element S6 is turned on. The timing at which the first low-side maintenance switch element S6 is turned on is a time T0 after the first low-side recovery switch element S2 is turned on. The time T0 may be the same as the time T1 which is the mode I time, or may be the same as the LC resonance time as in the prior art. This is because the PDP 10 does not discharge at the timing of transition from mode III to mode IV. The first low-side recovery switch element S2 may be turned on or off, but is turned off before the mode I is shifted.

  On the other hand, during the mode IV, the sustain circuit 61 and the recovery circuit 62 included in the sustain electrode drive circuit 6 operate in the same manner as the scan electrode drive circuit 5 operates from mode I to mode III in FIG. Also good. That is, when the second high-side recovery switch element S3 in the recovery circuit 62 of the sustain electrode drive circuit 6 is turned on, the voltage of the sustain electrode is increased by the LC resonance operation similar to that in mode I. The sustain voltage Vsus is supplied by turning on the second high-side sustain switch element S7 until the discharge starts when the voltage of the sustain electrode reaches the discharge start voltage (operation similar to mode II). At this time, a discharge current flows from the sustain electrode side to the scan electrode side. After the discharge is finished, the second low-side recovery switch element S4 in the recovery circuit 62 of the sustain electrode drive circuit 6 is turned on, so that the voltage of the sustain electrode is lowered by the LC resonance operation similar to mode III.

  By operating the sustain electrode driving circuit 6 in this way, the PDP 10 can be driven with high efficiency for the same reason as described in the mode II even when a discharge current flows from the sustain electrode side to the scan electrode side. Is possible. Thus, in the period of mode IV, sustain electrode drive circuit 6 may perform the same operation as scan electrode drive circuit 5 operates from mode I to mode III.

  As described above, the present embodiment causes the recovery circuit to perform an LC resonance operation when the discharge start voltage is lower than the discharge start voltage, and during the discharge delay period from when the discharge start voltage is exceeded to when the discharge actually starts, The high-side sustain switch element is turned on, and the voltage applied to the PDP is set to the sustain voltage Vsus. As a result, the PDP can emit light with high efficiency. Therefore, by using the PDP drive circuit of this embodiment, a plasma display device with high PDP light emission efficiency and low power consumption can be provided.

  The relationship between the time T1 from when the first recovery switch element S1 is turned on to the time when the first high-side sustain switch element S5 is turned on and the LC resonance time is approximately T1 ≦ (0.6 × resonance time). ), It is preferable that the first high-side sustain switch element S5 is in the vicinity of the discharge start voltage before and after the first high-side sustain switch element S5 is turned on.

  FIG. 2 is a diagram showing the relationship between the ratio of the time T1 to the LC resonance time and the relative value of the luminous efficiency with the maximum value being 1. Thus, the luminous efficiency is maximized when the time T1 is 60% or less of the LC resonance time. In the region where the time T1 exceeds 60%, the discharge starts at the stage of mode I, so that the panel light emission efficiency is drastically lowered for the reason described above. On the other hand, as the ratio of time T1 decreases, the power recovery efficiency of the PDP decreases, so that power consumption increases. Therefore, the region where the ratio of the time T1 is 40% to 60% is a region where the light emission efficiency of the PDP is high and the power recovery efficiency is not lowered so much, and the power recovery operation in this region is preferable.

  The ideal ratio of the time T1 at which the luminous efficiency is maximized varies depending on the discharge gas of the PDP, the structure of the discharge cell, etc., but if it is in the above range, the luminous efficiency is sufficiently high in practical use. Is obtained. According to the present embodiment, by operating the recovery circuit and the maintenance circuit in such a region of the ratio of time T1, it is possible to provide a PDP drive circuit with high light emission efficiency and low power consumption.

  Note that the specific circuit configurations of the initialization circuit and the writing circuit in the initialization period and the writing period may be the same as or different from those in the related art. In the present embodiment, voltage waveforms and circuits in the initialization period and the writing period are not limited to the configurations in FIGS.

(Embodiment 2)
The overall structure of the PDP drive circuit according to the second embodiment of the present invention is substantially the same as that of the first embodiment, but the recovery circuit 54 in the circuit shown in FIG. 13 is similar to the recovery circuit 54A shown in FIG. Has an improved configuration. The other parts of the PDP drive circuit can be configured in the same manner as the circuit shown in FIG.

  The recovery circuit 54A shown in FIG. 3 is different from the first embodiment in that a circuit (step-up converter) for adjusting the voltage of the first recovery capacitor C1 is added. That is, one end of the second inductor L3 is connected to the first recovery capacitor C1, and the other end is connected to the drain terminal of the boost switch element S13. The anode terminal of the boost diode D5 is connected to the drain terminal of the boost switch element S13, and the cathode terminal of the boost diode D5 is connected to the voltage source V5. The source terminal of the boost switch element S13 is connected to the ground potential.

FIG. 4 is a waveform diagram showing voltage waveforms applied to the scan electrodes SC _{1 to} SC _n of the PDP 10 during the sustain period, and on / off states of the switch elements of the sustain circuit 51 and the recovery circuit 54 in the scan electrode driving circuit 5. . The difference from the first embodiment is that an on / off state of the boost switch element S13 is added. The boost switch element S13 is turned on during the mode IV. In mode IV, the boost switch element S13 is turned on for a while and then turned off. When turned on, a current flows from the first recovery capacitor C1 to the second inductor L3. This current flows through the boost switch element S13 to the ground potential. By turning off immediately after turning on, the current flowing through the second inductor L3 is supplied to the voltage source V5 via the boosting diode D5 when the boosting switch element S13 is turned off. This operation is performed once or a plurality of times during the mode IV, and the voltage of the first recovery capacitor C1 is controlled to a desired voltage. As a result, the voltage of the first recovery capacitor C1 at the time of transition to mode I can be made lower than the voltage at the time of mode IV.

  By controlling in this way, even when the LC resonance operation is being performed in mode II, when the first high-side sustain switch element S5 is forcibly turned on, the sustain voltage due to the voltage being superimposed on the scan electrode of the PDP 10 Overshoot can be prevented. As a result, a more stable sustain voltage can be supplied to the PDP 10, and a recovery circuit with a smaller loss than that of the first embodiment can be provided. That is, since the power recovery efficiency can be increased, a plasma display device with low power consumption can be provided.

  Further, since the period T2 in mode I and the period T0 in mode III are not equal, the power to charge the first recovery capacitor C1 and the power to be discharged are different, and repeating the sustain discharge operation results in the first recovery The voltage of the capacitor C1 increases. Therefore, in order to prevent the overshoot, it is preferable to reduce the voltage of the first recovery capacitor C1 in the mode IV.

Further, in _order to make the voltage applied to the scan electrodes SC _{1 to} SC _n less than the discharge start voltage at the end of the mode I operation, the voltage of the first recovery capacitor C1 is reduced in advance before the mode I operation starts. Also good. If the voltage is equal to or lower than the discharge start voltage at the end of the operation in mode I, the operation time in mode I does not need to be shorter than the resonance time, and may be substantially the same as the resonance time. That is, time T2 may be substantially the same as time T0. In this case, the power recovery efficiency is increased as in the prior art. Therefore, discharge in mode I does not occur and high light emission efficiency is obtained, and at the same time, the power recovery efficiency is high, so that a more preferable PDP drive circuit can be provided.

  The operation of each switch element S1, S2, S5, S6 may be the same as in the first embodiment. Further, even if the recovery circuit 62 of the sustain electrode driving circuit 6 is configured in the same manner as the circuit shown in FIG. 3 and operated as shown in FIG. 4, the same effects as described above can be obtained.

  Further, the on / off operation of the boost switch element S13 in the mode IV is not limited to the mode shown in FIG. If the boost switch element S13 operates so that the potential of the first recovery capacitor C1 becomes a desired potential, it can be set as appropriate. Therefore, there is no limit to the time for turning on or off, and the number of on / off times. Further, it is not always necessary to turn on and off at least once in one maintenance operation.

  Further, the on / off operation of the boost switch element S13 may be performed during the mode II period. Since the LC resonance operation time of mode III is determined by itself, the power recovered from the PDP to the first recovery capacitor C1 in mode III is also known in advance. Therefore, calculating the desired first recovery capacitor C1 voltage at the start of mode III from the desired first recovery capacitor C1 voltage at the start of mode I and the power recovered in mode III. Is possible. As a result, the step-up switch element S13 can be turned on and off during the mode II period so that the desired voltage is obtained when the mode III is started.

  Further, the voltage value of the voltage source V5 in FIG. 3 can be appropriately set as long as the voltage source is larger than the maximum value of the voltage applied to the first recovery capacitor C1. Therefore, the voltage source V5 may be, for example, a voltage source that supplies the voltage Vd to the data electrode driving circuit, or a voltage source that supplies the sustain voltage Vsus.

(Embodiment 3)
FIG. 5 is a specific circuit diagram of the recovery circuit 54B according to the third embodiment of the present invention. The present embodiment is characterized by the configuration of the recovery circuit 54B, and relates to another suitable circuit configuration for achieving the various objects described in the second embodiment.

  In addition to the configuration of the recovery circuit 54 shown in FIG. 13, the recovery circuit 54B includes a second recovery capacitor C3 that lowers the voltage of the first recovery capacitor C1 and a second recovery switch element S14. Specifically, the drain terminal of the second recovery switch element S14 is connected to one end of the first recovery capacitor C1 that is not on the ground potential side. The source terminal of the second recovery switch element S14 is connected to the second recovery capacitor C3. This connection point is connected to the drain terminal of the first high-side recovery switch element S1. The other end of the second recovery capacitor C3 is connected to the ground potential.

  The on / off operation of the second recovery switch element S14 is the same as the operation of the boost switch element S13 shown in FIG. 4 (see FIG. 4). That is, in the second embodiment, the boost switch element S13 is operated so as to control the voltage of the first recovery capacitor C1, whereas in the third embodiment, the second recovery switch element S14 is The second recovery capacitor C3 is operated to control the voltage. By operating the second recovery switch element S14 in this way, the charge is transferred from the first recovery capacitor C1 to the second recovery capacitor C3 via the second recovery switch element S14. The voltage of the recovery capacitor C3 can be controlled to a desired voltage.

  Therefore, the recovery circuit 54B can obtain the same effect as described in the second embodiment. That is, when the recovery circuit 54B starts operation in mode I, the voltage of the second recovery capacitor C3 becomes lower than the voltage of the first recovery capacitor C1 when mode III ends. Accordingly, in the mode I, after the recovery circuit starts the LC resonance operation, the scan electrode of the PDP 10 is forced to turn on the first high-side sustain switch element S5 even during the LC resonance operation in the mode II. It is possible to prevent overshoot of the sustain voltage due to voltage superposition with respect to. As a result, a more stable sustain voltage can be supplied to the PDP, and waste of voltage applied to the PDP can be eliminated.

Further, it is possible to prevent the voltage increase of the first recovery capacitor C1 that occurs because the period T1 of mode I and the period T0 of mode III are not equal. Further, in _order to set the voltage applied to scan electrodes SC _{1 to} SC _n to the discharge start voltage or less at the end of the mode I operation, the voltage of the second recovery capacitor C3 is reduced in advance before the mode I operation starts. You can also. As a result, a recovery circuit with a smaller loss than that of Embodiment 1 can be provided, and a plasma display device with low power consumption can be provided.

  The operation of each switch element S1, S2, S5, S6 may be the same as in the first embodiment. Further, even if the recovery circuit 62 of the sustain electrode drive circuit 6 is configured in the same manner as the circuit of FIG. 5 and is operated as shown in FIG. 4, the same effects as described above can be obtained.

  Further, the on / off operation of the second recovery switch element S14 in the mode IV is not limited to the mode shown in FIG. If the second recovery switch element S14 operates so that the potential of the second recovery capacitor C3 becomes a desired potential, it can be operated as appropriate. Therefore, there is no limit to the time for turning on or off, and the number of on / off times. Further, it may be operated during the mode II or mode III period.

The desired voltage value of the second recovery capacitor C3 is not less than 5% and not more than 40% of the sustain voltage Vsus. The reason why the desired voltage value has a range is that an appropriate voltage value is different for each of the above-described purposes. For example, in order to ensure that the voltages of the scan electrodes SC _{1 to} SC _n become equal to or lower than the discharge start voltage at the time when the mode I operation ends and the mode II operation starts, the discharge start voltage Vf It is necessary to set the desired voltage Vc3 so that the relationship of the desired voltage Vc3 of the second recovery capacitor C3 is Vc3 <(Vf−wall voltage) / 2. In the operation in the conventional sustain period, since (Vf−wall voltage) is a value close to the sustain voltage Vsus, the relationship is Vc3 <Vsus / 2. Since (Vf−wall voltage) is actually smaller than Vsus, in order to achieve the above object, the desired voltage of the second recovery capacitor C3 is, for example, 40% or less of the sustain voltage Vsus. desirable. In addition, in order to prevent voltage overshoot when the mode II is shifted to, the desired voltage value of the second recovery capacitor C3 must be considerably reduced. For example, it has been found by the present inventors that this overshoot does not occur if Vsus is set to 5% to 15%.

  As described above, the desired voltage value is set according to the purpose, but in any case, it may be set within the above-described value range. On the other hand, the desired voltage value of the first recovery capacitor C1 is, for example, 30% to 80% of the sustain voltage Vsus. Within this voltage value range, when performing the power recovery operation from the PDP in mode III, the recovered power is almost the same and maximum regardless of the voltage value of the first recovery capacitor C1. However, it has been found by the examination of the present inventors.

  Note that the third embodiment has an advantage that the circuit can be reduced in size because it has no inductor as compared with the second embodiment.

(Embodiment 4)
FIG. 6 is a specific circuit diagram of the recovery circuit 54C according to the fourth embodiment of the present invention. The other parts of the PDP drive circuit can be configured in the same manner as the circuit shown in FIG. In the present embodiment, a second recovery capacitor C3 is added to the recovery circuit 54A of the second embodiment shown in FIG. 3, and a control circuit 55 is connected to the second recovery capacitor C3. . Specific circuit configurations of the control circuit 55 are shown in FIGS.

FIG. 8 shows a voltage waveform applied to the scan electrodes SC _{1 to} SC _n of the PDP 10 during the sustain period, and the on / off states of the switch elements of the sustain circuit 51 and the recovery circuit 54C in the scan electrode drive circuit 5 in this embodiment. FIG.

  The feature of this embodiment is that the recovery capacitors have two configurations and the voltages of the respective capacitors can be controlled independently. That is, the first recovery capacitor C1 is involved only in the operation of charging from the PDP 10, and the second recovery capacitor C3 is involved only in the operation of discharging the PDP 10. An independently operable circuit for controlling the voltage of each capacitor is provided. The on / off operations of the switch elements S1, S2, S5, and S6 in the present embodiment are the same as those in the first to third embodiments, and thus the description thereof is omitted.

  The operation of the boost switch S13 in the present embodiment will be described. The step-up switch S13 controls the voltage of the first recovery capacitor C1 to be a desired voltage at the start of mode III. The on / off operation of the boost switch element S13 is different from the second embodiment in that it may be in any period of mode IV, mode I, and mode II. Further, the number of on / off operations, the waveform, the period, the on time, and the off time are not limited to those shown in FIG. Since the first recovery capacitor C1 is only charged from the PDP 10, the voltage of the first recovery capacitor C1 increases as the sustain operation is repeated. Therefore, the voltage of the first recovery capacitor C1 is controlled to a desired voltage by operating the boost switch S13 so as not to become overvoltage.

  Next, the control circuit 55 in the present embodiment will be described. The control circuit 55 performs control so that the voltage of the second recovery capacitor C3 becomes a desired voltage at the start of mode I. Unlike the second embodiment, since the recovery capacitor is configured independently, the operation of the control circuit 55 may be any period of mode II, mode III, and mode IV. Further, the number of on / off operations, the waveform, the period, the on time, and the off time are not limited to those shown in FIG. The specific circuit configuration of the control circuit 55 is a circuit as shown in FIGS. 7A to 7D, or a circuit combining these.

  Each of the control circuits 55 includes a switch element S15, and the operation of the control circuit 55 is determined by the on / off operation of the switch element S15. That is, the switch element S15 is turned on and off within the range of the mode period described above.

  The circuit of FIG. 7A is a step-down circuit composed of a third inductor L4, a diode D6, and a switch element S15. In this step-down circuit, the voltage of the second recovery capacitor C3 is higher than a desired voltage. When it is low, it is used to supply power from the voltage source V6 to the second recovery capacitor C3. The circuit in FIG. 7B has a configuration in which the step-down circuit in FIG. 7A is simplified. The circuit shown in FIG. 7C is a booster circuit. The booster circuit supplies power from the second recovery capacitor C3 to the voltage source V6 when the voltage of the second recovery capacitor C3 is higher than a desired voltage. Used to do. The circuit shown in FIG. 7D is a regulator circuit including a switch element S15 and a resistor R1, and is used when the voltage of the second recovery capacitor C3 is higher than a desired voltage.

  In any of the circuits of FIGS. 7A to 7D, the output voltage of the voltage source V6 may be a voltage higher than the maximum value of the voltage of the second recovery capacitor C3. For example, the voltage source V1 that supplies the sustain voltage Vsus or the voltage source that supplies the voltage Vd of the data electrode driving circuit may be used. The voltage source V5 is the same as that described in the second embodiment. The desired voltage values of the first recovery capacitor C1 and the second recovery capacitor C3 are the same as those in the third embodiment.

By using a circuit as shown in this embodiment, the voltage of the recovery capacitor at the start of the recovery operation of the high-side recovery operation and the low-side recovery operation can be controlled independently. In particular, by controlling the voltage of the recovery capacitor connected to the high-side recovery circuit, it is possible to prevent the discharge start voltage from being reached during the recovery operation. In that case, by always turning on the high-side sustain switch element S5 without forcibly turning on the high-side sustain switch element S5 in a time shorter than the resonance time, the discharge start voltage is reliably ensured in the mode I period. The discharge start voltage can be set to be exceeded for the first time in the mode II period. That is, by controlling the voltage of the recovery capacitor connected to the high-side recovery circuit to be low, even if the high-side sustain switch element S5 is turned on after a time substantially equal to the resonance time has elapsed, the discharge is performed in the mode I period. The starting voltage is not reached.
Thereby, it is possible to provide plasma display panel driving with a higher degree of freedom. In addition, a plasma display device with high luminous efficiency can be provided.

(Embodiment 5)
The plasma display device according to the fifth embodiment of the present invention is configured using any of the PDP drive circuits described in the first to fourth embodiments. When the plasma display panel itself has the following characteristics, high luminous efficiency can be obtained by using any of the PDP drive circuits of Embodiments 1 to 4. Hereinafter, the advantages of using the above PDP drive circuit will be described while listing the features of the plasma display panel itself.

  The setting of the sustain voltage Vsus during the sustain discharge period will be described. In general, in a PDP, the discharge start voltage and the discharge end voltage of m × n discharge cells vary. When the applied voltage is increased from the state where all the cells are turned off, one discharge cell is turned on first. As the applied voltage is further increased, many discharge cells are lit and finally all cells are lit. The voltage applied when the first one starts discharging is called Vf1, and the voltage applied when all the cells are lit is called Vfn. In addition, when the applied voltage is lowered from the state where all the cells are turned on, one discharge cell is turned off first. When the applied voltage is further decreased, many discharge cells are extinguished and finally all cells are extinguished. The applied voltage when the first one is turned off is called Vsmn, and the applied voltage when all the cells are turned off is called Vsm1. The voltage Vsus applied during the sustain discharge period is generally set to a value larger than Vsmn and smaller than Vf1. Further, there is a relationship of Vsm1 <Vsmn <Vf1 <Vfn.

  The difference between Vf1 and Vfn tends to increase as the xenon partial pressure contained in the discharge gas increases. Therefore, Vsus must be set to a value close to Vf1. This is because all cells do not light properly unless the sum of the wall voltage and Vsus exceeds Vfn. Since the wall voltage cannot be increased too much even if the xenon partial pressure increases, it is necessary to bring Vsus closer to Vf1 as the xenon partial pressure increases. Therefore, when the xenon partial pressure is large, the recovery operation shown in the first embodiment, that is, the voltage applied to the PDP in the second half of mode I tends to exceed Vf1, and the discharge starts, resulting in an operation with low luminous efficiency. End up. Therefore, the PDP drive circuit of the present invention has a remarkable effect when driving a PDP having a large xenon partial pressure. For example, in order to increase the xenon partial pressure, a PDP having a discharge gas whose xenon concentration exceeds 15% is driven. The xenon concentration may be up to 100% PDP. Further, since the PDP has a tendency that the difference between Vfn and Vf1 increases as the pressure of the discharge gas increases, the PDP drive circuit of the present invention has a remarkable effect even when driving a PDP having a high discharge gas pressure. Have For example, this is a case where a PDP having a discharge gas whose discharge gas pressure exceeds 300 Torr is driven.

  Note that if the discharge gas pressure is too high, light emission will not occur unless the value of the voltage Vsus applied during the sustain period is increased, so it is generally set to about atmospheric pressure. According to the study by the present inventors, at a pressure exceeding 600 Torr, circuit loss due to the need to increase the sustain voltage Vsus increases, and as a result, the luminous efficiency tends to decrease at a PDP exceeding 600 Torr. showed that. Accordingly, the discharge gas pressure of the PDP is desirably 600 Torr or less.

  Further, based on the present embodiment, even when a plasma display device is configured in which a PDP having higher luminous efficiency as the discharge current is larger is driven by any of the PDP driving circuits of the first to fourth embodiments, the luminous efficiency is also improved. High characteristics can be obtained. That is, a PDP that requires a peak current exceeding 100 amperes at the maximum load cannot completely supply the discharge current from the inductor of the recovery circuit, so that the light emission efficiency is inevitably lowered in the conventional drive circuit. However, according to the present embodiment, even in a PDP that requires a discharge current exceeding 100 amperes, the discharge current is not limited by the PDP drive circuit, so that high light emission efficiency can be obtained.

  Further, based on the present embodiment, even when a plasma display device that drives a PDP having a small bus electrode width of the scan electrode and the sustain electrode by the PDP drive circuit of any of the first to fourth embodiments is configured to emit light. Features with high efficiency are obtained. As the width of the electrodes used for the scan electrode and the sustain electrode of the PDP becomes narrower, the discharge intensity tends to increase. In particular, a PDP having a bus electrode width of 200 microns or less has a property that the discharge intensity is high and the light emission efficiency increases as the discharge current increases. The PDP drive circuit of the present embodiment can be driven with extremely high light emission efficiency, particularly when driving a PDP having a bus electrode width of 200 microns or less, so that the effect is remarkable for obtaining high light emission efficiency. is there. On the other hand, if the bus electrode width is too narrow, the electrode resistance value increases, resulting in an increase in resistance loss in the panel. According to the study by the present inventors, the resistance loss increases as the bus electrode width becomes narrower. As a result, the PDP having an electrode width of 100 microns or less tends to decrease the light emission efficiency. Accordingly, it is desirable that the electrode width used for the scan electrode and the sustain electrode of the PDP be 100 microns or more and 200 microns or less.

  In addition, based on this embodiment, when a plasma display device that drives a PDP having a small capacitance with any of the PDP drive circuits of Embodiments 1 to 4 is configured, a feature with high luminous efficiency is obtained. It is done. The charge stored in the capacitance of the PDP is also used during discharge. Therefore, the smaller the PDP capacitance is, the smaller the amount of capacitance that can cover the discharge current from the capacitance, so the discharge current must be supplied from the drive circuit. According to the present embodiment, even when driving a PDP having a small capacitance as described above, a sufficient discharge current can be supplied, so that the discharge current of the PDP is not limited. That is, the PDP drive circuit of the present invention has a remarkable effect even when driving a PDP having a small capacitance.

The above-described PDP having a small capacitance is particularly effective in the case of 1 microfarad or less, for example. If the capacitance is too small, the load dependency tends to increase. That is, when all the pixels in one horizontal row are caused to emit light, that is, when all the cells of Ci _{, 1 to} Ci _{, m} in FIG. Compared with this, a display defect occurs in which the luminance of the i row is lowered. According to the study by the present inventors, as the capacitance decreases, the luminance difference between a row with a low lighting rate and a row with a high lighting rate increases, resulting in a capacitance of 0.001. It was found that the brightness difference can be recognized visually with a PDP of microfarad or less. Therefore, it is desirable that the capacitance of the PDP is 0.001 microfarad or more.

  As described above, the PDP drive circuit of the present invention is particularly useful when driving a plasma display panel having the above characteristics from the viewpoint of providing a plasma display device with high luminous efficiency.

  In any of the first to fifth embodiments described above, the initialization circuit and the write circuit that are components of the scan electrode driving circuit are not limited to the configurations shown in the prior art. The present invention is characterized in the operation and circuit configuration of the sustain circuit and the recovery circuit during the sustain period, and is not limited to the circuit configuration of the initialization circuit and the write circuit, and the drive waveform in the initialization period and the write period. It is.

  In any of the first to fifth embodiments described above, the circuit configuration has been described on the assumption of a MOSFET, but it goes without saying that a transistor such as an IGBT may be used. Further, a transistor using a material different from Si, such as SiC or GaN, may be used, and various elements can be used as long as they have a function of conducting or blocking current.

  The PDP driving circuit and the plasma display device of the present invention are suitable for a wall-mounted television and a large monitor because they have high luminous efficiency and an effect of reducing power consumption.

Regarding the operation of the PDP drive circuit according to the first embodiment of the present invention, the voltage waveform applied to the scan electrode during the sustain period, and the ON / OFF of each switch element included in the sustain circuit and the recovery circuit in the scan electrode drive circuit Waveform diagram showing the timing of The graph which shows the relationship of the luminous efficiency with respect to the ratio of the operation time of the collection circuit which comprises the PDP drive circuit, and the resonance time Circuit diagram of recovery circuit included in PDP drive circuit in Embodiment 2 of the present invention Regarding the operation of the PDP drive circuit, a waveform diagram showing voltage waveforms applied to the scan electrodes during the sustain period, and on / off timing of each switch element included in the sustain circuit and the recovery circuit in the scan electrode drive circuit Circuit diagram of recovery circuit included in PDP drive circuit in Embodiment 3 of the present invention Circuit diagram of recovery circuit included in PDP drive circuit in embodiment 4 of the present invention Circuit diagram of control circuit included in recovery circuit of same PDP drive circuit Regarding the operation of the PDP drive circuit, a waveform diagram showing voltage waveforms applied to the scan electrodes during the sustain period, and on / off timing of each switch element included in the sustain circuit and the recovery circuit in the scan electrode drive circuit The perspective view which shows the structure of PDP of a prior art example. The figure which shows the electrode arrangement | sequence of PDP of a prior art example Waveform diagram showing voltage waveforms applied to each electrode of a conventional PDP during one subfield period Block configuration diagram showing the configuration of a conventional plasma display device for each functional block Circuit diagram showing scan electrode drive circuit and sustain electrode drive circuit in a conventional PDP drive circuit Regarding the operation of the PDP drive circuit, a waveform diagram showing voltage waveforms applied to the scan electrodes during the sustain period, and on / off timing of each switch element included in the sustain circuit and the recovery circuit in the scan electrode drive circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 A / D converter 2 Video signal processing circuit 3 Subfield processing circuit 4 Data electrode drive circuit 5 Scan electrode drive circuit 6 Sustain electrode drive circuit 10 PDP
20 Front plate 21 Flexible wiring board 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protective layer 26 Chassis member 30 Back plate 31 Flexible wiring board 32 Data electrode 33 Dielectric layer 34 Partition 35 Phosphor layers 51 and 61 Sustain circuit 52 Initial stage Write circuit 54, 54A, 54B, 54C, 62 Recovery circuit 55 Control circuit C1, C2 First recovery capacitor C3 Second recovery capacitor D1, D3 First high side recovery diode D2, D4 First low side Recovery diode D5 Boost diode D6 Diode IC1 Scan driver L1, L2 First inductor L3 Second inductor L4 Third inductor R1 Resistance S1, S3 First high-side recovery switch elements S2, S4 First low-side recovery switch element S5, S7 First high side Holding switch elements S6, S8 first low-side sustain switch element S9 first separation switch element S10 second separation switch element S11 high-side initialization switch element S12 low-side initialization switch element S13 boost switch element S14 second recovery switch Element S15 Switch element

Claims (16)

A display cell formed by applying a voltage to each electrode of a plasma display panel having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode orthogonal to the display electrode pair, and the display electrode pair and the data electrode Configured to cause display discharge in
A sustain circuit for supplying power for starting and maintaining the display discharge in the plasma display panel from a sustain voltage power source to the display electrode pair via a switch element;
A recovery capacitor that is charged and discharged by a current accompanying the display discharge, at least one inductor connected in series with the recovery capacitor, and a recovery circuit having a switch unit for controlling the charge and discharge by the recovery capacitor In the provided plasma display panel drive circuit,
After the recovery circuit starts supplying power to the display electrode by discharging the recovery capacitor, the switch element is turned on to start supplying power for discharging from the sustain circuit to the display electrode. The plasma display panel drive circuit is controlled to 60% or less of a resonance time determined by the inductor and the capacitance of the plasma display panel.   The time from when the recovery circuit starts supplying power to the display electrode due to discharge from the recovery capacitor until the switch element of the sustain circuit is turned on to start supplying discharge power to the display electrode The plasma display panel driving circuit according to claim 1, wherein the driving time is 15% or more of a resonance time determined by the inductor and the capacitance of the plasma display panel. The recovery capacitor is
A first recovery capacitor for recovering power from the display electrode;
The plasma display panel drive circuit according to claim 1, further comprising a second recovery capacitor for supplying power to the display electrode.   The plasma display panel drive according to claim 3, wherein the voltage value of the first recovery capacitor is set to be in a range of 30% to 80% of a voltage value for supplying discharge power to the display electrode. circuit.   4. The plasma display panel drive according to claim 3, wherein the voltage value of the second recovery capacitor is set to be in a range of 5% to 40% of a voltage value for supplying discharge power to the display electrode. circuit.   6. The plasma display panel drive circuit according to claim 3, wherein surplus electric charge recovered by the first recovery capacitor is regenerated to the sustain voltage power source via a boost converter. 6.   The plasma display panel drive circuit according to any one of claims 3 to 5, wherein surplus electric charge recovered by the first recovery capacitor is stabilized by a regulator.   The plasma display panel drive circuit according to claim 3, further comprising a circuit for supplying electric charge from the first recovery capacitor to the second recovery capacitor.   The plasma display panel drive circuit according to claim 3, wherein electric charge is supplied from the sustain voltage power source to the second recovery capacitor.   The plasma display panel drive circuit according to claim 3, wherein charge is supplied from an address voltage power supply to the second recovery capacitor. A plasma display panel having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode orthogonal to the display electrode pair, wherein a display cell is formed at each intersection of the display electrode pair and the data electrode;
The plasma display apparatus provided with the plasma display panel drive circuit of any one of Claims 1-10 for driving the said plasma display panel.   The plasma display apparatus according to claim 11, wherein the plasma display panel is filled with a discharge gas having a xenon concentration of 15% or more.   The plasma display device according to claim 11 or 12, wherein the plasma display panel has a peak value of a discharge current at a maximum load of 100 amperes or more.   The plasma display device according to any one of 11 to 13, wherein the plasma display panel has an electrode width of 200 microns or less.   The plasma display device according to any one of claims 11 to 14, wherein the plasma display panel has a capacitance of 0.001 microfarad to 1 microfarad.   The plasma display apparatus according to any one of claims 11 to 15, wherein the plasma display panel is filled with a gas having a discharge gas pressure of 300 Torr or more and 600 Torr or less.

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