WO2011089891A1 - Plasma display panel driving method and plasma display device - Google Patents

Plasma display panel driving method and plasma display device Download PDF

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Publication number
WO2011089891A1
WO2011089891A1 PCT/JP2011/000243 JP2011000243W WO2011089891A1 WO 2011089891 A1 WO2011089891 A1 WO 2011089891A1 JP 2011000243 W JP2011000243 W JP 2011000243W WO 2011089891 A1 WO2011089891 A1 WO 2011089891A1
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Prior art keywords
pulse
subfield
sustain
electrode
scan
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PCT/JP2011/000243
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French (fr)
Japanese (ja)
Inventor
雄一 坂井
秀彦 庄司
富岡 直之
貴彦 折口
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パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to EP11734498A priority Critical patent/EP2506239A1/en
Priority to CN2011800063537A priority patent/CN102714015A/en
Priority to JP2011550850A priority patent/JPWO2011089891A1/en
Publication of WO2011089891A1 publication Critical patent/WO2011089891A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2018Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms
    • G09G2310/065Waveforms comprising zero voltage phase or pause
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0247Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/16Calculation or use of calculated indices related to luminance levels in display data
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery

Definitions

  • the present invention relates to a method for driving a plasma display panel used for a wall-mounted television or a large monitor, and a plasma display device using the same.
  • a typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other.
  • a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other.
  • a dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
  • the back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
  • the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed.
  • a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.
  • ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
  • the subfield method is generally used as a method for driving the panel.
  • one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield.
  • Each subfield has an initialization period, an address period, and a sustain period.
  • an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell.
  • wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.
  • the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed.
  • an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).
  • the number of sustain pulses determined for each subfield is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode.
  • a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”. Also written as “lit”.)
  • each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield.
  • each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.
  • the plasma display device includes a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit in order to drive the panel in this way. Then, a drive voltage waveform is applied to each electrode to display an image on the panel.
  • the data electrode drive circuit is a drive circuit that generates an address discharge in each discharge cell by applying an address pulse corresponding to an image signal to each of the data electrodes. If the power consumption of the data electrode drive circuit exceeds the allowable value (maximum rating) of the circuit elements constituting the data electrode drive circuit, the data electrode drive circuit malfunctions and normal writing operation is not performed, and the image display quality May be damaged. In order to prevent this phenomenon, a circuit element having a large rated value may be used. However, such a circuit element is relatively expensive, which is one of the major causes of cost increase in the plasma display device.
  • a technique for controlling the number of sustain pulses in the sustain period is disclosed (for example, see Patent Document 2).
  • one field is divided into eight subfields from the first subfield to the eighth subfield (hereinafter, the first subfield is abbreviated as “first SF” and the second subfield is abbreviated as “second SF”).
  • first SF the first subfield
  • second SF the second subfield
  • the number of sustain pulses in the first SF is 1
  • the number of sustain pulses in the second SF is 2
  • the number of sustain pulses from the third SF to the eighth SF is 4, 8, 16, 32, 64, and 128, respectively.
  • a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode and a data electrode is applied with a scan pulse applied to the scan electrode and an address pulse applied to the data electrode.
  • This is a panel driving method in which one field is configured and driven by a plurality of subfields each having an address period and a sustain period in which the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pair. Then, the luminance weight is set in each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue, and the sustain pulse is generated based on the signal level of the image signal. Provide a subfield to stop.
  • the normal operation is a state in which no subfield for stopping the generation of the sustain pulse is generated.
  • the pulse width of the write pulse and the pulse width of the scan pulse are the same.
  • the pulse width is longer than the pulse width of the write pulse and the scan pulse during normal operation in the subfield.
  • the pulse width of the write pulse and the pulse of the scan pulse are generated in the subfield immediately after the subfield.
  • the width may be longer than the pulse width of the write pulse and the scan pulse during normal operation in the same subfield.
  • the plasma display apparatus includes a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a write that applies a scan pulse to the scan electrode and applies a write pulse to the data electrode.
  • a plasma display device comprising a drive circuit for driving a panel by forming one field with a plurality of subfields having a period and a sustain period in which a number of sustain pulses corresponding to a luminance weight are applied to a display electrode pair .
  • the drive circuit sets the luminance weight in each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue, and maintains the luminance weight based on the signal level of the image signal.
  • a subfield for stopping the generation of pulses is provided. Further, in the subfield immediately after the subfield where the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the pulse width of the scan pulse in normal operation in the subfield. Than to extend.
  • FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention.
  • FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention.
  • FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of the panel used in the plasma display device according to one embodiment of the present invention.
  • FIG. 4 is a diagram schematically showing the operation in the sustain period of each subfield in the embodiment of the present invention.
  • FIG. 5 is a characteristic diagram showing the relationship between the presence / absence of the sustain pulse and the amplitude of the address pulse necessary for generating a stable address discharge.
  • FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention.
  • FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention.
  • FIG. 3 is a diagram showing a driving voltage waveform applied to
  • FIG. 6 is a characteristic diagram showing the relationship between the pulse width of the address pulse and the amplitude of the address pulse necessary for generating a stable address discharge.
  • FIG. 7 is a diagram schematically showing a drive voltage waveform in one embodiment of the present invention.
  • FIG. 8 is a circuit block diagram of the plasma display device according to one embodiment of the present invention.
  • FIG. 9 is a circuit diagram showing a configuration of a scan electrode driving circuit of the plasma display device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a configuration of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing a configuration of a data electrode driving circuit of the plasma display device according to one embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention.
  • a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21.
  • a dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.
  • This protective layer 26 has been used as a panel material in order to lower the discharge starting voltage in the discharge cell.
  • the secondary layer 26 has a large secondary electron emission coefficient and is durable. It is made of a material mainly composed of magnesium oxide (MgO).
  • a plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon.
  • a phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
  • the front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.
  • a discharge gas having a xenon partial pressure of about 15% is used in order to improve the light emission efficiency in the discharge cell.
  • the discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32.
  • a color image is displayed on the panel 10 by discharging and emitting (lighting) these discharge cells.
  • R red
  • G green
  • B blue discharge cells
  • the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas may be further increased, for example, in order to improve the luminous efficiency, but may be other mixing ratios.
  • FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.
  • the panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) that are long in the row direction (line direction). Are arranged, and m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged.
  • the plasma display device in this embodiment performs gradation display by a subfield method.
  • the subfield method one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield.
  • Each subfield has an initialization period, an address period, and a sustain period.
  • An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.
  • the luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, various gradations can be displayed and images can be displayed by selectively causing each subfield to emit light in a combination according to the image signal.
  • one field is divided into 10 subfields (first SF, second SF,..., 10th SF), and each subfield is (1, 2, 4, 10, 19, 40, 4). , 7, 18, 35) will be described.
  • the luminance weights of the subfields are not simply set in ascending order (from the first SF to the tenth SF, and the luminance weights are increased in order), but the luminances are sequentially increased from the first SF to the sixth SF.
  • the weight is increased, and then the luminance weight is increased in order from the seventh SF to the tenth SF. That is, the luminance weight is set to each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue.
  • subfields with high emission luminance are concentrated in the latter half of the field.
  • subfields with high emission luminance are dispersed in the field, so that, for example, an image signal that displays an image of 50 fields per second (an image signal of 50 fields / second)
  • image flicker called flicker can be reduced.
  • an initializing operation is performed in all the cells to generate an initializing discharge in the initializing period of one subfield, and an immediately preceding period is set in the initializing period of the other subfield.
  • a selective initializing operation for selectively generating an initializing discharge is performed on a discharge cell that has generated a sustaining discharge in the sustain period of the subfield.
  • all-cell initializing subfield the subfield that performs the all-cell initializing operation
  • selective initializing subfield the subfield that performs the selective initializing operation
  • the all-cell initializing operation is performed in the initializing period of the first SF and the selective initializing operation is performed in the initializing periods of the second SF to the tenth SF.
  • the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the first SF. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge occurs, is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.
  • the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is applied to each display electrode pair 24.
  • This proportionality constant is the luminance magnification.
  • the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each of scan electrode 22 and sustain electrode 23. Therefore, for example, when the luminance magnification is two times, the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.
  • the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values.
  • the structure which switches a subfield structure based on an image signal etc. may be sufficient.
  • FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of panel 10 used in the plasma display device in one embodiment of the present invention.
  • FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown.
  • FIG. 3 shows drive voltage waveforms of two subfields having different drive voltage waveform shapes applied to scan electrode SC1 through scan electrode SCn during the initialization period.
  • the two subfields are a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield.
  • the drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different.
  • scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the electrodes based on image data (data indicating lighting / non-lighting for each subfield).
  • the first SF which is an all-cell initialization subfield, will be described.
  • the voltage 0 (V) is applied to each of the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn.
  • Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn.
  • Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
  • a ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn.
  • this ramp waveform voltage is referred to as “lamp voltage L1”.
  • Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
  • a numerical value of about 1.3 V / ⁇ sec can be cited.
  • all-cell initialization period the period for performing the all-cell initialization operation
  • all-cell initialization waveform The drive voltage waveform generated for performing the all-cell initialization operation
  • a scan pulse of voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn.
  • an address pulse of positive voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.
  • voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn
  • voltage Vc is applied to scan electrode SC1 through scan electrode SCn.
  • the scan pulse of the negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is performed first, and the data of the discharge cells that should emit light in the first row of the data electrodes D1 to Dm.
  • An address pulse with a positive voltage Vd is applied to the electrode Dk.
  • the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (voltage Vd ⁇ voltage Va). It will be added.
  • the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.
  • the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve2 ⁇ voltage Va) and sustain electrode SU1.
  • the difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added.
  • the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.
  • a discharge generated between the data electrode Dk and the scan electrode SC1 can be triggered to generate a discharge between the sustain electrode SU1 and the scan electrode SC1 in the region intersecting the data electrode Dk.
  • an address discharge is generated in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Is accumulated.
  • a scan pulse is applied to the scan electrode SC2 that performs the second address operation, and an address pulse is applied to the data electrode Dk corresponding to the discharge cell that should emit light in the row that performs the second address operation.
  • an address discharge is generated and an address operation is performed.
  • the above address operation is sequentially performed until the discharge cell in the n-th row, and the address period ends. In this manner, in the address period, address discharge is selectively generated in the discharge cells to emit light, and wall charges are formed in the discharge cells.
  • V voltage 0 (V) is first applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of positive voltage Vsus is applied to scan electrode SC1 through scan electrode SCn.
  • the voltage difference between the scan electrode SCi and the sustain electrode SUi is obtained by adding the difference between the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi to the sustain pulse voltage Vsus. It will be a thing.
  • the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
  • sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. By doing so, sustain discharge is continuously generated in the discharge cells that have generated address discharge in the address period.
  • the weak discharge is continuously generated during a period in which the voltage applied to scan electrode SC1 through scan electrode SCn rises above the discharge start voltage.
  • the voltage applied to scan electrode SC1 through scan electrode SCn is maintained at voltage Vr, and then decreases to voltage 0 (V) as the base potential.
  • the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi.
  • the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn is the difference between the voltage applied to scan electrode SCi and the discharge start voltage, for example, (voltage Vr ⁇ discharge start voltage). It is weakened to the extent. That is, the discharge generated by the erase lamp voltage L3 works as an erase discharge.
  • scan electrode SC1 to scan electrode SCn are returned to voltage 0 (V), and the sustain operation in the sustain period ends.
  • a drive voltage waveform in which the first half of the initialization period in the first SF is omitted is applied to each electrode.
  • Voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm.
  • Scan voltage SC1 to scan electrode SCn are applied with a ramp voltage L4 that gradually decreases from a voltage lower than the discharge start voltage (eg, voltage 0 (V)) toward negative voltage Vi4 that exceeds the discharge start voltage.
  • the gradient of the ramp voltage L4 is the same as the gradient of the ramp voltage L2, and an example thereof is a numerical value of about ⁇ 2.5 V / ⁇ sec.
  • the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is generated in the discharge cell that has generated the sustaining discharge in the sustain period of the immediately preceding subfield.
  • a period during which the selective initialization operation is performed is referred to as a selective initialization period.
  • a drive voltage waveform similar to that in the first SF address period and sustain period is applied to each electrode.
  • the same drive voltage waveform as that of the second SF is applied to each electrode except for the number of sustain pulses.
  • Voltage Va ⁇ 180 (V)
  • voltage Vsus 190 (V)
  • voltage Vr 190 (V)
  • voltage Ve1 125 (V)
  • voltage Ve2 125 (V)
  • voltage Vd 60 (V) is there.
  • these voltage values are merely an example.
  • Each voltage value is desirably set to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.
  • FIG. 4 is a diagram schematically showing the operation during the sustain period of each subfield in the embodiment of the present invention.
  • FIG. 4 shows a drive voltage waveform applied to scan electrode SCi.
  • a waveform whose generation has been stopped is indicated by a broken line. That is, the waveform shown by the broken line in FIG. 4 is a waveform that occurs during normal operation but stops in response to the image signal.
  • the emission luminance is controlled by the combination of the subfield that generates the sustain discharge and the subfield that does not generate the sustain discharge, and the discharge cell emits light with the luminance according to the gradation. Display gradation. Therefore, when an image with a low signal level (gradation value) of the image signal and a low emission luminance is displayed, no sustain discharge occurs in the subfield with a large luminance weight.
  • a subfield for stopping the generation of the sustain pulse is provided based on the signal level (gradation value) of the image signal.
  • the sixth SF for example, luminance weight 40
  • no sustain pulse is generated in the sixth SF.
  • the voltage waveform applied to the scan electrode 22 at this time is the waveform shown in the waveform diagram of the sixth SF stop (second waveform diagram from the top) shown in FIG.
  • the voltage waveform applied to the scan electrode 22 at this time is the waveform shown in the waveform diagram of the sixth and tenth SF stops (third waveform diagram from the top) shown in FIG.
  • FIG. 4 shows the voltage waveform applied to the scan electrode 22, but the voltage waveform applied to the sustain electrode 23 also depends on the signal level (gradation value) in the same manner as described above. Then, the generation of sustain pulses is stopped in order from the subfield with the largest luminance weight. Therefore, in the subfield where the sustain pulse applied to scan electrode 22 is stopped, the sustain pulse applied to sustain electrode 23 is similarly stopped.
  • the generation of sustain pulses is stopped in order from the subfield having the largest luminance weight based on the magnitude of the signal level (gradation value).
  • the generation of a sustain pulse can be stopped in that subfield. Therefore, it is possible to reduce the power consumption for the generation of the sustain pulses.
  • the write operation and the initialization operation are not required. Therefore, the generation of the write pulse, the scan pulse, and the ramp voltage L4 for the initialization operation is stopped together with the sustain pulse. Also good. Thereby, the effect of reducing power consumption can be further enhanced.
  • the present inventor experimentally confirmed that the write operation tends to become unstable in the subfield immediately after the generation of the sustain pulse is stopped.
  • FIG. 5 is a characteristic diagram showing the relationship between the presence / absence of the sustain pulse and the amplitude of the address pulse necessary for generating a stable address discharge.
  • FIG. 5 shows the amplitude (V) of the address pulse necessary for generating a stable address discharge during normal operation and when the sustain pulse generation is stopped in the sustain period of the immediately preceding subfield. ing. However, in this normal operation, a sustain pulse is generated in the sustain period of the immediately preceding subfield, but no sustain discharge is generated.
  • the amplitude of the address pulse necessary for generating a stable address discharge is about 45 (V).
  • the amplitude of the address pulse necessary for generating a stable address discharge in the subfield immediately after is about 48 (V), About 3 (V) higher than normal operation. Therefore, the write operation tends to become unstable accordingly.
  • the reason why the discharge becomes unstable when the discharge delay time becomes large is that the discharge delay time becomes large, and the time until discharge occurs is a pulse width (the time when voltage is applied to the discharge cell). This is considered to be because the applied voltage of the discharge cell decreases before discharge occurs.
  • This discharge delay time can be improved by increasing the voltage applied to the discharge cell. And the generation
  • the inventor of the present application can generate a stable address discharge without increasing the voltage applied to the discharge cells by increasing the pulse width according to the discharge delay time during the address operation. This was confirmed by experiments.
  • FIG. 6 is a characteristic diagram showing the relationship between the pulse width of the address pulse and the amplitude of the address pulse necessary for generating a stable address discharge.
  • the horizontal axis represents the pulse width ( ⁇ sec) of the address pulse
  • the vertical axis represents the amplitude (V) of the address pulse necessary for generating a stable address discharge.
  • the pulse width of the scan pulse is also changed in accordance with the write pulse.
  • the amplitude of the address pulse necessary to generate a stable address discharge is 48 (V). there were.
  • the pulse width of the address pulse and the pulse width of the scan pulse were set to 1.05 ⁇ sec
  • the amplitude of the address pulse necessary for generating a stable address discharge was 45 (V).
  • the amplitude of the address pulse necessary for generating a stable address discharge is The voltage could be reduced from 48 (V) to 45 (V).
  • the pulse width of the write pulse is reduced from 0.95 ⁇ sec to 1 It can be seen that by extending to 0.05 ⁇ sec, it is possible to generate a stable address discharge similar to that during normal operation without increasing the address pulse amplitude.
  • the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the scan pulse in the other subfield. It is assumed to extend beyond the pulse width.
  • FIG. 7 is a diagram schematically showing a drive voltage waveform in one embodiment of the present invention.
  • FIG. 7 shows drive voltage waveforms applied to scan electrode SCi and data electrode D1 to data electrode Dm.
  • FIG. 7 shows a drive voltage waveform during normal operation and a drive voltage waveform when the generation of the sustain pulse is stopped in the sixth SF.
  • the “normal operation” represents an operation for generating a sustain pulse in all subfields, that is, an operation when a subfield for stopping the generation of the sustain pulse does not occur.
  • the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse in the other subfield.
  • the pulse width of the scanning pulse is extended. For example, as shown in FIG. 7, when the generation of the sustain pulse is stopped in the sixth SF, the pulse width of the write pulse and the pulse width of the scan pulse are changed to other subfields (for example, the first SF) in the write period of the seventh SF. It is assumed that the pulse width is longer than the pulse width of the write pulse and the scan pulse.
  • the pulse width of the write pulse and the pulse width of the scan pulse are set differently for each subfield
  • the pulse width of the write pulse and the scan pulse of the subfield where the generation of the sustain pulse is stopped are set to other subfields.
  • the pulse width of the write pulse and the pulse width of the scan pulse are increased in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the write in the subfield in which the generation of the sustain pulse is stopped. It may be less than the pulse width of the pulse and the pulse width of the scanning pulse.
  • the pulse width of the writing pulse and the pulse width of the scanning pulse in the subfield having the largest luminance weight are larger than those of the other subfields, and generation of the sustain pulse is stopped in that subfield. Even if the pulse width of the address pulse and the pulse width of the scan pulse are increased in the subsequent subfield (seventh SF), the pulse width of the address pulse and the pulse width of the scan pulse in the subfield having the largest luminance weight may not be reached.
  • the pulse width of the write pulse and the pulse width of the scanning pulse are Normal operation of the same subfield (in this case, 7th SF) It shall be extended than the pulse width of the pulse width and the scanning pulse of the write pulse in.
  • the pulse width of the write pulse and the pulse width of the scan pulse are set to those in the normal operation (for example, about 0.95 ⁇ sec). Is set to be extended by 0.1 ⁇ sec (for example, about 1.05 ⁇ sec).
  • these numerical values are based on the measurement results shown in FIG. 6, and the present invention is not limited to these numerical values.
  • Each pulse width and extension time are desirably set optimally according to the characteristics of the panel 10 and the specifications of the plasma display device.
  • the length of the address period is extended by extending the pulse width of the address pulse and the pulse width of the scan pulse.
  • the start time of the subfield is advanced by the extension time, it is not necessary to extend the end time of the last subfield (for example, the 10th SF) backward.
  • the sustain pulse generation is stopped in the sixth SF and the pulse width of the seventh SF write pulse and the pulse width of the scan pulse are extended so that the write period of the seventh SF is increased by 76.8 ⁇ sec from the normal operation time. .
  • This is a numerical value when the pulse width of the write pulse and the pulse width of the scan pulse are set to +0.1 ⁇ sec and the number of scan electrodes 22 is 768.
  • the start time of the seventh SF may be advanced by 76.8 ⁇ sec from the normal operation time. Since no sustain pulse is generated in the sixth SF, there is no problem even if the start time of the seventh SF is advanced.
  • the generation timing of the sustain period of each subfield can be made equal to that during normal operation, the temporal deviation of the center of gravity of the luminance is suppressed, and flicker (the luminance flickering that occurs in the display image) may occur. It can also be reduced.
  • FIG. 8 is a circuit block diagram of the plasma display device 30 in one embodiment of the present invention.
  • the plasma display device 30 includes a panel 10 and a drive circuit.
  • the drive circuit includes an image signal processing circuit 36, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a control signal generation circuit 40, and a power supply circuit (not shown) that supplies power necessary for each circuit block. ).
  • the image signal processing circuit 36 assigns a gradation value to each discharge cell based on the input image signal.
  • the gradation value is converted into image data indicating light emission / non-light emission for each subfield (data corresponding to light emission / non-light emission corresponding to digital signals “1” and “0”).
  • each gradation value of R, G, and B is assigned to each discharge cell based on the R signal, the G signal, and the B signal.
  • the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal, etc.)
  • the luminance signal and saturation signal Based on the degree signal, R signal, G signal, and B signal are calculated, and thereafter, R, G, and B gradation values (gradation values expressed in one field) are assigned to each discharge cell. Then, the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.
  • the control signal generation circuit 40 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. Then, the generated control signal is supplied to each circuit block (data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, image signal processing circuit 36, etc.).
  • the control signal generation circuit 40 determines a subfield for stopping the generation of sustain pulses based on the image data from the image signal processing circuit 36, and generates a control signal based on the determination. Further, in the address period of the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the control signal is generated so as to extend the pulse width of the address pulse and the pulse width of the scan pulse.
  • Scan electrode drive circuit 43 includes an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 8), and a drive voltage waveform based on a control signal supplied from control signal generation circuit 40. Is applied to each of scan electrode SC1 to scan electrode SCn.
  • the initialization waveform generation circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn based on the control signal during the initialization period.
  • the sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn based on the control signal during the sustain period.
  • the scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn based on a control signal during an address period. At this time, the scan pulse generation circuit generates a scan pulse with a pulse width based on the control signal.
  • scan ICs scan electrode driving ICs
  • Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit that generates voltage Ve1 and voltage Ve2 (not shown in FIG. 8), and generates a drive voltage waveform based on a control signal supplied from control signal generation circuit 40. It is prepared and applied to each of sustain electrode SU1 through sustain electrode SUn. In the sustain period, a sustain pulse is generated based on the control signal and applied to sustain electrode SU1 through sustain electrode SUn.
  • the data electrode drive circuit 42 converts the data for each subfield constituting the image data into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the control signal supplied from the control signal generation circuit 40, the data electrodes D1 to Dm are driven. In the address period, an address pulse having a pulse width based on the control signal is generated and applied to each of the data electrodes D1 to Dm.
  • FIG. 9 is a circuit diagram showing a configuration of scan electrode drive circuit 43 of plasma display device 30 in one embodiment of the present invention.
  • Scan electrode drive circuit 43 includes sustain pulse generation circuit 50 on the scan electrode 22 side, initialization waveform generation circuit 53, and scan pulse generation circuit 54.
  • Each of the output terminals of scan pulse generating circuit 54 is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. This is so that the scan pulse can be individually applied to each of the scan electrodes 22 in the address period.
  • the voltage input to the scan pulse generation circuit 54 is referred to as “reference potential A”. Further, in the following description, the operation of turning on the switching element is expressed as “ON”, and the operation of blocking is described as “OFF”. In FIG. 9, details of the signal path of the control signal are omitted.
  • the initialization waveform generation circuit 53 raises or lowers the reference potential A of the scan pulse generation circuit 54 in a ramp shape during the initialization period, and generates the initialization waveform shown in FIG.
  • the sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52.
  • the power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a backflow prevention diode Di12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to cause the sustain pulse to rise and fall.
  • the clamp circuit 52 includes a switching element Q13 for clamping scan electrode SC1 to scan electrode SCn to voltage Vsus, and a switching element Q14 for clamping scan electrode SC1 to scan electrode SCn to voltage 0 (V) which is a base potential.
  • V voltage
  • the reference potential A is connected to the power source VS via the switching element Q13, the scan electrodes SC1 to SCn are clamped to the voltage Vsus, and the reference potential A is grounded via the switching element Q14 to scan the scan electrodes SC1 to SC1.
  • the electrode SCn is clamped to a voltage of 0 (V).
  • sustain pulse generating circuit 50 Based on the control signal supplied from control signal generating circuit 40, sustain pulse generating circuit 50 conducts (on) and interrupts (off) switching element Q11, switching element Q12, switching element Q13, and switching element Q14. By switching the power recovery circuit 51 and the clamp circuit 52, the sustain pulse is generated.
  • the switching element Q11 when the sustain pulse is raised, the switching element Q11 is turned on to cause the interelectrode capacitance Cp and the inductor L10 to resonate, and from the power recovery capacitor C10 through the switching element Q11, the diode Di11, and the inductor L10, the scan electrode SC1. Power is supplied to scan electrode SCn.
  • switching element Q13 When the voltage of scan electrode SC1 through scan electrode SCn approaches voltage Vsus, switching element Q13 is turned on, and the circuit for driving scan electrode SC1 through scan electrode SCn is switched from power recovery circuit 51 to clamp circuit 52. Scan electrode SC1 to scan electrode SCn are clamped to voltage Vsus.
  • the switching element Q12 is turned on to resonate the interelectrode capacitance Cp and the inductor L10. From the interelectrode capacitance Cp, the power recovery power is passed through the inductor L10, the diode Di12, and the switching element Q12. Power is collected in the capacitor C10.
  • switching element Q14 is turned on, and a circuit for driving scan electrode SC1 through scan electrode SCn is connected from power recovery circuit 51 to a clamp circuit. Then, the scan electrode SC1 to the scan electrode SCn are clamped to the voltage 0 (V) which is the base potential.
  • switching element Q14 is turned on, and scan electrode SC1 to scan electrode SCn are kept clamped at voltage 0 (V).
  • switching elements can be configured using generally known elements such as MOSFETs and IGBTs.
  • the scan pulse generation circuit 54 includes a switch 72 for connecting the reference potential A to the negative voltage Va in the write period, a power supply VC for generating the voltage Vcn by generating the voltage Vscn and superimposing it on the reference potential A, Switching element QH1 to switching element QHn for applying voltage Vc to each of scan electrode SC1 to scan electrode SCn, and switching element QL1 to switching element for applying reference potential A to each of scan electrode SC1 to scan electrode SCn QLn.
  • the switching elements QH1 to QHn and the switching elements QL1 to QLn are integrated into a plurality of ICs for each output.
  • This IC is a scanning IC. That is, scan pulse generating circuit 54 has a plurality of scan ICs that generate scan pulses to be applied to scan electrode SC1 through scan electrode SCn.
  • scan pulse generating circuit 54 has a plurality of scan ICs that generate scan pulses to be applied to scan electrode SC1 through scan electrode SCn.
  • the switching element QHi is turned off and the switching element QLi is turned on for the scan electrode SCi to which the scan pulse is applied.
  • the scan pulse of the negative voltage Va is applied to the scan electrode SCi.
  • the switching element QLh is turned off and the switching element QHh is turned on, so that the switching element QHh is turned on. Via, the voltage Vc is applied to the scan electrode SCh.
  • the pulse width of the scan pulse can be controlled by controlling the switching elements QH1 to QHn and the switching elements QL1 to QLn based on the control signal.
  • Scan pulse generation circuit 54 generates a control signal so that the voltage waveform output from initialization waveform generation circuit 53 is output during the initialization period, and the voltage waveform output from sustain pulse generation circuit 50 is output during the sustain period. It is assumed that it is controlled by the circuit 40. That is, when the initialization waveform generation circuit 53 or the sustain pulse generation circuit 50 is operating, the switching elements QH1 to QHn of the scan pulse generation circuit 54 are turned off and the switching elements QL1 to QLn are turned on. Then, an initialization waveform or a sustain pulse is applied to each of scan electrode SC1 through scan electrode SCn via switching element QL1 through switching element QLn.
  • a control signal for controlling each circuit is supplied from the control signal generation circuit 40.
  • FIG. 10 is a circuit diagram showing a configuration of sustain electrode drive circuit 44 of plasma display device 30 in one embodiment of the present invention.
  • the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit diagram of the scan electrode driving circuit 43 is omitted.
  • Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 having substantially the same configuration as sustain pulse generation circuit 50.
  • Sustain pulse generation circuit 80 includes power recovery circuit 81 and clamp circuit 82, and is connected to sustain electrode SU1 through sustain electrode SUn of panel 10.
  • the output voltage of the sustain electrode drive circuit 44 is applied to all the sustain electrodes 23 in parallel. This is because it is not necessary to individually drive the sustain electrodes 23 like the scan electrodes 22 in both the writing period and the sustain period, and it is sufficient to apply the drive voltage to all the sustain electrodes 23 at the same time.
  • the power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a backflow prevention diode Di22, and a resonance inductor L20.
  • the clamp circuit 82 includes a switching element Q23 for clamping sustain electrode SU1 to sustain electrode SUn to voltage Vsus, and a switching element Q24 for clamping sustain electrode SU1 to sustain electrode SUn to the ground potential (voltage 0 (V)).
  • sustain pulse generating circuit 80 switches on / off of each switching element based on a control signal output from control signal generating circuit 40 to generate a sustain pulse. Then, a sustain pulse is applied to n sustain electrodes SU1 to SUn.
  • the operation of sustain pulse generating circuit 80 is the same as that of sustain pulse generating circuit 50 described above, and a description thereof will be omitted.
  • switching element Q24 is turned on, and sustain electrode SU1 through sustain electrode SUn are kept clamped at voltage 0 (V).
  • sustain electrode drive circuit 44 includes a power source VE1 that generates voltage Ve1, a switching element Q26 and switching element Q27 for applying voltage Ve1 to sustain electrode SU1 through sustain electrode SUn, and a power source ⁇ VE that generates voltage ⁇ Ve.
  • a backflow prevention diode Di30, a charge pump capacitor C30 for superimposing voltage ⁇ Ve on voltage Ve1, a switching element Q28 for generating voltage Ve2 by superimposing voltage ⁇ Ve on voltage Ve1, and switching element Q29 And have.
  • the capacitor C30, the switching element Q28, the switching element Q29, and the power source ⁇ VE are not necessary.
  • FIG. 11 is a circuit diagram showing the configuration of the data electrode drive circuit 42 of the plasma display device 30 according to one embodiment of the present invention.
  • Data electrode drive circuit 42 has switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm.
  • the data electrode drive circuit 42 clamps the data electrodes D1 to Dm to the voltage Vd independently through the switching elements Q1D1 to Q1Dm. Further, the data electrodes D1 to Dm are independently grounded via the switching elements Q2D1 to Q2Dm and clamped to a voltage of 0 (V). In this way, the data electrode driving circuit 42 independently drives the data electrodes D1 to Dm, and applies an address pulse of the positive voltage Vd to the data electrodes D1 to Dm.
  • Data electrode drive circuit 42 controls the switching time of switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm based on the control signal supplied from control signal generation circuit 40.
  • the pulse width of the write pulse can be changed.
  • the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the scan pulse in the same subfield during normal operation. More than that.
  • the pulse width of the write pulse and the pulse width of the scan pulse are equal to each other, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, The pulse width of the scan pulse is made longer than the pulse width of the write pulse and the pulse width of the scan pulse in the other subfields. Thereby, stable address discharge can be generated in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped.
  • the start time of the subfield is advanced by the length of the writing period by extending the pulse width. Therefore, even when the length of the writing period is extended, all the subfields can be accommodated within one field time. Furthermore, since the generation timing of the sustain period of each subfield can be made equal to that during normal operation, it is possible to suppress the temporal deviation of the gravity center of gravity and prevent the occurrence of flicker.
  • the pulse width of the write pulse in the subfield immediately after that subfield may be extended.
  • the predetermined number of times described above is set to 3
  • the pulse width and scanning of the write pulse are performed in the seventh SF that is a subfield immediately after those subfields.
  • the pulse width of the pulse is made longer than the pulse width of the write pulse and the scan pulse in the seventh SF during normal operation.
  • the predetermined number of times described above may be appropriately set according to the characteristics of the panel, the specifications of the plasma display device, and the like.
  • the extension time when extending the pulse width of the address pulse and the pulse width of the scan pulse is necessary to generate a stable address discharge. It is desirable to set the write pulse amplitude to be equivalent to that during normal operation.
  • each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
  • each control signal shown in the present embodiment is not limited to the polarity described above. As long as the operation is similar to the operation described in this embodiment, the polarity may be opposite to the above polarity.
  • the drive circuit described above is merely an example, and the configuration of the drive circuit is not limited to the configuration described above.
  • the specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 768. It is just an example.
  • the present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
  • the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.
  • the present invention can achieve both reduction in power consumption and stable address discharge even for a large-screen panel with high definition, and is useful as a panel driving method and a plasma display device. .
  • SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 30 Plasma display device 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 36 Image signal processing circuit 40 Control signal generation circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 50, 80 Sustain pulse generation circuit 51, 81 Power recovery circuit 52, 82 Clamp circuit 53 Initialization waveform generation circuit 54 Scan pulse generation circuit 72 Switch Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29, QH1 to QHn, QL1 to QLn, Q1D1 to Q1Dm, Q2D1 to Q2Dm Switching elements C10, C20, C30 Capacitors L10, L 0 inductors Di11, Di12, Di21, Di22, Di30 diodes L1, L2, L4 ramp voltage L3 erasing ramp voltage

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Abstract

Disclosed are a plasma display panel driving method and a plasma display device wherein reduction in power consumption and stable write discharge are compatible with each other even when applied to a high-definition and large-screen panel. For this, the plasma display panel driving method which drives the plasma display panel by configuring each field of a plurality of subfields each having a writing period and a sustaining period so sets a luminance weight to each subfield that the subfield having the largest luminance weight and the subfield having the second largest luminance weight are not continuous, provides a subfield wherein the occurrence of sustain pulses is stopped on the basis of the signal level of an image signal, and in the subfield right after the subfield wherein the occurrence of the sustain pulses is stopped, extends the pulse width of write pulses and that of scanning pulses to be longer than the pulse width of the write pulses and that of the scanning pulses in normal operation in the same subfield.

Description

プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置Plasma display panel driving method and plasma display device
 本発明は、壁掛けテレビや大型モニターに用いられるプラズマディスプレイパネルの駆動方法およびそれを用いたプラズマディスプレイ装置に関する。 The present invention relates to a method for driving a plasma display panel used for a wall-mounted television or a large monitor, and a plasma display device using the same.
 プラズマディスプレイパネル(以下、「パネル」と略記する)として代表的な交流面放電型パネルは、対向配置された前面基板と背面基板との間に多数の放電セルが形成されている。前面基板は、1対の走査電極と維持電極とからなる表示電極対が前面側のガラス基板上に互いに平行に複数対形成されている。そして、それら表示電極対を覆うように誘電体層および保護層が形成されている。 2. Description of the Related Art A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other. In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
 背面基板は、背面側のガラス基板上に複数の平行なデータ電極が形成され、それらデータ電極を覆うように誘電体層が形成され、さらにその上にデータ電極と平行に複数の隔壁が形成されている。そして、誘電体層の表面と隔壁の側面とに蛍光体層が形成されている。 The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
 そして、表示電極対とデータ電極とが立体交差するように、前面基板と背面基板とを対向配置して密封する。密封された内部の放電空間には、例えば分圧比で5%のキセノンを含む放電ガスを封入し、表示電極対とデータ電極とが対向する部分に放電セルを形成する。このような構成のパネルにおいて、各放電セル内でガス放電により紫外線を発生し、この紫外線で赤色(R)、緑色(G)および青色(B)の各色の蛍光体を励起発光してカラーの画像表示を行う。 Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
 パネルを駆動する方法としては一般にサブフィールド法が用いられている。サブフィールド法では、1フィールドを複数のサブフィールドに分割し、それぞれのサブフィールドで各放電セルを発光または非発光にすることにより階調表示を行う。各サブフィールドは、初期化期間、書込み期間および維持期間を有する。 The subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.
 初期化期間では、各走査電極に初期化波形を印加し、各放電セルで初期化放電を発生する。これにより、各放電セルにおいて、続く書込み動作のために必要な壁電荷を形成するとともに、書込み放電を安定して発生するためのプライミング粒子(放電を発生させるための励起粒子)を発生する。 In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.
 書込み期間では、走査電極に走査パルスを順次印加するとともに、データ電極には表示すべき画像信号にもとづき選択的に書込みパルスを印加する。これにより、発光を行うべき放電セルの走査電極とデータ電極との間に書込み放電を発生し、その放電セル内に壁電荷を形成する(以下、これらの動作を総称して「書込み」とも記す)。 In the address period, the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).
 維持期間では、サブフィールド毎に定められた数の維持パルスを走査電極と維持電極とからなる表示電極対に交互に印加する。これにより、書込み放電を発生した放電セルで維持放電を発生し、その放電セルの蛍光体層を発光させる(以下、放電セルを維持放電により発光させることを「点灯」、発光させないことを「非点灯」とも記す)。これにより、各放電セルを、サブフィールド毎に定められた輝度重みに応じた輝度で発光させる。このようにして、パネルの各放電セルを画像信号の階調値に応じた輝度で発光させて、パネルの画像表示領域に画像を表示する。 In the sustain period, the number of sustain pulses determined for each subfield is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”. Also written as “lit”.) As a result, each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.
 そしてプラズマディスプレイ装置は、パネルをこのように駆動するために、走査電極駆動回路、維持電極駆動回路、データ電極駆動回路を備えている。そして、それぞれの電極に駆動電圧波形を印加して、パネルに画像を表示する。 The plasma display device includes a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit in order to drive the panel in this way. Then, a drive voltage waveform is applied to each electrode to display an image on the panel.
 近年はパネルの高精細度化、大画面化が進み、それにともないプラズマディスプレイ装置の消費電力が増加する傾向にある。データ電極駆動回路は、画像信号に対応した書込みパルスをデータ電極のそれぞれに印加して各放電セルで書込み放電を発生する駆動回路である。そして、データ電極駆動回路の消費電力が、データ電極駆動回路を構成する回路素子の許容値(最大定格)を超えると、データ電極駆動回路が誤動作し、正常な書込み動作が行われず、画像表示品質を損なうことがある。この現象を防止するためには定格値の大きい回路素子を使用すればよい。しかし、そのような回路素子は比較的高価であり、プラズマディスプレイ装置におけるコストアップの大きな要因の1つとなる。 In recent years, the panel has become higher definition and larger screen, and the power consumption of the plasma display device tends to increase accordingly. The data electrode drive circuit is a drive circuit that generates an address discharge in each discharge cell by applying an address pulse corresponding to an image signal to each of the data electrodes. If the power consumption of the data electrode drive circuit exceeds the allowable value (maximum rating) of the circuit elements constituting the data electrode drive circuit, the data electrode drive circuit malfunctions and normal writing operation is not performed, and the image display quality May be damaged. In order to prevent this phenomenon, a circuit element having a large rated value may be used. However, such a circuit element is relatively expensive, which is one of the major causes of cost increase in the plasma display device.
 そこで、画像表示品質を低下させずにデータ電極駆動回路の消費電力を抑制する方法として、データ電極に印加する書込みパルスの順序を変更し、データ電極の充放電に際して流れる充放電電流を減らして、データ電極駆動回路の消費電力を制限する方法が提案されている(例えば、特許文献1参照)。 Therefore, as a method of suppressing the power consumption of the data electrode driving circuit without degrading the image display quality, the order of the address pulses applied to the data electrode is changed, the charge / discharge current flowing during the charge / discharge of the data electrode is reduced, A method for limiting the power consumption of the data electrode driving circuit has been proposed (see, for example, Patent Document 1).
 また、維持期間における維持パルスのパルス数を制御する技術が開示されている(例えば、特許文献2参照)。この技術では、例えば、1フィールドを第1サブフィールドから第8サブフィールド(以下、第1サブフィールドを「第1SF」、第2サブフィールドを「第2SF」というように略記する)の8つのサブフィールドで構成し、第1SFの維持パルス数を1、第2SFの維持パルス数を2、以下第3SFから第8SFまでの維持パルス数をそれぞれ4、8、16、32、64、128としたとき、第1SFから第8SFまでの維持パルス数をそれぞれ2倍の2、4、8、16、32、64、128、256にした2倍モード、同様にそれぞれを3倍にした3倍モード、4倍にした4倍モードと、サブフィールドの維持パルス数を1倍から2倍、3倍、4倍と変化させる(以下、この倍率のことを「輝度倍率」と略記する)ことによって維持期間における発光の回数を制御することができる。これにより、輝度倍率を上げたときには暗い画像を明るく表示することができ、輝度倍率を下げたときには消費電力を抑制することができる。 Also, a technique for controlling the number of sustain pulses in the sustain period is disclosed (for example, see Patent Document 2). In this technique, for example, one field is divided into eight subfields from the first subfield to the eighth subfield (hereinafter, the first subfield is abbreviated as “first SF” and the second subfield is abbreviated as “second SF”). When the number of sustain pulses in the first SF is 1, the number of sustain pulses in the second SF is 2, and the number of sustain pulses from the third SF to the eighth SF is 4, 8, 16, 32, 64, and 128, respectively. , The double mode in which the number of sustain pulses from the first SF to the eighth SF is doubled to 2, 4, 8, 16, 32, 64, 128, 256, respectively, and similarly, the triple mode in which each is tripled, 4 Sustained period by doubling the 4 × mode and changing the number of subfield sustain pulses from 1 × to 2 ×, 3 ×, and 4 × (hereinafter, this magnification is abbreviated as “luminance magnification”). It is possible to control the number of light emission in. Thereby, a dark image can be displayed brightly when the luminance magnification is increased, and power consumption can be suppressed when the luminance magnification is decreased.
 高精細度化された大画面のパネルでは、駆動しなければならない電極の数が増加し、また、駆動時のインピーダンスも増加するため、消費電力が増大する傾向にある。そのため、そのようなパネルを備えたプラズマディスプレイ装置では、さらなる消費電力の削減が求められている。しかし、消費電力を削減するために放電セルに印加する駆動電圧を低減すると、放電セル内に発生する放電が不安定になるおそれがある。 In a large-screen panel with high definition, the number of electrodes that must be driven increases, and the impedance during driving also increases, so power consumption tends to increase. Therefore, further reduction of power consumption is demanded in the plasma display device provided with such a panel. However, if the drive voltage applied to the discharge cell is reduced to reduce power consumption, the discharge generated in the discharge cell may become unstable.
特開平11-282398号公報Japanese Patent Laid-Open No. 11-282398 特開平8-286636号公報JP-A-8-286636
 本発明のパネルの駆動方法は、走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたパネルを、走査電極に走査パルスを印加しデータ電極に書込みパルスを印加する書込み期間と、輝度重みに応じた数の維持パルスを表示電極対に印加する維持期間とを有する複数のサブフィールドで1フィールドを構成して駆動するパネルの駆動方法である。そして、最も輝度重みの大きいサブフィールドと2番目に輝度重みが大きいサブフィールドとが連続しないように各サブフィールドに輝度重みを設定し、画像信号の信号レベルの大きさにもとづき維持パルスの発生を停止するサブフィールドを設ける。そして、維持パルスの発生を停止するサブフィールドが生じない状態を通常動作とし、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、同サブフィールドにおける通常動作時の書込みパルスのパルス幅および走査パルスのパルス幅よりも延長する。 According to the panel driving method of the present invention, a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode and a data electrode is applied with a scan pulse applied to the scan electrode and an address pulse applied to the data electrode. This is a panel driving method in which one field is configured and driven by a plurality of subfields each having an address period and a sustain period in which the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pair. Then, the luminance weight is set in each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue, and the sustain pulse is generated based on the signal level of the image signal. Provide a subfield to stop. The normal operation is a state in which no subfield for stopping the generation of the sustain pulse is generated. In the subfield immediately after the subfield for which the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are the same. The pulse width is longer than the pulse width of the write pulse and the scan pulse during normal operation in the subfield.
 この方法により、高精細度化された大画面のパネルであっても、消費電力を削減するとともに、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、安定した書込み放電を行うことが可能となる。 By this method, even for a large-screen panel with high definition, power consumption can be reduced and stable address discharge can be performed in the subfield immediately after the subfield where the generation of the sustain pulse is stopped. It becomes possible.
 また、本発明のパネルの駆動方法においては、維持パルスの発生を停止するサブフィールドが所定回数以上連続したときに、それらサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、同サブフィールドにおける通常動作時の書込みパルスのパルス幅および走査パルスのパルス幅よりも延長してもよい。 Further, in the panel driving method of the present invention, when the subfields for which the generation of the sustain pulse is stopped continue for a predetermined number of times or more, the pulse width of the write pulse and the pulse of the scan pulse are generated in the subfield immediately after the subfield. The width may be longer than the pulse width of the write pulse and the scan pulse during normal operation in the same subfield.
 本発明のプラズマディスプレイ装置は、走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたパネルと、走査電極に走査パルスを印加しデータ電極に書込みパルスを印加する書込み期間と、輝度重みに応じた数の維持パルスを表示電極対に印加する維持期間とを有する複数のサブフィールドで1フィールドを構成してパネルを駆動する駆動回路とを備えたプラズマディスプレイ装置である。そして、駆動回路は、最も輝度重みの大きいサブフィールドと2番目に輝度重みが大きいサブフィールドとが連続しないように各サブフィールドに輝度重みを設定し、画像信号の信号レベルの大きさにもとづき維持パルスの発生を停止するサブフィールドを設ける。さらに、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、同サブフィールドにおける通常動作時の書込みパルスのパルス幅および走査パルスのパルス幅よりも延長する。 The plasma display apparatus according to the present invention includes a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode and a data electrode, and a write that applies a scan pulse to the scan electrode and applies a write pulse to the data electrode. A plasma display device comprising a drive circuit for driving a panel by forming one field with a plurality of subfields having a period and a sustain period in which a number of sustain pulses corresponding to a luminance weight are applied to a display electrode pair . Then, the drive circuit sets the luminance weight in each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue, and maintains the luminance weight based on the signal level of the image signal. A subfield for stopping the generation of pulses is provided. Further, in the subfield immediately after the subfield where the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the pulse width of the scan pulse in normal operation in the subfield. Than to extend.
 この構成により、高精細度化された大画面のパネルであっても、消費電力を削減するとともに、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、安定した書込み放電を行うことが可能となる。 With this configuration, even for a large-screen panel with high definition, power consumption can be reduced and stable address discharge can be performed in the subfield immediately after the subfield where the generation of the sustain pulse is stopped. It becomes possible.
図1は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネルの構造を示す分解斜視図である。FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. 図2は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネルの電極配列図である。FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention. 図3は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネルの各電極に印加する駆動電圧波形を示す図である。FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of the panel used in the plasma display device according to one embodiment of the present invention. 図4は、本発明の一実施の形態における各サブフィールドの維持期間の動作を概略的に示す図である。FIG. 4 is a diagram schematically showing the operation in the sustain period of each subfield in the embodiment of the present invention. 図5は、維持パルスの発生の有無と安定した書込み放電を発生するめに必要な書込みパルスの振幅との関係を示す特性図である。FIG. 5 is a characteristic diagram showing the relationship between the presence / absence of the sustain pulse and the amplitude of the address pulse necessary for generating a stable address discharge. 図6は、書込みパルスのパルス幅と安定した書込み放電を発生するために必要な書込みパルスの振幅との関係を示す特性図である。FIG. 6 is a characteristic diagram showing the relationship between the pulse width of the address pulse and the amplitude of the address pulse necessary for generating a stable address discharge. 図7は、本発明の一実施の形態における駆動電圧波形を概略的に示す図である。FIG. 7 is a diagram schematically showing a drive voltage waveform in one embodiment of the present invention. 図8は、本発明の一実施の形態におけるプラズマディスプレイ装置の回路ブロック図である。FIG. 8 is a circuit block diagram of the plasma display device according to one embodiment of the present invention. 図9は、本発明の一実施の形態におけるプラズマディスプレイ装置の走査電極駆動回路の構成を示す回路図である。FIG. 9 is a circuit diagram showing a configuration of a scan electrode driving circuit of the plasma display device according to one embodiment of the present invention. 図10は、本発明の一実施の形態におけるプラズマディスプレイ装置の維持電極駆動回路の構成を示す回路図である。FIG. 10 is a circuit diagram showing a configuration of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. 図11は、本発明の一実施の形態におけるプラズマディスプレイ装置のデータ電極駆動回路の構成を示す回路図である。FIG. 11 is a circuit diagram showing a configuration of a data electrode driving circuit of the plasma display device according to one embodiment of the present invention.
 以下、本発明の実施の形態におけるプラズマディスプレイ装置について、図面を用いて説明する。 Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.
 (実施の形態)
 図1は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネル10の構造を示す分解斜視図である。ガラス製の前面基板21上には、走査電極22と維持電極23とからなる表示電極対24が複数形成されている。そして、走査電極22と維持電極23とを覆うように誘電体層25が形成され、その誘電体層25上に保護層26が形成されている。
(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.
 この保護層26は、放電セルにおける放電開始電圧を下げるために、パネルの材料として使用実績があり、ネオン(Ne)およびキセノン(Xe)ガスを封入した場合に2次電子放出係数が大きく耐久性に優れた酸化マグネシウム(MgO)を主成分とする材料で形成されている。 This protective layer 26 has been used as a panel material in order to lower the discharge starting voltage in the discharge cell. When neon (Ne) and xenon (Xe) gas is sealed, the secondary layer 26 has a large secondary electron emission coefficient and is durable. It is made of a material mainly composed of magnesium oxide (MgO).
 背面基板31上にはデータ電極32が複数形成され、データ電極32を覆うように誘電体層33が形成され、さらにその上に井桁状の隔壁34が形成されている。そして、隔壁34の側面および誘電体層33上には赤色(R)、緑色(G)および青色(B)の各色に発光する蛍光体層35が設けられている。 A plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
 これら前面基板21と背面基板31とを、微小な放電空間を挟んで表示電極対24とデータ電極32とが交差するように対向配置する。そして、その外周部をガラスフリット等の封着材によって封着する。そして、その内部の放電空間には、例えばネオンとキセノンの混合ガスを放電ガスとして封入する。なお、本実施の形態では、放電セルにおける発光効率を向上するために、キセノン分圧を約15%にした放電ガスを用いている。 The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas. In the present embodiment, a discharge gas having a xenon partial pressure of about 15% is used in order to improve the light emission efficiency in the discharge cell.
 放電空間は隔壁34によって複数の区画に仕切られており、表示電極対24とデータ電極32とが交差する部分に放電セルが形成されている。そして、これらの放電セルを放電、発光(点灯)することにより、パネル10にカラーの画像が表示される。 The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. A color image is displayed on the panel 10 by discharging and emitting (lighting) these discharge cells.
 なお、パネル10においては、表示電極対24が延伸する方向に配列された連続する3つの放電セル、すなわち、赤色(R)に発光する放電セルと、緑色(G)に発光する放電セルと、青色(B)に発光する放電セルの3つの放電セルで1つの画素が構成される。以下、赤色で発光する放電セルをR放電セル、緑色で発光する放電セルをG放電セル、青色で発光する放電セルをB放電セルと呼称する。 In the panel 10, three continuous discharge cells arranged in the extending direction of the display electrode pair 24, that is, discharge cells that emit red (R), and discharge cells that emit green (G), One pixel is composed of three discharge cells that emit blue (B) light. Hereinafter, red discharge cells are referred to as R discharge cells, green discharge cells are referred to as G discharge cells, and blue discharge cells are referred to as B discharge cells.
 なお、パネル10の構造は上述したものに限られるわけではなく、例えばストライプ状の隔壁を備えたものであってもよい。また、放電ガスの混合比率は、例えば、発光効率を向上するためにキセノン分圧をさらに上げてもよいが、その他の混合比率であってもよい。 Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas may be further increased, for example, in order to improve the luminous efficiency, but may be other mixing ratios.
 図2は、本発明の実施の形態1におけるプラズマディスプレイ装置に用いるパネル10の電極配列図である。パネル10には、行方向(ライン方向)に長いn本の走査電極SC1~走査電極SCn(図1の走査電極22)およびn本の維持電極SU1~維持電極SUn(図1の維持電極23)が配列され、列方向に長いm本のデータ電極D1~データ電極Dm(図1のデータ電極32)が配列されている。そして、1対の走査電極SCi(i=1~n)および維持電極SUiと1つのデータ電極Dj(j=1~m)とが交差した部分に放電セルが形成される。すなわち、1対の表示電極対24上には、m個の放電セルが形成され、m/3個の画素が形成される。そして、放電セルは放電空間内にm×n個形成され、m×n個の放電セルが形成された領域がパネル10の画像表示領域となる。例えば、画素数が1920×1080個のパネルでは、m=1920×3となり、n=1080となる。なお、本実施の形態においては、n=768とするが、本発明は何らこの数値に限定されるものではない。 FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) that are long in the row direction (line direction). Are arranged, and m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). That is, m discharge cells are formed on one display electrode pair 24, and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080. In this embodiment, n = 768, but the present invention is not limited to this value.
 次に、本実施の形態におけるプラズマディスプレイ装置のパネル10の駆動方法について説明する。なお、本実施の形態におけるプラズマディスプレイ装置は、サブフィールド法によって階調表示を行う。サブフィールド法では、1フィールドを時間軸上で複数のサブフィールドに分割し、各サブフィールドに輝度重みをそれぞれ設定する。それぞれのサブフィールドは初期化期間、書込み期間および維持期間を有する。そして、サブフィールド毎に各放電セルの発光・非発光を制御することによってパネル10に画像を表示する。 Next, a method for driving the panel 10 of the plasma display apparatus according to the present embodiment will be described. Note that the plasma display device in this embodiment performs gradation display by a subfield method. In the subfield method, one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Each subfield has an initialization period, an address period, and a sustain period. An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.
 輝度重みとは、各サブフィールドで表示する輝度の大きさの比を表すものであり、各サブフィールドでは輝度重みに応じた数の維持パルスを維持期間に発生する。したがって、例えば、輝度重み「8」のサブフィールドは、輝度重み「1」のサブフィールドの約8倍の輝度で発光し、輝度重み「2」のサブフィールドの約4倍の輝度で発光する。したがって、画像信号に応じた組み合わせで各サブフィールドを選択的に発光させることによって様々な階調を表示し、画像を表示することができる。 The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, various gradations can be displayed and images can be displayed by selectively causing each subfield to emit light in a combination according to the image signal.
 本実施の形態では、1フィールドを10のサブフィールド(第1SF、第2SF、・・・、第10SF)に分割し、各サブフィールドはそれぞれ(1、2、4、10、19、40、4、7、18、35)の輝度重みを有する構成とする例を説明する。このように、本実施の形態では、各サブフィールドの輝度重みを単に昇順(第1SFから第10SFまで、順に輝度重みを大きくすること)に設定するのではなく、第1SFから第6SFまで順に輝度重みを大きくし、その後、第7SFから第10SFまで順に輝度重みを大きくしている。すなわち、最も輝度重みの大きいサブフィールドと2番目に輝度重みが大きいサブフィールドとが連続しないように、各サブフィールドに輝度重みを設定している。 In this embodiment, one field is divided into 10 subfields (first SF, second SF,..., 10th SF), and each subfield is (1, 2, 4, 10, 19, 40, 4). , 7, 18, 35) will be described. As described above, in the present embodiment, the luminance weights of the subfields are not simply set in ascending order (from the first SF to the tenth SF, and the luminance weights are increased in order), but the luminances are sequentially increased from the first SF to the sixth SF. The weight is increased, and then the luminance weight is increased in order from the seventh SF to the tenth SF. That is, the luminance weight is set to each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue.
 各サブフィールドの輝度重みを単に昇順に設定すると、フィールドの後半に発光輝度の高いサブフィールドが集中する。しかし、本実施の形態に示すサブフィールドの構成では、発光輝度の高いサブフィールドがフィールド内で分散するので、例えば、1秒間に50フィールドの画像を表示する画像信号(50フィールド/秒の画像信号、例えば、PAL規格の画像信号等)等を表示する際に、フリッカーと呼ばれる画像のちらつきを低減することができる。 • If the luminance weight of each subfield is simply set in ascending order, the subfields with high emission luminance are concentrated in the latter half of the field. However, in the subfield configuration shown in the present embodiment, subfields with high emission luminance are dispersed in the field, so that, for example, an image signal that displays an image of 50 fields per second (an image signal of 50 fields / second) For example, when displaying a PAL standard image signal or the like, image flicker called flicker can be reduced.
 なお、複数のサブフィールドのうち、1つのサブフィールドの初期化期間においては全ての放電セルに初期化放電を発生する全セル初期化動作を行い、他のサブフィールドの初期化期間においては直前のサブフィールドの維持期間で維持放電を発生した放電セルに対して選択的に初期化放電を発生する選択初期化動作を行う。以下、全セル初期化動作を行うサブフィールドを「全セル初期化サブフィールド」と呼称し、選択初期化動作を行うサブフィールドを「選択初期化サブフィールド」と呼称する。 Of all the subfields, an initializing operation is performed in all the cells to generate an initializing discharge in the initializing period of one subfield, and an immediately preceding period is set in the initializing period of the other subfield. A selective initializing operation for selectively generating an initializing discharge is performed on a discharge cell that has generated a sustaining discharge in the sustain period of the subfield. Hereinafter, the subfield that performs the all-cell initializing operation is referred to as “all-cell initializing subfield”, and the subfield that performs the selective initializing operation is referred to as “selective initializing subfield”.
 本実施の形態では、第1SFの初期化期間では全セル初期化動作を行い、第2SF~第10SFの初期化期間では選択初期化動作を行う例を説明する。これにより、画像の表示に関係のない発光は第1SFにおける全セル初期化動作の放電にともなう発光のみとなる。したがって、維持放電を発生しない黒表示領域の輝度である黒輝度は全セル初期化動作における微弱発光だけとなり、パネル10にコントラストの高い画像を表示することが可能となる。 In this embodiment, an example will be described in which the all-cell initializing operation is performed in the initializing period of the first SF and the selective initializing operation is performed in the initializing periods of the second SF to the tenth SF. Thereby, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the first SF. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge occurs, is only weak light emission in the all-cell initialization operation, and an image with high contrast can be displayed on the panel 10.
 また、各サブフィールドの維持期間においては、それぞれのサブフィールドの輝度重みに所定の比例定数を乗じた数の維持パルスを表示電極対24のそれぞれに印加する。この比例定数が輝度倍率である。 In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is applied to each display electrode pair 24. This proportionality constant is the luminance magnification.
 なお、維持期間においては、それぞれのサブフィールドの輝度重みに所定の輝度倍率を乗じた数の維持パルスを、走査電極22および維持電極23のそれぞれに印加する。したがって、例えば、輝度倍率が2倍のとき、輝度重み「2」のサブフィールドの維持期間では、走査電極22と維持電極23とにそれぞれ4回ずつ維持パルスを印加する。そのため、その維持期間で発生する維持パルスの数は8となる。 In the sustain period, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each of scan electrode 22 and sustain electrode 23. Therefore, for example, when the luminance magnification is two times, the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.
 しかし、本実施の形態は、1フィールドを構成するサブフィールドの数や各サブフィールドの輝度重みが上記の値に限定されるものではない。また、画像信号等にもとづいてサブフィールド構成を切り換える構成であってもよい。 However, in the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.
 図3は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネル10の各電極に印加する駆動電圧波形を示す図である。図3には、書込み期間において最初に書込み動作を行う走査電極SC1、書込み期間において最後に書込み動作を行う走査電極SCn、維持電極SU1~維持電極SUn、およびデータ電極D1~データ電極Dmのそれぞれに印加する駆動電圧波形を示す。 FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of panel 10 used in the plasma display device in one embodiment of the present invention. FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown.
 また、図3には、初期化期間に走査電極SC1~走査電極SCnに印加する駆動電圧の波形形状が異なる2つのサブフィールドの駆動電圧波形を示す。この2つのサブフィールドとは、全セル初期化サブフィールドである第1サブフィールド(第1SF)と、選択初期化サブフィールドである第2サブフィールド(第2SF)である。なお、他のサブフィールドにおける駆動電圧波形は、維持期間における維持パルスの発生数が異なる以外は第2SFの駆動電圧波形とほぼ同様である。また、以下における走査電極SCi、維持電極SUi、データ電極Dkは、各電極の中から画像データ(サブフィールド毎の点灯・非点灯を示すデータ)にもとづき選択された電極を表す。 FIG. 3 shows drive voltage waveforms of two subfields having different drive voltage waveform shapes applied to scan electrode SC1 through scan electrode SCn during the initialization period. The two subfields are a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the electrodes based on image data (data indicating lighting / non-lighting for each subfield).
 まず、全セル初期化サブフィールドである第1SFについて説明する。 First, the first SF, which is an all-cell initialization subfield, will be described.
 第1SFの初期化期間前半部では、データ電極D1~データ電極Dm、維持電極SU1~維持電極SUnには、それぞれ電圧0(V)を印加する。走査電極SC1~走査電極SCnには、電圧Vi1を印加する。電圧Vi1は、維持電極SU1~維持電極SUnに対して放電開始電圧未満の電圧に設定する。さらに、走査電極SC1~走査電極SCnに、電圧Vi1から電圧Vi2に向かって緩やかに上昇する傾斜波形電圧を印加する。以下、この傾斜波形電圧を、「ランプ電圧L1」と呼称する。また、電圧Vi2は、維持電極SU1~維持電極SUnに対して放電開始電圧を超える電圧に設定する。なお、このランプ電圧L1の勾配の一例として、約1.3V/μsecという数値を挙げることができる。 In the first half of the initialization period of the first SF, the voltage 0 (V) is applied to each of the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn. Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. Further, a ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn. Hereinafter, this ramp waveform voltage is referred to as “lamp voltage L1”. Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. As an example of the gradient of the lamp voltage L1, a numerical value of about 1.3 V / μsec can be cited.
 このランプ電圧L1が上昇する間に、走査電極SC1~走査電極SCnと維持電極SU1~維持電極SUnとの間、および走査電極SC1~走査電極SCnとデータ電極D1~データ電極Dmとの間に、それぞれ微弱な初期化放電が持続して発生する。そして、走査電極SC1~走査電極SCn上に負の壁電圧が蓄積され、データ電極D1~データ電極Dm上および維持電極SU1~維持電極SUn上には正の壁電圧が蓄積される。この電極上の壁電圧とは、電極を覆う誘電体層上、保護層上、蛍光体層上等に蓄積された壁電荷により生じる電圧を表す。 While ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, Each weak initializing discharge is continuously generated. Negative wall voltage is accumulated on scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated on data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
 初期化期間後半部では、維持電極SU1~維持電極SUnには正の電圧Ve1を印加し、データ電極D1~データ電極Dmには電圧0(V)を印加する。走査電極SC1~走査電極SCnには、電圧Vi3から負の電圧Vi4に向かって緩やかに下降する傾斜波形電圧を印加する。以下、この傾斜波形電圧を、「ランプ電圧L2」と呼称する。電圧Vi3は、維持電極SU1~維持電極SUnに対して放電開始電圧未満となる電圧に設定し、電圧Vi4は放電開始電圧を超える電圧に設定する。なお、このランプ電圧L2の勾配の一例として、例えば、約-2.5V/μsecという数値を挙げることができる。 In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. A ramp waveform voltage that gently falls from voltage Vi3 toward negative voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn. Hereinafter, this ramp waveform voltage is referred to as “lamp voltage L2”. Voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn, and voltage Vi4 is set to a voltage exceeding the discharge start voltage. An example of the gradient of the ramp voltage L2 is a numerical value of about −2.5 V / μsec.
 走査電極SC1~走査電極SCnにランプ電圧L2を印加する間に、走査電極SC1~走査電極SCnと維持電極SU1~維持電極SUnとの間、および走査電極SC1~走査電極SCnとデータ電極D1~データ電極Dmとの間に、それぞれ微弱な初期化放電が発生する。そして、走査電極SC1~走査電極SCn上の負の壁電圧および維持電極SU1~維持電極SUn上の正の壁電圧が弱められ、データ電極D1~データ電極Dm上の正の壁電圧は書込み動作に適した値に調整される。以上により、全ての放電セルで初期化放電を発生する全セル初期化動作が終了する。 While applying ramp voltage L2 to scan electrode SC1 through scan electrode SCn, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn and data electrode D1 through data A weak initializing discharge is generated between each electrode Dm. Then, the negative wall voltage on scan electrode SC1 through scan electrode SCn and the positive wall voltage on sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage on data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for generating the initializing discharge in all the discharge cells is completed.
 以下、全セル初期化動作を行う期間を「全セル初期化期間」と記す。また、全セル初期化動作を行うために発生する駆動電圧波形を「全セル初期化波形」と記す。 Hereinafter, the period for performing the all-cell initialization operation is referred to as “all-cell initialization period”. The drive voltage waveform generated for performing the all-cell initialization operation is referred to as “all-cell initialization waveform”.
 続く書込み期間では、走査電極SC1~走査電極SCnに対しては、電圧Vaの走査パルスを順次印加する。データ電極D1~データ電極Dmに対しては、発光するべき放電セルに対応するデータ電極Dkに正の電圧Vdの書込みパルスを印加する。こうして、各放電セルに選択的に書込み放電を発生する。 In the subsequent address period, a scan pulse of voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn. For data electrode D1 to data electrode Dm, an address pulse of positive voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Thus, an address discharge is selectively generated in each discharge cell.
 具体的には、まず維持電極SU1~維持電極SUnに電圧Ve2を印加し、走査電極SC1~走査電極SCnに電圧Vcを印加する。 Specifically, first, voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.
 次に、最初に書込み動作を行う1行目の走査電極SC1に負の電圧Vaの走査パルスを印加するとともに、データ電極D1~データ電極Dmのうちの1行目において発光するべき放電セルのデータ電極Dkに正の電圧Vdの書込みパルスを印加する。このときデータ電極Dkと走査電極SC1との交差部の電圧差は、外部印加電圧の差(電圧Vd-電圧Va)にデータ電極Dk上の壁電圧と走査電極SC1上の壁電圧との差が加算されたものとなる。これによりデータ電極Dkと走査電極SC1との電圧差が放電開始電圧を超え、データ電極Dkと走査電極SC1との間に放電が発生する。 Next, the scan pulse of the negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is performed first, and the data of the discharge cells that should emit light in the first row of the data electrodes D1 to Dm. An address pulse with a positive voltage Vd is applied to the electrode Dk. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (voltage Vd−voltage Va). It will be added. As a result, the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.
 また、維持電極SU1~維持電極SUnに電圧Ve2を印加しているため、維持電極SU1と走査電極SC1との電圧差は、外部印加電圧の差である(電圧Ve2-電圧Va)に維持電極SU1上の壁電圧と走査電極SC1上の壁電圧との差が加算されたものとなる。このとき、電圧Ve2を、放電開始電圧をやや下回る程度の電圧値に設定することで、維持電極SU1と走査電極SC1との間を、放電には至らないが放電が発生しやすい状態とすることができる。 Further, since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve2−voltage Va) and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.
 これにより、データ電極Dkと走査電極SC1との間に発生する放電を引き金にして、データ電極Dkと交差する領域にある維持電極SU1と走査電極SC1との間に放電を発生することができる。こうして、発光するべき放電セルに書込み放電が発生し、走査電極SC1上に正の壁電圧が蓄積され、維持電極SU1上に負の壁電圧が蓄積され、データ電極Dk上にも負の壁電圧が蓄積される。 Thereby, a discharge generated between the data electrode Dk and the scan electrode SC1 can be triggered to generate a discharge between the sustain electrode SU1 and the scan electrode SC1 in the region intersecting the data electrode Dk. Thus, an address discharge is generated in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Is accumulated.
 このようにして、1行目において発光するべき放電セルで書込み放電を発生して各電極上に壁電圧を蓄積する書込み動作を行う。一方、書込みパルスを印加しなかったデータ電極32と走査電極SC1との交差部の電圧は放電開始電圧を超えないので、書込み放電は発生しない。 In this way, an address operation is performed in which an address discharge is generated in the discharge cells that should emit light in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode 32 and the scan electrode SC1 to which the address pulse is not applied does not exceed the discharge start voltage, so the address discharge does not occur.
 次に、2番目に書込み動作を行う走査電極SC2に走査パルスを印加するとともに、2番目に書込み動作を行う行の発光すべき放電セルに対応するデータ電極Dkに書込みパルスを印加する。走査パルスと書込みパルスとが同時に印加された放電セルでは書込み放電が発生し、書込み動作が行われる。 Next, a scan pulse is applied to the scan electrode SC2 that performs the second address operation, and an address pulse is applied to the data electrode Dk corresponding to the discharge cell that should emit light in the row that performs the second address operation. In the discharge cells to which the scan pulse and the address pulse are simultaneously applied, an address discharge is generated and an address operation is performed.
 以上の書込み動作をn行目の放電セルに至るまで順次行い、書込み期間が終了する。このようにして、書込み期間では、発光するべき放電セルに選択的に書込み放電を発生し、その放電セルに壁電荷を形成する。 The above address operation is sequentially performed until the discharge cell in the n-th row, and the address period ends. In this manner, in the address period, address discharge is selectively generated in the discharge cells to emit light, and wall charges are formed in the discharge cells.
 続く維持期間では、まず維持電極SU1~維持電極SUnに電圧0(V)を印加するとともに走査電極SC1~走査電極SCnに正の電圧Vsusの維持パルスを印加する。書込み放電を発生した放電セルでは、走査電極SCiと維持電極SUiとの電圧差が、維持パルスの電圧Vsusに走査電極SCi上の壁電圧と維持電極SUi上の壁電圧との差が加算されたものとなる。 In the subsequent sustain period, voltage 0 (V) is first applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of positive voltage Vsus is applied to scan electrode SC1 through scan electrode SCn. In the discharge cell in which the address discharge is generated, the voltage difference between the scan electrode SCi and the sustain electrode SUi is obtained by adding the difference between the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi to the sustain pulse voltage Vsus. It will be a thing.
 これにより、走査電極SCiと維持電極SUiとの電圧差が放電開始電圧を超え、走査電極SCiと維持電極SUiとの間に維持放電が発生する。そして、この放電により発生した紫外線により蛍光体層35が発光する。また、この放電により、走査電極SCi上に負の壁電圧が蓄積され、維持電極SUi上に正の壁電圧が蓄積される。さらに、データ電極Dk上にも正の壁電圧が蓄積される。書込み期間において書込み放電が発生しなかった放電セルでは維持放電は発生せず、初期化期間の終了時における壁電圧が保たれる。 Thereby, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. Further, due to this discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
 続いて、走査電極SC1~走査電極SCnには電圧0(V)を印加し、維持電極SU1~維持電極SUnには電圧Vsusの維持パルスを印加する。維持放電を発生した放電セルでは、維持電極SUiと走査電極SCiとの電圧差が放電開始電圧を超える。これにより、再び維持電極SUiと走査電極SCiとの間に維持放電が発生し、維持電極SUi上に負の壁電圧が蓄積され、走査電極SCi上に正の壁電圧が蓄積される。 Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vsus is applied to sustain electrode SU1 through sustain electrode SUn. In the discharge cell that has generated the sustain discharge, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage. As a result, a sustain discharge is generated again between sustain electrode SUi and scan electrode SCi, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.
 以降同様に、走査電極SC1~走査電極SCnと維持電極SU1~維持電極SUnとに、輝度重みに所定の輝度倍率を乗じた数の維持パルスを交互に印加する。こうすることで、書込み期間において書込み放電を発生した放電セルで維持放電が継続して発生する。 Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. By doing so, sustain discharge is continuously generated in the discharge cells that have generated address discharge in the address period.
 そして、維持期間における維持パルスの発生後に、走査電極SC1~走査電極SCnに、電圧0(V)から電圧Vrに向かって緩やかに上昇する上り傾斜波形電圧を印加する。以下、この上り傾斜波形電圧を「消去ランプ電圧L3」と呼称する。これにより、維持放電を発生した放電セルにおいて、微弱な放電を持続して発生し、データ電極Dk上の正の壁電圧を残したまま、走査電極SCiおよび維持電極SUi上の壁電圧の一部または全部を消去する。 Then, after the sustain pulse is generated in the sustain period, an upward ramp waveform voltage that gently rises from voltage 0 (V) toward voltage Vr is applied to scan electrode SC1 through scan electrode SCn. Hereinafter, this upward ramp waveform voltage is referred to as “erasing ramp voltage L3”. As a result, a weak discharge is continuously generated in the discharge cell in which the sustain discharge is generated, and a part of the wall voltage on the scan electrode SCi and the sustain electrode SUi is left while the positive wall voltage on the data electrode Dk remains. Or erase everything.
 具体的には、維持電極SU1~維持電極SUnおよびデータ電極D1~データ電極Dmには電圧0(V)を印加したまま、ベース電位である電圧0(V)から電圧Vrに向かって上昇する消去ランプ電圧L3を、ランプ電圧L1よりも急峻な勾配で発生し、走査電極SC1~走査電極SCnに印加する。この勾配は、例えば、約10V/μsecである。電圧Vrを放電開始電圧を超える電圧に設定することにより、維持放電を発生した放電セルの維持電極SUiと走査電極SCiとの間で、微弱な放電が発生する。 Specifically, erasing that rises from voltage 0 (V), which is the base potential, toward voltage Vr while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. Ramp voltage L3 is generated with a steeper slope than ramp voltage L1, and is applied to scan electrode SC1 through scan electrode SCn. This gradient is, for example, about 10 V / μsec. By setting the voltage Vr to a voltage exceeding the discharge start voltage, a weak discharge is generated between the sustain electrode SUi and the scan electrode SCi of the discharge cell that has generated the sustain discharge.
 そして、この微弱な放電は、走査電極SC1~走査電極SCnへの印加電圧が放電開始電圧を超えて上昇する期間、持続して発生する。そして、上昇する電圧があらかじめ定めた電圧Vrに到達したら、走査電極SC1~走査電極SCnに印加する電圧を電圧Vrに維持し、その後、ベース電位となる電圧0(V)まで下降する。 The weak discharge is continuously generated during a period in which the voltage applied to scan electrode SC1 through scan electrode SCn rises above the discharge start voltage. When the increasing voltage reaches predetermined voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is maintained at voltage Vr, and then decreases to voltage 0 (V) as the base potential.
 この微弱な放電で発生した荷電粒子は、維持電極SUiと走査電極SCiとの間の電圧差を緩和するように、維持電極SUi上および走査電極SCi上に壁電荷となって蓄積されていく。これにより、走査電極SC1~走査電極SCnと維持電極SU1~維持電極SUnとの間の壁電圧は、走査電極SCiに印加した電圧と放電開始電圧の差、例えば(電圧Vr-放電開始電圧)の程度まで弱められる。すなわち、消去ランプ電圧L3により発生する放電は、消去放電として働く。 The charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thereby, the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn is the difference between the voltage applied to scan electrode SCi and the discharge start voltage, for example, (voltage Vr−discharge start voltage). It is weakened to the extent. That is, the discharge generated by the erase lamp voltage L3 works as an erase discharge.
 その後、走査電極SC1~走査電極SCnを電圧0(V)に戻し、維持期間における維持動作が終了する。 Thereafter, scan electrode SC1 to scan electrode SCn are returned to voltage 0 (V), and the sustain operation in the sustain period ends.
 第2SFの初期化期間では、第1SFにおける初期化期間の前半部を省略した駆動電圧波形を各電極に印加する。維持電極SU1~維持電極SUnには電圧Ve1を、データ電極D1~データ電極Dmには電圧0(V)を、それぞれ印加する。走査電極SC1~走査電極SCnには放電開始電圧未満となる電圧(例えば、電圧0(V))から放電開始電圧を超える負の電圧Vi4に向かって緩やかに下降するランプ電圧L4を印加する。このランプ電圧L4の勾配はランプ電圧L2の勾配と同じであり、その一例として、例えば、約-2.5V/μsecという数値を挙げることができる。 In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period in the first SF is omitted is applied to each electrode. Voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Scan voltage SC1 to scan electrode SCn are applied with a ramp voltage L4 that gradually decreases from a voltage lower than the discharge start voltage (eg, voltage 0 (V)) toward negative voltage Vi4 that exceeds the discharge start voltage. The gradient of the ramp voltage L4 is the same as the gradient of the ramp voltage L2, and an example thereof is a numerical value of about −2.5 V / μsec.
 これにより、直前のサブフィールド(図3では、第1SF)の維持期間で維持放電を発生した放電セルでは微弱な初期化放電が発生する。そして、走査電極SCi上および維持電極SUi上の壁電圧が弱められ、データ電極Dk上の壁電圧も書込み動作に適した値に調整される。一方、直前のサブフィールドの維持期間で維持放電を発生しなかった放電セルでは、初期化放電は発生せず、直前のサブフィールドの初期化期間終了時における壁電荷がそのまま保たれる。 As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge is generated in the sustain period of the immediately preceding subfield (first SF in FIG. 3). Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened, and the wall voltage on data electrode Dk is also adjusted to a value suitable for the write operation. On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield, the initialization discharge does not occur, and the wall charge at the end of the immediately preceding subfield initialization period is maintained.
 このように、第2SFにおける初期化動作は、直前のサブフィールドの維持期間で維持放電を発生した放電セルで初期化放電を発生する選択初期化動作となる。以下、選択初期化動作を行う期間を選択初期化期間と記す。 Thus, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is generated in the discharge cell that has generated the sustaining discharge in the sustain period of the immediately preceding subfield. Hereinafter, a period during which the selective initialization operation is performed is referred to as a selective initialization period.
 第2SFの書込み期間および維持期間では、維持パルスの発生数を除き、各電極に対して第1SFの書込み期間および維持期間と同様の駆動電圧波形を印加する。また、第3SF以降の各サブフィールドでは、維持パルスの発生数を除き、各電極に対して第2SFと同様の駆動電圧波形を印加する。 In the second SF address period and sustain period, except for the number of sustain pulses, a drive voltage waveform similar to that in the first SF address period and sustain period is applied to each electrode. In each subfield after the third SF, the same drive voltage waveform as that of the second SF is applied to each electrode except for the number of sustain pulses.
 以上が、本実施の形態においてパネル10の各電極に印加する駆動電圧波形の概要である。 The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.
 なお、本実施の形態において各電極に印加する電圧値は、例えば、電圧Vi1=145(V)、電圧Vi2=350(V)、電圧Vi3=190(V)、電圧Vi4=-160(V)、電圧Va=-180(V)、電圧Vsus=190(V)、電圧Vr=190(V)、電圧Ve1=125(V)、電圧Ve2=125(V)、電圧Vd=60(V)である。また、電圧Vcは負の電圧Va=-180(V)に正の電圧Vscn=145(V)を重畳することで発生することができ、その場合、電圧Vc=-35(V)となる。ただしこれらの電圧値は、単に一例を挙げただけに過ぎない。各電圧値は、パネル10の特性やプラズマディスプレイ装置の仕様等に合わせて、適宜最適な値に設定することが望ましい。 In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vi1 = 145 (V), voltage Vi2 = 350 (V), voltage Vi3 = 190 (V), voltage Vi4 = −160 (V). , Voltage Va = −180 (V), voltage Vsus = 190 (V), voltage Vr = 190 (V), voltage Ve1 = 125 (V), voltage Ve2 = 125 (V), voltage Vd = 60 (V) is there. The voltage Vc can be generated by superimposing the positive voltage Vscn = 145 (V) on the negative voltage Va = −180 (V). In this case, the voltage Vc = −35 (V). However, these voltage values are merely an example. Each voltage value is desirably set to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.
 次に、各サブフィールドの維持期間の動作について説明する。まず、画像表示品質の低下を防止しつつ消費電力を抑制する方法について説明する。 Next, the operation during the maintenance period of each subfield will be described. First, a method for suppressing power consumption while preventing deterioration in image display quality will be described.
 図4は、本発明の一実施の形態における各サブフィールドの維持期間の動作を概略的に示す図である。図4には、走査電極SCiに印加する駆動電圧波形を示す。なお、図4には、発生を停止した波形を破線で示す。すなわち、図4に破線で示す波形は、通常動作時には発生するが、画像信号に応じて発生を停止する波形である。 FIG. 4 is a diagram schematically showing the operation during the sustain period of each subfield in the embodiment of the present invention. FIG. 4 shows a drive voltage waveform applied to scan electrode SCi. In FIG. 4, a waveform whose generation has been stopped is indicated by a broken line. That is, the waveform shown by the broken line in FIG. 4 is a waveform that occurs during normal operation but stops in response to the image signal.
 上述したように、サブフィールド法では維持放電を発生するサブフィールドと維持放電を発生しないサブフィールドとの組み合わせで発光輝度を制御し、放電セルを階調に応じた輝度で発光させ、パネル10に階調を表示する。したがって、画像信号の信号レベル(階調値)が低く発光輝度が低い画像を表示する際には、輝度重みの大きいサブフィールドで維持放電が発生しない。 As described above, in the subfield method, the emission luminance is controlled by the combination of the subfield that generates the sustain discharge and the subfield that does not generate the sustain discharge, and the discharge cell emits light with the luminance according to the gradation. Display gradation. Therefore, when an image with a low signal level (gradation value) of the image signal and a low emission luminance is displayed, no sustain discharge occurs in the subfield with a large luminance weight.
 そこで、本実施の形態では、画像信号の信号レベル(階調値)の大きさにもとづき、維持パルスの発生を停止するサブフィールドを設けるものとする。 Therefore, in this embodiment, it is assumed that a subfield for stopping the generation of the sustain pulse is provided based on the signal level (gradation value) of the image signal.
 例えば、信号レベルが低く(階調値が小さく)、第6SF(例えば、輝度重み40とする)で維持放電が発生しない画像を表示する際には、第6SFで維持パルスを発生しない。このとき走査電極22に印加する電圧波形は、図4に示した第6SF停止の波形図(上から2番目の波形図)に示す波形となる。 For example, when displaying an image in which the signal level is low (gradation value is small) and the sixth SF (for example, luminance weight 40) and no sustain discharge is generated, no sustain pulse is generated in the sixth SF. The voltage waveform applied to the scan electrode 22 at this time is the waveform shown in the waveform diagram of the sixth SF stop (second waveform diagram from the top) shown in FIG.
 信号レベル(階調値)がさらに低く、第6SFおよび第10SF(例えば、輝度重み35とする)で維持放電が発生しない画像を表示する際には、第6SFおよび第10SFで維持パルスを発生しない。このとき走査電極22に印加する電圧波形は、図4に示した第6、第10SF停止の波形図(上から3番目の波形図)に示す波形となる。 When displaying an image that has a lower signal level (gradation value) and no sustain discharge at the sixth SF and the tenth SF (for example, luminance weight 35), no sustain pulse is generated at the sixth SF and the tenth SF. . The voltage waveform applied to the scan electrode 22 at this time is the waveform shown in the waveform diagram of the sixth and tenth SF stops (third waveform diagram from the top) shown in FIG.
 以降、同様に、信号レベル(階調値)の大きさに応じて、輝度重みの大きいサブフィールドから順に維持パルスの発生を停止する。 Thereafter, similarly, the generation of sustain pulses is stopped in order from the subfield having the largest luminance weight according to the level of the signal level (gradation value).
 なお、図4には、走査電極22に印加する電圧波形を示しているが、維持電極23に印加する電圧波形においても、上述と同様に、信号レベル(階調値)の大きさに応じて、輝度重みの大きいサブフィールドから順に維持パルスの発生を停止する。したがって、走査電極22に印加する維持パルスを停止するサブフィールドでは、維持電極23に印加する維持パルスも、同様に停止する。 FIG. 4 shows the voltage waveform applied to the scan electrode 22, but the voltage waveform applied to the sustain electrode 23 also depends on the signal level (gradation value) in the same manner as described above. Then, the generation of sustain pulses is stopped in order from the subfield with the largest luminance weight. Therefore, in the subfield where the sustain pulse applied to scan electrode 22 is stopped, the sustain pulse applied to sustain electrode 23 is similarly stopped.
 このように、本実施の形態では、信号レベル(階調値)の大きさにもとづき、輝度重みの大きいサブフィールドから順に維持パルスの発生を停止するものとする。これにより、信号レベルが低い画像(階調値が小さい画像)を表示する際に、輝度重みが大きいサブフィールドにおいて維持放電を発生しない場合、そのサブフィールドでは維持パルスの発生を停止することができるので、それらの維持パルスの発生に使用する分の消費電力を削減することができる。 As described above, in this embodiment, the generation of sustain pulses is stopped in order from the subfield having the largest luminance weight based on the magnitude of the signal level (gradation value). Thus, when displaying an image with a low signal level (image with a small gradation value), if no sustain discharge is generated in a subfield with a large luminance weight, generation of a sustain pulse can be stopped in that subfield. Therefore, it is possible to reduce the power consumption for the generation of the sustain pulses.
 なお、維持パルスを発生しないサブフィールドでは、書込み動作および初期化動作も不要となるので、維持パルスとともに、書込みパルス、走査パルス、および初期化動作のためのランプ電圧L4の発生をそれぞれ停止してもよい。これにより、消費電力を削減する効果をさらに高めることができる。 In the sub-field that does not generate the sustain pulse, the write operation and the initialization operation are not required. Therefore, the generation of the write pulse, the scan pulse, and the ramp voltage L4 for the initialization operation is stopped together with the sustain pulse. Also good. Thereby, the effect of reducing power consumption can be further enhanced.
 一方、本発明者は、維持パルスの発生を停止することで、その直後のサブフィールドにおいて書込み動作が不安定になりやすいことを実験的に確認した。 On the other hand, the present inventor experimentally confirmed that the write operation tends to become unstable in the subfield immediately after the generation of the sustain pulse is stopped.
 図5は、維持パルスの発生の有無と安定した書込み放電を発生するために必要な書込みパルスの振幅との関係を示す特性図である。図5には、通常動作のときと、直前のサブフィールドの維持期間において維持パルスの発生を停止したときとの、安定した書込み放電を発生するために必要な書込みパルスの振幅(V)を示している。ただし、この通常動作では、直前のサブフィールドの維持期間において、維持パルスは発生するが、維持放電は発生しない。 FIG. 5 is a characteristic diagram showing the relationship between the presence / absence of the sustain pulse and the amplitude of the address pulse necessary for generating a stable address discharge. FIG. 5 shows the amplitude (V) of the address pulse necessary for generating a stable address discharge during normal operation and when the sustain pulse generation is stopped in the sustain period of the immediately preceding subfield. ing. However, in this normal operation, a sustain pulse is generated in the sustain period of the immediately preceding subfield, but no sustain discharge is generated.
 図5に示すように、維持放電を発生しないときに維持パルスの発生を停止しない通常動作のときには、安定した書込み放電を発生するために必要な書込みパルスの振幅は、約45(V)である。一方、維持放電を発生しないときに維持パルスの発生を停止する場合、その直後のサブフィールドにおいて、安定した書込み放電を発生するために必要な書込みパルスの振幅は、約48(V)であり、通常動作と比較して約3(V)高い。したがって、その分、書込み動作は不安定になりやすい。 As shown in FIG. 5, in the normal operation in which the generation of the sustain pulse is not stopped when the sustain discharge is not generated, the amplitude of the address pulse necessary for generating a stable address discharge is about 45 (V). . On the other hand, when the generation of the sustain pulse is stopped when the sustain discharge is not generated, the amplitude of the address pulse necessary for generating a stable address discharge in the subfield immediately after is about 48 (V), About 3 (V) higher than normal operation. Therefore, the write operation tends to become unstable accordingly.
 これは、維持放電を発生しない場合であっても、維持パルスを放電セルに連続して印加することで、次のサブフィールドにおいて書込み動作を補助する電荷が放電セル内に補充されるためと考えられる。したがって、維持パルスを発生しないことで、その電荷が放電セル内に補充されなくなる。 This is because even when sustain discharge does not occur, the sustain pulse is continuously applied to the discharge cell, so that the charge assisting the address operation is replenished in the discharge cell in the next subfield. It is done. Therefore, by not generating the sustain pulse, the charge is not replenished in the discharge cell.
 そして、その電荷が不足する放電セルにおいては、その電荷が補充された放電セルと比較して、放電が不安定になりやすい。これは、その電荷が不足することで、放電セルに電圧が印加されてから実際に放電が発生するまでの時間(放電遅れ時間)が大きくなるためと考えられる。 And, in a discharge cell whose charge is insufficient, the discharge is likely to be unstable as compared with a discharge cell supplemented with the charge. This is presumably because the shortage of the charge increases the time (discharge delay time) from when a voltage is applied to the discharge cell until when discharge actually occurs.
 なお、放電遅れ時間が大きくなったときに放電が不安定になるのは、放電遅れ時間が大きくなることで、放電が発生するまでの時間がパルス幅(放電セルに電圧が印加される時間)を上回り、放電が発生する前に放電セルの印加電圧が低下するためと考えられる。 The reason why the discharge becomes unstable when the discharge delay time becomes large is that the discharge delay time becomes large, and the time until discharge occurs is a pulse width (the time when voltage is applied to the discharge cell). This is considered to be because the applied voltage of the discharge cell decreases before discharge occurs.
 この放電遅れ時間は、放電セルに印加する電圧を大きくすることで改善する。そして、放電遅れ時間が改善することで、放電の発生も安定する。しかし、放電セルに印加する電圧を大きくすることは、消費電力が増大するため、望ましくない。 This discharge delay time can be improved by increasing the voltage applied to the discharge cell. And the generation | occurrence | production of discharge is also stabilized by improving discharge delay time. However, increasing the voltage applied to the discharge cell is not desirable because it increases power consumption.
 しかしながら、本願発明者は、書込み動作時に、放電遅れ時間に応じてパルス幅を大きくすれば、放電セルに印加する電圧を大きくせずとも、安定した書込み放電を発生することが可能であることを、実験により確認した。 However, the inventor of the present application can generate a stable address discharge without increasing the voltage applied to the discharge cells by increasing the pulse width according to the discharge delay time during the address operation. This was confirmed by experiments.
 図6は、書込みパルスのパルス幅と安定した書込み放電を発生するために必要な書込みパルスの振幅との関係を示す特性図である。図6において、横軸は、書込みパルスのパルス幅(μsec)を表し、縦軸は、安定した書込み放電を発生するために必要な書込みパルスの振幅(V)を表す。なお、この実験では、走査パルスのパルス幅も、書込みパルスに合わせて変更していいる。 FIG. 6 is a characteristic diagram showing the relationship between the pulse width of the address pulse and the amplitude of the address pulse necessary for generating a stable address discharge. In FIG. 6, the horizontal axis represents the pulse width (μsec) of the address pulse, and the vertical axis represents the amplitude (V) of the address pulse necessary for generating a stable address discharge. In this experiment, the pulse width of the scan pulse is also changed in accordance with the write pulse.
 例えば、図6に示す例では、書込みパルスのパルス幅および走査パルスのパルス幅を0.95μsecに設定したときには、安定した書込み放電を発生するために必要な書込みパルスの振幅は48(V)であった。一方、書込みパルスのパルス幅および走査パルスのパルス幅を1.05μsecに設定したときには、安定した書込み放電を発生するために必要な書込みパルスの振幅は45(V)であった。このように、書込みパルスのパルス幅および走査パルスのパルス幅を0.95μsecから1.05μsecへと0.1μsec延長することで、安定した書込み放電を発生するために必要な書込みパルスの振幅を、48(V)から45(V)へと低減することができた。 For example, in the example shown in FIG. 6, when the pulse width of the address pulse and the pulse width of the scan pulse are set to 0.95 μsec, the amplitude of the address pulse necessary to generate a stable address discharge is 48 (V). there were. On the other hand, when the pulse width of the address pulse and the pulse width of the scan pulse were set to 1.05 μsec, the amplitude of the address pulse necessary for generating a stable address discharge was 45 (V). Thus, by extending the pulse width of the address pulse and the pulse width of the scan pulse from 0.95 μsec to 1.05 μsec by 0.1 μsec, the amplitude of the address pulse necessary for generating a stable address discharge is The voltage could be reduced from 48 (V) to 45 (V).
 したがって、図5に示した特性と図6に示した特性とを比較すると、維持パルスの発生を停止したサブフィールドの直後のサブフィールドであっても、書込みパルスのパルス幅を0.95μsecから1.05μsecに延長することで、書込みパルスの振幅を大きくせずとも、通常動作のときと同様の安定した書込み放電を発生することが可能なことがわかる。 Therefore, when the characteristics shown in FIG. 5 are compared with the characteristics shown in FIG. 6, even in the subfield immediately after the subfield where the generation of the sustain pulse is stopped, the pulse width of the write pulse is reduced from 0.95 μsec to 1 It can be seen that by extending to 0.05 μsec, it is possible to generate a stable address discharge similar to that during normal operation without increasing the address pulse amplitude.
 このように、パネル10においては、放電遅れ時間に応じて書込みパルスのパルス幅および走査パルスのパルス幅を大きくすることで、書込みパルスの振幅を大きくすることなく安定した書込み放電を発生することが可能である。 As described above, in the panel 10, by increasing the pulse width of the address pulse and the pulse width of the scan pulse according to the discharge delay time, stable address discharge can be generated without increasing the amplitude of the address pulse. Is possible.
 なお、維持パルスの発生停止の有無にかかわらず書込み動作を安定にするために、全てのサブフィールドの書込み期間で書込みパルスのパルス幅および走査パルスのパルス幅を大きくすることも考えられる。しかし、その場合、全てのサブフィールドで書込み期間が延びてしまうため、1フィールドの時間内に全てのサブフィールドが入りきらなくなるおそれがある。さらに、十分に電荷が補充されている放電セルでは、走査パルスのパルス幅を延長することで、書込みパルスが印加されていないにもかかわらず書込み放電が誤って発生することもある(書込み誤放電)。 Note that in order to stabilize the address operation regardless of whether or not the generation of the sustain pulse is stopped, it is conceivable to increase the pulse width of the address pulse and the pulse width of the scan pulse in the address period of all subfields. However, in this case, since the writing period is extended in all the subfields, there is a possibility that not all of the subfields can be entered within the time of one field. Furthermore, in a discharge cell that is sufficiently charged, an address discharge may occur erroneously even if no address pulse is applied by extending the pulse width of the scan pulse (address error discharge). ).
 そこで、本実施の形態では、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、他のサブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長するものとする。 Therefore, in this embodiment, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the scan pulse in the other subfield. It is assumed to extend beyond the pulse width.
 図7は、本発明の一実施の形態における駆動電圧波形を概略的に示す図である。図7には、走査電極SCiおよびデータ電極D1~データ電極Dmに印加する駆動電圧波形を示す。なお、図7には、通常動作時の駆動電圧波形と、第6SFにおいて維持パルスの発生を停止したときの駆動電圧波形とを示す。また、本実施の形態では、この「通常動作」とは、全てのサブフィールドで維持パルスを発生する動作、すなわち、維持パルスの発生を停止するサブフィールドが生じないときの動作のことを表す。 FIG. 7 is a diagram schematically showing a drive voltage waveform in one embodiment of the present invention. FIG. 7 shows drive voltage waveforms applied to scan electrode SCi and data electrode D1 to data electrode Dm. FIG. 7 shows a drive voltage waveform during normal operation and a drive voltage waveform when the generation of the sustain pulse is stopped in the sixth SF. In the present embodiment, the “normal operation” represents an operation for generating a sustain pulse in all subfields, that is, an operation when a subfield for stopping the generation of the sustain pulse does not occur.
 上述したように、本実施の形態では、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、他のサブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長するものとする。例えば、図7に示すように、第6SFにおいて維持パルスの発生を停止するときには、第7SFの書込み期間において書込みパルスのパルス幅および走査パルスのパルス幅を、他のサブフィールド(例えば、第1SF)における書込みパルスのパルス幅および走査パルスのパルス幅よりも延長するものとする。 As described above, in this embodiment, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse in the other subfield. Also, the pulse width of the scanning pulse is extended. For example, as shown in FIG. 7, when the generation of the sustain pulse is stopped in the sixth SF, the pulse width of the write pulse and the pulse width of the scan pulse are changed to other subfields (for example, the first SF) in the write period of the seventh SF. It is assumed that the pulse width is longer than the pulse width of the write pulse and the scan pulse.
 ただし、これは、通常動作時において書込みパルスのパルス幅および走査パルスのパルス幅が全てのサブフィールドで互いに等しい、という条件の下でのことである。 However, this is under the condition that the pulse width of the write pulse and the pulse width of the scan pulse are equal to each other in all subfields during normal operation.
 例えば、サブフィールド毎に書込みパルスのパルス幅および走査パルスのパルス幅を異なる設定とする構成では、維持パルスの発生を停止するサブフィールドの書込みパルスのパルス幅および走査パルスのパルス幅が他のサブフィールドよりも大きいということがある。そして、そのような場合、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて書込みパルスのパルス幅および走査パルスのパルス幅を大きくしても、維持パルスの発生を停止するサブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅に満たない場合もあり得る。 For example, in a configuration in which the pulse width of the write pulse and the pulse width of the scan pulse are set differently for each subfield, the pulse width of the write pulse and the scan pulse of the subfield where the generation of the sustain pulse is stopped are set to other subfields. Sometimes larger than the field. In such a case, even if the pulse width of the write pulse and the pulse width of the scan pulse are increased in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the write in the subfield in which the generation of the sustain pulse is stopped. It may be less than the pulse width of the pulse and the pulse width of the scanning pulse.
 例えば、輝度重みが最も大きいサブフィールド(例えば、第6SF)における書込みパルスのパルス幅および走査パルスのパルス幅が他のサブフィールドよりも大きく、かつそのサブフィールドで維持パルスの発生を停止したときに、続くサブフィールド(第7SF)において書込みパルスのパルス幅および走査パルスのパルス幅を大きくしても、輝度重みが最も大きいサブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅に満たないような場合、本実施の形態においては、維持パルスの発生を停止するサブフィールド(例えば、第6SF)の直後のサブフィールド(例えば、第7SF)において、書込みパルスのパルス幅および走査パルスのパルス幅を、同サブフィールド(この場合には、第7SF)の通常動作時における書込みパルスのパルス幅および走査パルスのパルス幅よりも延長するものとする。 For example, when the pulse width of the writing pulse and the pulse width of the scanning pulse in the subfield (for example, the sixth SF) having the largest luminance weight are larger than those of the other subfields, and generation of the sustain pulse is stopped in that subfield. Even if the pulse width of the address pulse and the pulse width of the scan pulse are increased in the subsequent subfield (seventh SF), the pulse width of the address pulse and the pulse width of the scan pulse in the subfield having the largest luminance weight may not be reached. In the present embodiment, in the subfield (for example, the seventh SF) immediately after the subfield (for example, the sixth SF) for stopping the generation of the sustain pulse, the pulse width of the write pulse and the pulse width of the scanning pulse are Normal operation of the same subfield (in this case, 7th SF) It shall be extended than the pulse width of the pulse width and the scanning pulse of the write pulse in.
 これにより、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、書込みパルスの振幅を大きくすることなく、安定した書込み放電を発生することが可能となる。 This makes it possible to generate a stable address discharge without increasing the address pulse amplitude in the subfield immediately after the subfield where the generation of the sustain pulse is stopped.
 なお、本実施の形態では、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、通常動作時(例えば、約0.95μsec)に対して0.1μsec延長するように設定(例えば、約1.05μsec)している。ただし、この数値は、図6に示した測定結果にもとづくものであり、本発明はパルス幅が何らこれらの数値に限定されるものではない。各パルス幅および延長時間は、パネル10の特性やプラズマディスプレイ装置の仕様等に応じて最適に設定することが望ましい。 In this embodiment, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set to those in the normal operation (for example, about 0.95 μsec). Is set to be extended by 0.1 μsec (for example, about 1.05 μsec). However, these numerical values are based on the measurement results shown in FIG. 6, and the present invention is not limited to these numerical values. Each pulse width and extension time are desirably set optimally according to the characteristics of the panel 10 and the specifications of the plasma display device.
 なお、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいては、書込みパルスのパルス幅および走査パルスのパルス幅を延長することで、書込み期間の長さが延びてしまう。しかし、そのサブフィールドの開始時間をその延長時間分だけ早めれば、最終サブフィールド(例えば、第10SF)の終了時間を後ろに延ばさずに済む。 Note that, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the length of the address period is extended by extending the pulse width of the address pulse and the pulse width of the scan pulse. However, if the start time of the subfield is advanced by the extension time, it is not necessary to extend the end time of the last subfield (for example, the 10th SF) backward.
 例えば、第6SFにおいて維持パルスの発生を停止し、第7SFの書込みパルスのパルス幅および走査パルスのパルス幅を延長することで、第7SFの書込み期間が通常動作時よりも76.8μsec延びたとする。これは、書込みパルスのパルス幅および走査パルスのパルス幅の延長時間を+0.1μsecとし、走査電極22の数を768本として計算した場合の数値である。その場合には、第7SFの開始時間を、通常動作時よりも76.8μsec早めればよい。第6SFでは維持パルスを発生しないので、第7SFの開始時間が早まっても何ら問題はない。また、これにより、各サブフィールドの維持期間の発生タイミングを通常動作時と同等にできるので、輝度の時間的な重心のずれを抑え、フリッカー(表示画像に生じる輝度のちらつき)が発生するおそれを低減することもできる。 For example, it is assumed that the sustain pulse generation is stopped in the sixth SF and the pulse width of the seventh SF write pulse and the pulse width of the scan pulse are extended so that the write period of the seventh SF is increased by 76.8 μsec from the normal operation time. . This is a numerical value when the pulse width of the write pulse and the pulse width of the scan pulse are set to +0.1 μsec and the number of scan electrodes 22 is 768. In that case, the start time of the seventh SF may be advanced by 76.8 μsec from the normal operation time. Since no sustain pulse is generated in the sixth SF, there is no problem even if the start time of the seventh SF is advanced. In addition, since the generation timing of the sustain period of each subfield can be made equal to that during normal operation, the temporal deviation of the center of gravity of the luminance is suppressed, and flicker (the luminance flickering that occurs in the display image) may occur. It can also be reduced.
 次に、本実施の形態におけるプラズマディスプレイ装置の構成について説明する。 Next, the configuration of the plasma display device in the present embodiment will be described.
 図8は、本発明の一実施の形態におけるプラズマディスプレイ装置30の回路ブロック図である。プラズマディスプレイ装置30は、パネル10と駆動回路とを備えている。駆動回路は、画像信号処理回路36、データ電極駆動回路42、走査電極駆動回路43、維持電極駆動回路44、制御信号発生回路40、各回路ブロックに必要な電源を供給する電源回路(図示せず)を備えている。 FIG. 8 is a circuit block diagram of the plasma display device 30 in one embodiment of the present invention. The plasma display device 30 includes a panel 10 and a drive circuit. The drive circuit includes an image signal processing circuit 36, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a control signal generation circuit 40, and a power supply circuit (not shown) that supplies power necessary for each circuit block. ).
 画像信号処理回路36は、入力された画像信号にもとづき、各放電セルに階調値を割り当てる。そして、その階調値を、サブフィールド毎の発光・非発光を示す画像データ(発光・非発光をデジタル信号の「1」、「0」に対応させたデータのこと)に変換する。 The image signal processing circuit 36 assigns a gradation value to each discharge cell based on the input image signal. The gradation value is converted into image data indicating light emission / non-light emission for each subfield (data corresponding to light emission / non-light emission corresponding to digital signals “1” and “0”).
 例えば、入力された画像信号がR信号、G信号、B信号を含むときには、そのR信号、G信号、B信号にもとづき、各放電セルにR、G、Bの各階調値を割り当てる。あるいは、入力された画像信号が輝度信号(Y信号)および彩度信号(C信号、またはR-Y信号およびB-Y信号、またはu信号およびv信号等)を含むときには、その輝度信号および彩度信号にもとづきR信号、G信号、B信号を算出し、その後、各放電セルにR、G、Bの各階調値(1フィールドで表現される階調値)を割り当てる。そして、各放電セルに割り当てたR、G、Bの階調値を、サブフィールド毎の発光・非発光を示す画像データに変換する。 For example, when an input image signal includes an R signal, a G signal, and a B signal, each gradation value of R, G, and B is assigned to each discharge cell based on the R signal, the G signal, and the B signal. Alternatively, when the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal, etc.), the luminance signal and saturation signal Based on the degree signal, R signal, G signal, and B signal are calculated, and thereafter, R, G, and B gradation values (gradation values expressed in one field) are assigned to each discharge cell. Then, the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.
 制御信号発生回路40は、水平同期信号、垂直同期信号にもとづき、各回路ブロックの動作を制御する各種の制御信号を発生する。そして、発生した制御信号をそれぞれの回路ブロック(データ電極駆動回路42、走査電極駆動回路43、維持電極駆動回路44、および画像信号処理回路36等)へ供給する。また、制御信号発生回路40は、画像信号処理回路36からの画像データにもとづき、維持パルスの発生を停止するサブフィールドを決定し、その決定にもとづく制御信号を発生する。さらに、維持パルスの発生を停止するサブフィールドの直後のサブフィールドの書込み期間において、書込みパルスのパルス幅および走査パルスのパルス幅を延長するように制御信号を発生する。 The control signal generation circuit 40 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. Then, the generated control signal is supplied to each circuit block (data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, image signal processing circuit 36, etc.). The control signal generation circuit 40 determines a subfield for stopping the generation of sustain pulses based on the image data from the image signal processing circuit 36, and generates a control signal based on the determination. Further, in the address period of the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the control signal is generated so as to extend the pulse width of the address pulse and the pulse width of the scan pulse.
 走査電極駆動回路43は、初期化波形発生回路、維持パルス発生回路、走査パルス発生回路(図8には示さず)を備え、制御信号発生回路40から供給される制御信号にもとづいて駆動電圧波形を作成し、走査電極SC1~走査電極SCnのそれぞれに印加する。初期化波形発生回路は、初期化期間に、制御信号にもとづいて走査電極SC1~走査電極SCnに印加する初期化波形を発生する。維持パルス発生回路は、維持期間に、制御信号にもとづいて走査電極SC1~走査電極SCnに印加する維持パルスを発生する。走査パルス発生回路は、複数の走査電極駆動IC(走査IC)を備え、書込み期間に、制御信号にもとづいて走査電極SC1~走査電極SCnに印加する走査パルスを発生する。このとき、走査パルス発生回路は、制御信号にもとづくパルス幅で走査パルスを発生する。 Scan electrode drive circuit 43 includes an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 8), and a drive voltage waveform based on a control signal supplied from control signal generation circuit 40. Is applied to each of scan electrode SC1 to scan electrode SCn. The initialization waveform generation circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn based on the control signal during the initialization period. The sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn based on the control signal during the sustain period. The scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn based on a control signal during an address period. At this time, the scan pulse generation circuit generates a scan pulse with a pulse width based on the control signal.
 維持電極駆動回路44は、維持パルス発生回路および電圧Ve1、電圧Ve2を発生する回路を備え(図8には示さず)、制御信号発生回路40から供給される制御信号にもとづいて駆動電圧波形を作成し、維持電極SU1~維持電極SUnのそれぞれに印加する。維持期間では、制御信号にもとづいて維持パルスを発生し、維持電極SU1~維持電極SUnに印加する。 Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit that generates voltage Ve1 and voltage Ve2 (not shown in FIG. 8), and generates a drive voltage waveform based on a control signal supplied from control signal generation circuit 40. It is prepared and applied to each of sustain electrode SU1 through sustain electrode SUn. In the sustain period, a sustain pulse is generated based on the control signal and applied to sustain electrode SU1 through sustain electrode SUn.
 データ電極駆動回路42は、画像データを構成するサブフィールド毎のデータを、各データ電極D1~データ電極Dmに対応する信号に変換する。そして、その信号、および制御信号発生回路40から供給される制御信号にもとづき、各データ電極D1~データ電極Dmを駆動する。書込み期間では、制御信号にもとづくパルス幅の書込みパルスを発生し、各データ電極D1~データ電極Dmに印加する。 The data electrode drive circuit 42 converts the data for each subfield constituting the image data into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the control signal supplied from the control signal generation circuit 40, the data electrodes D1 to Dm are driven. In the address period, an address pulse having a pulse width based on the control signal is generated and applied to each of the data electrodes D1 to Dm.
 次に、走査電極駆動回路43について説明する。 Next, the scan electrode drive circuit 43 will be described.
 図9は、本発明の一実施の形態におけるプラズマディスプレイ装置30の走査電極駆動回路43の構成を示す回路図である。走査電極駆動回路43は、走査電極22側の維持パルス発生回路50と、初期化波形発生回路53と、走査パルス発生回路54とを備えている。走査パルス発生回路54の出力端子のそれぞれは、パネル10の走査電極SC1~走査電極SCnのそれぞれに接続されている。これは、書込み期間において各走査電極22のそれぞれに個別に走査パルスを印加できるようにするためである。 FIG. 9 is a circuit diagram showing a configuration of scan electrode drive circuit 43 of plasma display device 30 in one embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50 on the scan electrode 22 side, initialization waveform generation circuit 53, and scan pulse generation circuit 54. Each of the output terminals of scan pulse generating circuit 54 is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. This is so that the scan pulse can be individually applied to each of the scan electrodes 22 in the address period.
 なお、本実施の形態では、走査パルス発生回路54に入力される電圧を「基準電位A」と記す。また、以下の説明においては、スイッチング素子を導通する動作を「オン」、遮断する動作を「オフ」と表記する。また、図9では、制御信号の信号経路の詳細は省略する。 In the present embodiment, the voltage input to the scan pulse generation circuit 54 is referred to as “reference potential A”. Further, in the following description, the operation of turning on the switching element is expressed as “ON”, and the operation of blocking is described as “OFF”. In FIG. 9, details of the signal path of the control signal are omitted.
 初期化波形発生回路53は、初期化期間において走査パルス発生回路54の基準電位Aをランプ状に上昇または降下させ、図3に示した初期化波形を発生する。 The initialization waveform generation circuit 53 raises or lowers the reference potential A of the scan pulse generation circuit 54 in a ramp shape during the initialization period, and generates the initialization waveform shown in FIG.
 維持パルス発生回路50は、電力回収回路51とクランプ回路52とを備えている。 The sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52.
 電力回収回路51は、電力回収用のコンデンサC10、スイッチング素子Q11、スイッチング素子Q12、逆流防止用のダイオードDi11、逆流防止用のダイオードDi12、共振用のインダクタL10を有している。そして、電極間容量CpとインダクタL10とをLC共振させて維持パルスの立ち上がりおよび立ち下がりを行う。 The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a backflow prevention diode Di12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to cause the sustain pulse to rise and fall.
 クランプ回路52は、走査電極SC1~走査電極SCnを電圧Vsusにクランプするためのスイッチング素子Q13、走査電極SC1~走査電極SCnをベース電位である電圧0(V)にクランプするためのスイッチング素子Q14を有している。そして、基準電位Aをスイッチング素子Q13を介して電源VSに接続して走査電極SC1~走査電極SCnを電圧Vsusにクランプし、基準電位Aをスイッチング素子Q14を介して接地して走査電極SC1~走査電極SCnを電圧0(V)にクランプする。 The clamp circuit 52 includes a switching element Q13 for clamping scan electrode SC1 to scan electrode SCn to voltage Vsus, and a switching element Q14 for clamping scan electrode SC1 to scan electrode SCn to voltage 0 (V) which is a base potential. Have. Then, the reference potential A is connected to the power source VS via the switching element Q13, the scan electrodes SC1 to SCn are clamped to the voltage Vsus, and the reference potential A is grounded via the switching element Q14 to scan the scan electrodes SC1 to SC1. The electrode SCn is clamped to a voltage of 0 (V).
 そして、維持パルス発生回路50は、制御信号発生回路40から供給される制御信号にもとづき、スイッチング素子Q11、スイッチング素子Q12、スイッチング素子Q13、スイッチング素子Q14の導通(オン)と遮断(オフ)とを切り換えることによって電力回収回路51とクランプ回路52とを動作させ、維持パルスを発生する。 Based on the control signal supplied from control signal generating circuit 40, sustain pulse generating circuit 50 conducts (on) and interrupts (off) switching element Q11, switching element Q12, switching element Q13, and switching element Q14. By switching the power recovery circuit 51 and the clamp circuit 52, the sustain pulse is generated.
 例えば、維持パルスを立ち上げる際には、スイッチング素子Q11をオンにして電極間容量CpとインダクタL10とを共振させ、電力回収用のコンデンサC10からスイッチング素子Q11、ダイオードDi11、インダクタL10を通して走査電極SC1~走査電極SCnに電力を供給する。そして、走査電極SC1~走査電極SCnの電圧が電圧Vsusに近づいた時点で、スイッチング素子Q13をオンにして、走査電極SC1~走査電極SCnを駆動する回路を電力回収回路51からクランプ回路52に切り換え、走査電極SC1~走査電極SCnを電圧Vsusにクランプする。 For example, when the sustain pulse is raised, the switching element Q11 is turned on to cause the interelectrode capacitance Cp and the inductor L10 to resonate, and from the power recovery capacitor C10 through the switching element Q11, the diode Di11, and the inductor L10, the scan electrode SC1. Power is supplied to scan electrode SCn. When the voltage of scan electrode SC1 through scan electrode SCn approaches voltage Vsus, switching element Q13 is turned on, and the circuit for driving scan electrode SC1 through scan electrode SCn is switched from power recovery circuit 51 to clamp circuit 52. Scan electrode SC1 to scan electrode SCn are clamped to voltage Vsus.
 逆に、維持パルスを立ち下げる際には、スイッチング素子Q12をオンにして電極間容量CpとインダクタL10とを共振させ、電極間容量CpからインダクタL10、ダイオードDi12、スイッチング素子Q12を通して電力回収用のコンデンサC10に電力を回収する。そして、走査電極SC1~走査電極SCnの電圧が電圧0(V)に近づいた時点で、スイッチング素子Q14をオンにして、走査電極SC1~走査電極SCnを駆動する回路を電力回収回路51からクランプ回路52に切り換え、走査電極SC1~走査電極SCnをベース電位である電圧0(V)にクランプする。 Conversely, when the sustain pulse is lowered, the switching element Q12 is turned on to resonate the interelectrode capacitance Cp and the inductor L10. From the interelectrode capacitance Cp, the power recovery power is passed through the inductor L10, the diode Di12, and the switching element Q12. Power is collected in the capacitor C10. When the voltage of scan electrode SC1 through scan electrode SCn approaches voltage 0 (V), switching element Q14 is turned on, and a circuit for driving scan electrode SC1 through scan electrode SCn is connected from power recovery circuit 51 to a clamp circuit. Then, the scan electrode SC1 to the scan electrode SCn are clamped to the voltage 0 (V) which is the base potential.
 そして、維持パルスを発生しないサブフィールドの維持期間では、スイッチング素子Q14をオンにして、走査電極SC1~走査電極SCnを電圧0(V)にクランプしたままにする。 In the sustain period of the subfield where no sustain pulse is generated, switching element Q14 is turned on, and scan electrode SC1 to scan electrode SCn are kept clamped at voltage 0 (V).
 なお、これらのスイッチング素子は、MOSFETやIGBT等の一般に知られた素子を用いて構成することができる。 In addition, these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.
 走査パルス発生回路54は、書込み期間において基準電位Aを負の電圧Vaに接続するためのスイッチ72と、電圧Vscnを発生して基準電位Aに重畳し電圧Vcを発生するための電源VCと、走査電極SC1~走査電極SCnのそれぞれに電圧Vcを印加するためのスイッチング素子QH1~スイッチング素子QHnと、走査電極SC1~走査電極SCnのそれぞれに基準電位Aを印加するためのスイッチング素子QL1~スイッチング素子QLnとを備えている。 The scan pulse generation circuit 54 includes a switch 72 for connecting the reference potential A to the negative voltage Va in the write period, a power supply VC for generating the voltage Vcn by generating the voltage Vscn and superimposing it on the reference potential A, Switching element QH1 to switching element QHn for applying voltage Vc to each of scan electrode SC1 to scan electrode SCn, and switching element QL1 to switching element for applying reference potential A to each of scan electrode SC1 to scan electrode SCn QLn.
 スイッチング素子QH1~スイッチング素子QHn、スイッチング素子QL1~スイッチング素子QLnは複数の出力毎にまとめられIC化されている。このICが走査ICである。すなわち、走査パルス発生回路54は走査電極SC1~走査電極SCnに印加する走査パルスを発生する複数の走査ICを有する。このように、多数のスイッチング素子QH1~スイッチング素子QHn、スイッチング素子QL1~スイッチング素子QLnをIC化することにより、回路をコンパクトにまとめ、回路をプリント基板に搭載する面積(実装面積)を小さくすることができる。さらに、プラズマディスプレイ装置30の製造に要するコストも下げることができる。 The switching elements QH1 to QHn and the switching elements QL1 to QLn are integrated into a plurality of ICs for each output. This IC is a scanning IC. That is, scan pulse generating circuit 54 has a plurality of scan ICs that generate scan pulses to be applied to scan electrode SC1 through scan electrode SCn. In this way, by making a large number of switching elements QH1 to QHn and switching elements QL1 to QLn into an IC, the circuit is compactly integrated and the area (mounting area) for mounting the circuit on the printed circuit board is reduced. Can do. Furthermore, the cost required for manufacturing the plasma display device 30 can be reduced.
 そして、制御信号発生回路40から供給される制御信号にもとづき、走査パルスを印加する走査電極SCiに対しては、スイッチング素子QHiをオフ、スイッチング素子QLiをオンにすることで、スイッチング素子QLiを経由して走査電極SCiに負の電圧Vaの走査パルスを印加する。また、走査パルスを印加しない走査電極SCh(hは、1~nのうちiを除いたもの)に対しては、スイッチング素子QLhをオフ、スイッチング素子QHhをオンにすることで、スイッチング素子QHhを経由して走査電極SChに電圧Vcを印加する。 Then, based on the control signal supplied from the control signal generation circuit 40, the switching element QHi is turned off and the switching element QLi is turned on for the scan electrode SCi to which the scan pulse is applied. Then, the scan pulse of the negative voltage Va is applied to the scan electrode SCi. For the scan electrode SCh to which no scan pulse is applied (h is a value obtained by excluding i from 1 to n), the switching element QLh is turned off and the switching element QHh is turned on, so that the switching element QHh is turned on. Via, the voltage Vc is applied to the scan electrode SCh.
 すなわち、走査パルス発生回路54においては、制御信号にもとづきスイッチング素子QH1~スイッチング素子QHn、スイッチング素子QL1~スイッチング素子QLnを制御することで、走査パルスのパルス幅を制御することができる。 That is, in the scan pulse generation circuit 54, the pulse width of the scan pulse can be controlled by controlling the switching elements QH1 to QHn and the switching elements QL1 to QLn based on the control signal.
 なお、走査パルス発生回路54は、初期化期間では初期化波形発生回路53が出力する電圧波形を出力し、維持期間では維持パルス発生回路50が出力する電圧波形を出力するように、制御信号発生回路40によって制御されるものとする。すなわち、初期化波形発生回路53または維持パルス発生回路50が動作しているときには、走査パルス発生回路54のスイッチング素子QH1~スイッチング素子QHnをオフ、スイッチング素子QL1~スイッチング素子QLnをオンにすることにより、スイッチング素子QL1~スイッチング素子QLnを経由して各走査電極SC1~走査電極SCnに、初期化波形または維持パルスを印加する。 Scan pulse generation circuit 54 generates a control signal so that the voltage waveform output from initialization waveform generation circuit 53 is output during the initialization period, and the voltage waveform output from sustain pulse generation circuit 50 is output during the sustain period. It is assumed that it is controlled by the circuit 40. That is, when the initialization waveform generation circuit 53 or the sustain pulse generation circuit 50 is operating, the switching elements QH1 to QHn of the scan pulse generation circuit 54 are turned off and the switching elements QL1 to QLn are turned on. Then, an initialization waveform or a sustain pulse is applied to each of scan electrode SC1 through scan electrode SCn via switching element QL1 through switching element QLn.
 なお、各回路を制御する制御信号は、制御信号発生回路40から供給される。 A control signal for controlling each circuit is supplied from the control signal generation circuit 40.
 図10は、本発明の一実施の形態におけるプラズマディスプレイ装置30の維持電極駆動回路44の構成を示す回路図である。なお、図10にはパネル10の電極間容量をCpとして示し、走査電極駆動回路43の回路図は省略している。 FIG. 10 is a circuit diagram showing a configuration of sustain electrode drive circuit 44 of plasma display device 30 in one embodiment of the present invention. In FIG. 10, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit diagram of the scan electrode driving circuit 43 is omitted.
 維持電極駆動回路44は、維持パルス発生回路50とほぼ同じ構成の維持パルス発生回路80を備えている。維持パルス発生回路80は、電力回収回路81およびクランプ回路82を備え、パネル10の維持電極SU1~維持電極SUnに接続されている。このように、維持電極駆動回路44の出力電圧は全ての維持電極23に並列に印加される。これは、書込み期間、維持期間のいずれにおいても、維持電極23を走査電極22のように個別に駆動する必要がなく、全ての維持電極23に一斉に駆動電圧を印加すればよいためである。 Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 having substantially the same configuration as sustain pulse generation circuit 50. Sustain pulse generation circuit 80 includes power recovery circuit 81 and clamp circuit 82, and is connected to sustain electrode SU1 through sustain electrode SUn of panel 10. Thus, the output voltage of the sustain electrode drive circuit 44 is applied to all the sustain electrodes 23 in parallel. This is because it is not necessary to individually drive the sustain electrodes 23 like the scan electrodes 22 in both the writing period and the sustain period, and it is sufficient to apply the drive voltage to all the sustain electrodes 23 at the same time.
 電力回収回路81は、電力回収用のコンデンサC20、スイッチング素子Q21、スイッチング素子Q22、逆流防止用のダイオードDi21、逆流防止用のダイオードDi22、共振用のインダクタL20を有している。クランプ回路82は、維持電極SU1~維持電極SUnを電圧Vsusにクランプするためのスイッチング素子Q23、維持電極SU1~維持電極SUnを接地電位(電圧0(V))にクランプするためのスイッチング素子Q24を有している。 The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a backflow prevention diode Di22, and a resonance inductor L20. The clamp circuit 82 includes a switching element Q23 for clamping sustain electrode SU1 to sustain electrode SUn to voltage Vsus, and a switching element Q24 for clamping sustain electrode SU1 to sustain electrode SUn to the ground potential (voltage 0 (V)). Have.
 そして、維持パルス発生回路80は、制御信号発生回路40から出力される制御信号にもとづき各スイッチング素子のオン・オフを切り換えて維持パルスを発生する。そして、n本の維持電極SU1~維持電極SUnに維持パルスを印加する。なお、維持パルス発生回路80の動作は上述した維持パルス発生回路50と同様であるので説明を省略する。 Then, sustain pulse generating circuit 80 switches on / off of each switching element based on a control signal output from control signal generating circuit 40 to generate a sustain pulse. Then, a sustain pulse is applied to n sustain electrodes SU1 to SUn. The operation of sustain pulse generating circuit 80 is the same as that of sustain pulse generating circuit 50 described above, and a description thereof will be omitted.
 そして、維持パルスを発生しないサブフィールドの維持期間では、スイッチング素子Q24をオンにして、維持電極SU1~維持電極SUnを電圧0(V)にクランプしたままにする。 In the sustain period of the subfield in which no sustain pulse is generated, switching element Q24 is turned on, and sustain electrode SU1 through sustain electrode SUn are kept clamped at voltage 0 (V).
 また、維持電極駆動回路44は、電圧Ve1を発生する電源VE1と、電圧Ve1を維持電極SU1~維持電極SUnに印加するためのスイッチング素子Q26、スイッチング素子Q27と、電圧ΔVeを発生する電源ΔVEと、逆流防止用のダイオードDi30と、電圧Ve1に電圧ΔVeを重畳するためのチャージポンプ用のコンデンサC30と、電圧Ve1に電圧ΔVeを重畳して電圧Ve2を発生するためのスイッチング素子Q28、スイッチング素子Q29とを有する。 Further, sustain electrode drive circuit 44 includes a power source VE1 that generates voltage Ve1, a switching element Q26 and switching element Q27 for applying voltage Ve1 to sustain electrode SU1 through sustain electrode SUn, and a power source ΔVE that generates voltage ΔVe. , A backflow prevention diode Di30, a charge pump capacitor C30 for superimposing voltage ΔVe on voltage Ve1, a switching element Q28 for generating voltage Ve2 by superimposing voltage ΔVe on voltage Ve1, and switching element Q29 And have.
 なお、電圧Ve1と電圧Ve2とが互いに同じ電圧値の場合には、コンデンサC30、スイッチング素子Q28、スイッチング素子Q29、電源ΔVEは不要である。 When the voltage Ve1 and the voltage Ve2 are the same voltage value, the capacitor C30, the switching element Q28, the switching element Q29, and the power source ΔVE are not necessary.
 図11は、本発明の一実施の形態におけるプラズマディスプレイ装置30のデータ電極駆動回路42の構成を示す回路図である。データ電極駆動回路42は、スイッチング素子Q1D1~スイッチング素子Q1Dmおよびスイッチング素子Q2D1~スイッチング素子Q2Dmを有している。 FIG. 11 is a circuit diagram showing the configuration of the data electrode drive circuit 42 of the plasma display device 30 according to one embodiment of the present invention. Data electrode drive circuit 42 has switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm.
 データ電極駆動回路42は、スイッチング素子Q1D1~スイッチング素子Q1Dmを介して各データ電極D1~データ電極Dmをそれぞれ独立して電圧Vdにクランプする。また、スイッチング素子Q2D1~Q2Dmを介して各データ電極D1~データ電極Dmをそれぞれ独立して接地し、電圧0(V)にクランプする。このようにしてデータ電極駆動回路42はデータ電極D1~データ電極Dmをそれぞれ独立に駆動し、データ電極D1~データ電極Dmに正の電圧Vdの書込みパルスを印加する。 The data electrode drive circuit 42 clamps the data electrodes D1 to Dm to the voltage Vd independently through the switching elements Q1D1 to Q1Dm. Further, the data electrodes D1 to Dm are independently grounded via the switching elements Q2D1 to Q2Dm and clamped to a voltage of 0 (V). In this way, the data electrode driving circuit 42 independently drives the data electrodes D1 to Dm, and applies an address pulse of the positive voltage Vd to the data electrodes D1 to Dm.
 そして、データ電極駆動回路42においては、制御信号発生回路40から供給される制御信号にもとづき、これらのスイッチング素子Q1D1~スイッチング素子Q1Dmおよびスイッチング素子Q2D1~スイッチング素子Q2Dmの切り換えの時間を制御することで、書込みパルスのパルス幅を変更することができる。 Data electrode drive circuit 42 controls the switching time of switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm based on the control signal supplied from control signal generation circuit 40. The pulse width of the write pulse can be changed.
 以上示したように、本実施の形態では、入力される画像信号の信号レベルの大きさにもとづき、維持パルスの発生を停止するサブフィールドを設けるものとする。これにより、プラズマディスプレイ装置30における消費電力を削減することができる。 As described above, in this embodiment, it is assumed that a subfield for stopping the generation of sustain pulses is provided based on the signal level of the input image signal. Thereby, the power consumption in the plasma display apparatus 30 can be reduced.
 さらに、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、通常動作時の同サブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長するものとする。あるいは、通常動作時における全てのサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅が互いに等しいときには、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を、他のサブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長する。これにより、維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、安定した書込み放電を発生することが可能となる。 Further, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the write pulse and the pulse width of the scan pulse are set as the pulse width of the write pulse and the scan pulse in the same subfield during normal operation. More than that. Alternatively, in all subfields during normal operation, when the pulse width of the write pulse and the pulse width of the scan pulse are equal to each other, in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, The pulse width of the scan pulse is made longer than the pulse width of the write pulse and the pulse width of the scan pulse in the other subfields. Thereby, stable address discharge can be generated in the subfield immediately after the subfield in which the generation of the sustain pulse is stopped.
 さらに、パルス幅を延長することにより書込み期間の長さが延びた分だけ、そのサブフィールドの開始時間を早めるものとする。これにより、書込み期間の長さが延びた場合でも、全てのサブフィールドを1フィールドの時間内に収めることができる。さらに、各サブフィールドの維持期間の発生タイミングを通常動作時と同等にできるので、輝度の時間的な重心のずれを抑え、フリッカーの発生を防止することができる。 Furthermore, it is assumed that the start time of the subfield is advanced by the length of the writing period by extending the pulse width. Thereby, even when the length of the writing period is extended, all the subfields can be accommodated within one field time. Furthermore, since the generation timing of the sustain period of each subfield can be made equal to that during normal operation, it is possible to suppress the temporal deviation of the gravity center of gravity and prevent the occurrence of flicker.
 なお、各サブフィールドに設定される輝度重みの大きさによっては、維持パルスの発生を停止するサブフィールドが1サブフィールドだけであれば、そのサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を延長せずとも書込み動作が不安定にならないこともある。その場合には、維持パルスの発生を停止するサブフィールドが所定回数以上連続したときにのみ、それらのサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を通常動作時の同サブフィールドにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長する構成としてもよい。 Depending on the magnitude of the luminance weight set in each subfield, if there is only one subfield for which the generation of the sustain pulse is stopped, the pulse width of the write pulse in the subfield immediately after that subfield. In addition, the writing operation may not become unstable without extending the pulse width of the scanning pulse. In such a case, only when the subfields for which the generation of sustain pulses is stopped continue for a predetermined number of times, the pulse width of the write pulse and the pulse width of the scan pulse are set in the subfield immediately after those subfields during normal operation. The pulse width of the address pulse and the pulse width of the scan pulse in the same subfield may be extended.
 例えば、維持パルスの発生を停止するサブフィールドが3サブフィールド以上連続したときに、それらのサブフィールドの直後のサブフィールドで書込み動作が不安定になるような場合には、上述の所定回数を3とする。そして、例えば、第4SF、第5SF、第6SFと連続する3サブフィールドで維持パルスの発生を停止するときには、それらのサブフィールドの直後のサブフィールドである第7SFにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を通常動作時の第7SFにおける書込みパルスのパルス幅および走査パルスのパルス幅よりも延長する。例えば、このような構成としてもよい。このような構成の場合、上述した所定回数は、パネルの特性やプラズマディスプレイ装置の仕様等に応じて適切に設定すればよい。 For example, when the subfield for which the generation of the sustain pulse is stopped continues for three or more subfields, the write operation becomes unstable in the subfield immediately after those subfields, the predetermined number of times described above is set to 3 And For example, when the generation of the sustain pulse is stopped in three subfields that are continuous with the fourth SF, the fifth SF, and the sixth SF, the pulse width and scanning of the write pulse are performed in the seventh SF that is a subfield immediately after those subfields. The pulse width of the pulse is made longer than the pulse width of the write pulse and the scan pulse in the seventh SF during normal operation. For example, such a configuration may be used. In the case of such a configuration, the predetermined number of times described above may be appropriately set according to the characteristics of the panel, the specifications of the plasma display device, and the like.
 なお、維持パルスの発生を停止したサブフィールドの直後のサブフィールドにおいて、書込みパルスのパルス幅および走査パルスのパルス幅を延長するときの延長する時間は、安定した書込み放電を発生するために必要な書込みパルスの振幅が、通常動作時と同等になるように設定することが望ましい。 In the subfield immediately after the subfield where the generation of the sustain pulse is stopped, the extension time when extending the pulse width of the address pulse and the pulse width of the scan pulse is necessary to generate a stable address discharge. It is desirable to set the write pulse amplitude to be equivalent to that during normal operation.
 なお、本発明における実施の形態に示した各回路ブロックは、実施の形態に示した各動作を行う電気回路として構成されてもよく、あるいは、同様の動作をするようにプログラミングされたマイクロコンピュータ等を用いて構成されてもよい。 Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
 なお、本実施の形態に示した各制御信号の極性は、何ら上述した極性に限定されるものではない。本実施の形態に示した動作と同様の動作をする構成であれば、上述した極性とは逆の極性であってもかまわない。 Note that the polarity of each control signal shown in the present embodiment is not limited to the polarity described above. As long as the operation is similar to the operation described in this embodiment, the polarity may be opposite to the above polarity.
 なお、本実施の形態では、1画素をR、G、Bの3色の放電セルで構成する例を説明したが、1画素を4色あるいはそれ以上の色の放電セルで構成するパネルにおいても、本実施の形態に示した構成を適用することは可能であり、同様の効果を得ることができる。 In the present embodiment, an example in which one pixel is configured by discharge cells of three colors of R, G, and B has been described. However, in a panel in which one pixel is configured by discharge cells of four colors or more. It is possible to apply the structure shown in this embodiment mode, and the same effect can be obtained.
 なお、上述した駆動回路は一例を示したものであり、駆動回路の構成は上述した構成に限定されるものではない。 Note that the drive circuit described above is merely an example, and the configuration of the drive circuit is not limited to the configuration described above.
 なお、本発明の実施の形態において示した具体的な数値は、画面サイズが50インチ、表示電極対24の数が768のパネル10の特性にもとづき設定したものであって、単に実施の形態における一例を示したものに過ぎない。本発明はこれらの数値に何ら限定されるものではなく、各数値はパネルの特性やプラズマディスプレイ装置の仕様等にあわせて最適に設定することが望ましい。また、これらの各数値は、上述した効果を得られる範囲でのばらつきを許容するものとする。また、サブフィールド数や各サブフィールドの輝度重み等も本発明における実施の形態に示した値に限定されるものではなく、また、画像信号等にもとづいてサブフィールド構成を切り換える構成であってもよい。 The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 768. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Further, the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.
 本発明は、高精細度化された大画面のパネルであっても、消費電力の削減と安定した書込み放電とを両立することが可能であり、パネルの駆動方法およびプラズマディスプレイ装置として有用である。 INDUSTRIAL APPLICABILITY The present invention can achieve both reduction in power consumption and stable address discharge even for a large-screen panel with high definition, and is useful as a panel driving method and a plasma display device. .
 10  パネル
 21  前面基板
 22  走査電極
 23  維持電極
 24  表示電極対
 25,33  誘電体層
 26  保護層
 30  プラズマディスプレイ装置
 31  背面基板
 32  データ電極
 34  隔壁
 35  蛍光体層
 36  画像信号処理回路
 40  制御信号発生回路
 42  データ電極駆動回路
 43  走査電極駆動回路
 44  維持電極駆動回路
 50,80  維持パルス発生回路
 51,81  電力回収回路
 52,82  クランプ回路
 53  初期化波形発生回路
 54  走査パルス発生回路
 72  スイッチ
 Q11,Q12,Q13,Q14,Q21,Q22,Q23,Q24,Q26,Q27,Q28,Q29,QH1~QHn,QL1~QLn,Q1D1~Q1Dm,Q2D1~Q2Dm  スイッチング素子
 C10,C20,C30  コンデンサ
 L10,L20  インダクタ
 Di11,Di12,Di21,Di22,Di30  ダイオード
 L1,L2,L4  ランプ電圧
 L3  消去ランプ電圧
DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 30 Plasma display device 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 36 Image signal processing circuit 40 Control signal generation circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 50, 80 Sustain pulse generation circuit 51, 81 Power recovery circuit 52, 82 Clamp circuit 53 Initialization waveform generation circuit 54 Scan pulse generation circuit 72 Switch Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29, QH1 to QHn, QL1 to QLn, Q1D1 to Q1Dm, Q2D1 to Q2Dm Switching elements C10, C20, C30 Capacitors L10, L 0 inductors Di11, Di12, Di21, Di22, Di30 diodes L1, L2, L4 ramp voltage L3 erasing ramp voltage

Claims (3)

  1. 走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたプラズマディスプレイパネルを、前記走査電極に走査パルスを印加し前記データ電極に書込みパルスを印加する書込み期間と、輝度重みに応じた数の維持パルスを前記表示電極対に印加する維持期間とを有する複数のサブフィールドで1フィールドを構成して駆動するプラズマディスプレイパネルの駆動方法であって、
    最も輝度重みの大きいサブフィールドと2番目に輝度重みが大きいサブフィールドとが連続しないように各サブフィールドに輝度重みを設定し、
    画像信号の信号レベルの大きさにもとづき前記維持パルスの発生を停止するサブフィールドを設け、
    前記維持パルスの発生を停止するサブフィールドが生じない状態を通常動作とし、
    前記維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、前記書込みパルスのパルス幅および前記走査パルスのパルス幅を、前記直後のサブフィールドにおける前記通常動作時の前記書込みパルスのパルス幅および前記走査パルスのパルス幅よりも延長する
    ことを特徴とするプラズマディスプレイパネルの駆動方法。
    A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, an address period in which a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode, and brightness A driving method of a plasma display panel, wherein a plurality of subfields having a sustain period in which a number of sustain pulses corresponding to a weight are applied to the display electrode pair are configured to drive one field,
    Set the luminance weight for each subfield so that the subfield with the largest luminance weight and the subfield with the second largest luminance weight do not continue.
    Providing a subfield for stopping the generation of the sustain pulse based on the magnitude of the signal level of the image signal;
    A state in which a subfield for stopping the generation of the sustain pulse does not occur is a normal operation,
    In the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the address pulse and the pulse width of the scan pulse are set to the pulse width of the address pulse in the normal operation in the immediately following subfield and A method for driving a plasma display panel, wherein the pulse width is longer than a pulse width of the scan pulse.
  2. 維持パルスの発生を停止するサブフィールドが所定回数以上連続したときに、それらサブフィールドの直後のサブフィールドにおいて、前記書込みパルスのパルス幅および前記走査パルスのパルス幅を、前記直後のサブフィールドにおける前記通常動作時の前記書込みパルスのパルス幅および前記走査パルスのパルス幅よりも延長する
    ことを特徴とする請求項1に記載のプラズマディスプレイパネルの駆動方法。
    When subfields for which the generation of sustain pulses is stopped continue for a predetermined number of times or more, in the subfield immediately after those subfields, the pulse width of the write pulse and the pulse width of the scan pulse are set in the subfield immediately after the subfield. 2. The method of driving a plasma display panel according to claim 1, wherein the pulse width of the write pulse and the pulse width of the scan pulse during normal operation are extended.
  3. 走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたプラズマディスプレイパネルと、
    前記走査電極に走査パルスを印加し前記データ電極に書込みパルスを印加する書込み期間と、輝度重みに応じた数の維持パルスを前記表示電極対に印加する維持期間とを有する複数のサブフィールドで1フィールドを構成して前記プラズマディスプレイパネルを駆動する駆動回路とを備えたプラズマディスプレイ装置であって、
    前記駆動回路は、最も輝度重みの大きいサブフィールドと2番目に輝度重みが大きいサブフィールドとが連続しないように各サブフィールドに輝度重みを設定し、
    画像信号の信号レベルの大きさにもとづき前記維持パルスの発生を停止するサブフィールドを設け、
    前記維持パルスの発生を停止するサブフィールドの直後のサブフィールドにおいて、前記書込みパルスのパルス幅および前記走査パルスのパルス幅を、前記直後のサブフィールドにおける通常動作時の前記書込みパルスのパルス幅および前記走査パルスのパルス幅よりも延長する
    ことを特徴とするプラズマディスプレイ装置。
    A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
    1 in a plurality of subfields having an address period in which a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode, and a sustain period in which the number of sustain pulses corresponding to a luminance weight is applied to the display electrode pair. A plasma display device comprising a drive circuit configured to drive the plasma display panel by configuring a field,
    The driving circuit sets a luminance weight in each subfield so that the subfield having the largest luminance weight and the subfield having the second largest luminance weight do not continue.
    Providing a subfield for stopping the generation of the sustain pulse based on the magnitude of the signal level of the image signal;
    In the subfield immediately after the subfield in which the generation of the sustain pulse is stopped, the pulse width of the address pulse and the pulse width of the scan pulse are set as the pulse width of the address pulse in the normal operation in the immediately following subfield and A plasma display device characterized in that it extends longer than the pulse width of a scanning pulse.
PCT/JP2011/000243 2010-01-19 2011-01-19 Plasma display panel driving method and plasma display device WO2011089891A1 (en)

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