JP2001306020A - Method for driving display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving a display panel which realizes a high definition gradation display, while suppressing power consumption. SOLUTION: A unit display period in a video signal is divided into plural divided display periods, and during each divided display period, a pixel data write process for setting each pixel cell to either a light-emitting cell or a non-light-emitting cell according to a pixel data corresponding to the video signal, and a light-emission maintenance process for making only the above light-emitting cells emit light by the light-emitting frequency allocated correspondingly to each weighting during this divided display period are carried out. Luminance distribution of the video signal is obtained for each display line portion in the display panel, and the light-emitting frequency to be allocated to each of this light-emission maintenance processes according to the brightness distribution is altered for each display line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of driving a display panel of a matrix display system.

[0002]

2. Description of the Related Art In recent years, plasma display panels (hereinafter, referred to as PDPs), electroluminescent display panels (hereinafter, referred to as ELDPs), and the like have been put to practical use as display panels of a thin flat matrix display system. These PDPs and ELDPs have n
Pixel cells carrying each pixel are arranged in a matrix of rows × m columns. At this time, the above-mentioned pixel cells have “light emission” and “
Therefore, there are only two states of "non-light emission". Therefore, for a display panel such as the above PDP and ELDP, a gradation using the subfield method is used in order to obtain a halftone luminance corresponding to an input video signal. Drive is performed.

In the subfield method, an input video signal is converted into N-bit pixel data for each pixel, and 1 bit in the input video signal is associated with each of the N-bit bit digits.
The display period of the field is divided into N subfields. The number of times of light emission corresponding to each bit digit of the pixel data is assigned to each subfield. At this time, if the logic level of one bit digit of the N bits is, for example, “1”, light emission is performed by the number of times allocated as described above in the subfield corresponding to the bit digit. On the other hand, when the logic level of the one bit digit is "0", no light is emitted in the subfield corresponding to that bit digit. In the driving using the subfield method, the halftone luminance corresponding to the input video signal is expressed stepwise by the total number of times of light emission executed in each subfield within one field display period.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of driving a display panel which realizes a good gradation display corresponding to an input video signal.

[0005]

A method of driving a display panel according to the present invention is a method of driving a display panel in which a plurality of pixel cells are arranged in a matrix in accordance with a video signal. The unit display period in the video signal is divided into a plurality of divided display periods, and in each of the divided display periods, each of the pixel cells is either a light emitting cell or a non-light emitting cell according to pixel data corresponding to the video signal. Performing a pixel data writing process to be set on one side and a light emission sustaining process of causing only the light emitting cells to emit light for the number of times of light emission allocated in accordance with the weighting of each of the divided display periods. Calculating the luminance distribution of the video signal for each of the divided display during the unit display period according to the luminance distribution. To change for each display line a number between.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a plasma display device equipped with a plasma display panel as the display panel. As shown in FIG. 1, such a plasma display device includes a PDP 10 as a plasma display panel and a driving unit that drives the plasma display panel based on a driving method according to the present invention.

The PDP 10 has m column electrodes D _{1 to} D _m as address electrodes, and n row electrodes X _{1 to} X _n and a row electrode Y ₁ arranged so as to cross each of the column electrodes. ~
Y _n . At this time, the row electrode X and the row electrode Y
The pair forms a row electrode for displaying one display line on the PDP 10. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space. Then, a discharge cell as a pixel cell is formed at each intersection of each row electrode pair and each column electrode. That is, m pixels corresponding to each of the m column electrodes D are formed on one display line.

On the other hand, the A / D converter 1 in the drive section
The input video signal is sampled and converted into, for example, 8-bit pixel data D for each pixel. And
The A / D converter supplies the pixel data D to each of the 1H line luminance distribution analysis circuit 3 and the data conversion circuit 30. Every time the A / D converter 1 supplies the m pieces of pixel data D for one display line, the 1H line luminance distribution analysis circuit 3 performs the processing for one display line based on the m pieces of pixel data D. The luminance distribution at is analyzed. And 1H
The line luminance distribution analysis circuit 3 supplies the cumulative frequency data AC to the drive control circuit 2 based on the analysis result.

FIG. 2 is a diagram showing an example of the internal configuration of the 1H line luminance distribution analysis circuit 3. As shown in FIG. In FIG.
The frequency distribution memory 300 stores all luminance levels “0” that can be expressed as the pixel data D as shown in FIG.
"" 255 "are provided for each of the 256 storage areas. In each recording area, frequency number data DF indicating the number of times pixel data D having the luminance level has been supplied is provided.
_{0 to} DF ₂₅₅ are stored. The frequency data DF _{0 to} D
The initial value of each F ₂₅₅ is “0”.

Each time pixel data D for one pixel is supplied from the A / D converter 1, the frequency distribution measuring circuit 301 decrements only the frequency number data DF corresponding to the luminance level of the pixel data D by one. Increment. The frequency distribution measuring circuit 301 reads out frequency number data DF _{0 to} DF ₂₅₅ from the frequency distribution memory 300 each time the above-described processing for the m pieces of pixel data D for one display line is completed, and calculates the cumulative frequency distribution. The signal is supplied to the circuit 302.

[0011] The cumulative frequency distribution calculation circuit 302 has one display line.
Frequency data DF corresponding to in minutes ₀~ DF₂₅₅The low brightness
Are sequentially accumulated from those corresponding to
The intermediate results are accumulated for each of the luminance levels "0" to "255".
Product frequency data AC₀~ AC₂₅₅Asking. That is,
The cumulative frequency distribution calculation circuit 302 calculates the luminance level “0”: AC₀= DF₀ Brightness level "1": AC₁= DF₀+ DF₁ Brightness level "2": AC_Two= DF₀+ DF₁+ DF_Two ・ ・ ・ Brightness level "255": AC₂₅₅= DF₀+ DF₁+ DF_Two+ DF_Three+ ... + DF₂₅₅ By calculation, it corresponds to each brightness level "0"-"255"
Cumulative frequency data AC₀~ AC₂₅₅Respectively.
You. At this time, the number of pixel data D for one display line is m
Therefore, the maximum value of the cumulative frequency data AC is “m”.
You. Then, the cumulative frequency distribution calculation circuit 302
Product frequency data AC₀~ AC₂₅₅Is supplied to the drive control circuit 2.
You.

Here, the luminance level corresponding to the cumulative frequency data AC whose data value has become greater than 0 is defined as the lowest luminance level B _L0, and the cumulative frequency data AC whose data value first becomes equal to “m” The corresponding brightness level is defined as the highest brightness level _BHI . Accordingly, the range from B _{L0 to} B _HI is the above-described luminance distribution range based on the pixel data for one display line. Hereinafter, in order to simplify the description, the luminance distribution indicated by the lowest luminance level B _L0 to the highest luminance level B _HI in each display line for one field is, for example, one of the four patterns A to D in FIG. Will be described. The pattern A in FIG. 4 has luminance levels “0” to “25”.
This is a case where the luminance distribution is made over all the luminance levels of 5 ". The pattern B in FIG.
This is a case where the luminance distribution is made within a low luminance level range of 28 "or less. The pattern C in FIG.
This is a case where the luminance distribution is performed within the range of the medium luminance level of 4 ″ to “192.” The pattern D in FIG. This is the case where the luminance distribution is made.

The operation of the 1H line luminance distribution analyzing circuit 3 having the above-described configuration will be described below with reference to the transition of the luminance level of m pieces of pixel data D for one display line.
A case where the state is as shown in FIGS. 5A to 5D will be described as an example. 5 (a) to 5 (d) each show an image that gradually shifts to high brightness from the left end of the screen to the right end on one display line. At this time, FIG. 5A shows a case where the luminance levels uniformly appear on one display line at all the luminance levels “0” to “255” that can be expressed as 8-bit pixel data D. FIG. 5B shows a case where the luminance level uniformly appears on one display line within the range of the luminance levels “0” to “128”. FIG. 5C shows luminance levels “64” to “1”.
In the case where the brightness level uniformly appears on one display line within the range of 92 ", FIG. 5D shows the case where the brightness level is within the range of brightness levels" 128 "to" 255 ". This is a case where it appears uniformly on one display line.

Here, first, according to the pixel data D for one display line having the form as shown in FIG.
The frequency distribution for each of the luminance levels "0" to "255" is shown in FIG.
7 (a), the cumulative frequency distribution is as shown in FIG. 7 (a). Here, as shown in FIG. 7A, the luminance level “0” is set to the minimum luminance level B _L0 , and the luminance level “25” is set.
_Assuming that 5 ″ is the highest luminance level B _HI , these B _L0 and B
The range distribution in the luminance range “0” to “255” represented by _HI is pattern A in FIG. 4, and cumulative frequency data AC indicating pattern A is supplied to the drive control circuit 2.

Further, according to the pixel data D for one display line having the form as shown in FIG. 5B, the frequency distribution for each of the luminance levels "0" to "255" is shown in FIG. The cumulative frequency distribution is as shown in FIG. Here, as shown in FIG.
Assuming that “0” is the lowest brightness level B _L0 and the brightness level “128” is the highest brightness level B _HI , the range distribution in the brightness ranges “0” to “128” represented by B _L0 and B _HI is as follows: FIG.
The cumulative frequency data AC indicating the pattern B is supplied to the drive control circuit 2.

Further, according to the pixel data D for one display line having the form shown in FIG. 5C, the frequency distribution for each of the luminance levels "0" to "255" is shown in FIG. The cumulative frequency distribution is as shown in FIG. Here, as shown in FIG.
64 "as the minimum luminance level B _L0 and the luminance level" 192 "
Is the highest luminance level B _HI , the range distribution in the luminance range “64” to “192” represented by these B _L0 and B _HI is
4, the cumulative frequency data AC indicating the pattern C is supplied to the drive control circuit 2.

Further, according to the pixel data D for one display line having a form as shown in FIG. 5D, the frequency distribution for each of the luminance levels "0" to "255" is shown in FIG. The cumulative frequency distribution is as shown in FIG. Here, as shown in FIG.
128 "as the minimum luminance level B _L0 and the luminance level" 25
_Assuming that 5 ″ is the highest luminance level B _HI , these B _L0 and B
The range distribution in the luminance range “128” to “255” represented by _HI is the pattern D in FIG. 4, and the cumulative frequency data AC indicating the pattern D is supplied to the drive control circuit 2.

As described above, the 1H line luminance distribution analysis circuit 3 sequentially analyzes the luminance distribution based on the input pixel data D for one display line, and outputs the cumulative frequency data AC corresponding to the luminance distribution. 2. The drive control circuit 2 takes in the accumulated frequency data AC for each display line for one field. Then, based on the cumulative frequency data AC, the driving sequence for each display line is determined according to the ratio of the number of lines of each luminance distribution pattern.
(Light emission drive pattern). Further, the drive control circuit 2 converts the conversion characteristics of the first data conversion circuit described later (first data conversion table) in accordance with the set drive sequence.
Then, a conversion characteristic (second data conversion table) of the second data conversion circuit 34 is generated, and the number of compression bits in the multiple gradation processing circuit 33 is set.

For example, assuming that the driving capability of the PDP is such that a display period of one field can be gradation-displayed using seven subfields, the average number of scans (the number of write scans) per line is seven. . Based on the average of seven subfields per line (the average number of scans per line is 7), the above-described driving sequence is performed in accordance with the ratio of the number of lines of each luminance distribution pattern so as to be within the standard. (Light emission drive pattern), etc. The luminance distribution in each display line of the input video signal is 4 as shown in FIG.
In the case where two patterns are taken and the ratios are substantially the same, the display line of the pattern A is composed of ten subfields and the display lines of the patterns B, C and D are composed of five subfields, as described later. Set.

FIG. 8 is a diagram showing an internal configuration of the data conversion circuit 30. In FIG. 8, the delay circuit 31
After delaying the pixel data D supplied from the A / D converter 1 by a predetermined time, the pixel data D is delayed by the first data conversion circuit 3.
Feed to 2. The predetermined time is a processing time spent for analyzing a luminance distribution of pixel data for all display lines in one field and setting a drive sequence (light emission drive pattern) and the like for each display line. .

The first data conversion circuit 32 has 8 bits.
0 "to" 255 "becomes 256 the pixel data D may represent luminance levels of gradations" 0 "to" 160 "and converted into a luminance limited pixel data D _P which is suppressed to, multi-gradation this The data is supplied to a processing circuit 33. The first data conversion circuit 32
For example, it is composed of a writable memory. The storage contents (conversion table, that is, conversion characteristics) of such a memory are updated by a conversion table corresponding to the luminance distribution supplied from the drive control circuit 2 and correspond to the luminance distribution of the input pixel data D for one display line. Is set in the conversion characteristic (conversion table). That is, when the luminance distribution for the pixel data for one display line is the pattern A in FIG. 4, the conversion characteristics of the first data conversion circuit 32 are set to the conversion characteristics as shown in FIG. . At this time, the first data conversion circuit 32 converts the pixel data D of the display line into luminance suppression pixel data D _P in the luminance level range of “0” to “160” according to the conversion characteristic of FIG. The data is converted and supplied to the multi-gradation processing circuit 33. When the luminance distribution for the pixel data for one display line is the pattern B in FIG. 4, the conversion characteristic of the first data conversion circuit 32 is as shown in FIG.
The conversion characteristics are set as shown in FIG. At this time, the first
The data conversion circuit 32 converts the pixel data D of the display line into “0” to “16” in 8 bits according to the conversion characteristics shown in FIG.
0 "becomes converted into luminance limited pixel data D _P of the luminance level range, and supplies it to the multi-gradation processing circuit 33. Furthermore, the luminance distribution for one display line of the pixel data is pattern C in FIG. 4 In this case, the conversion characteristics of the first data conversion circuit 32 are set to the conversion characteristics as shown in Fig. 9C, and at this time, the first data conversion circuit 32 sets the conversion characteristics of Fig. 9C. As the pixel data D of the display line in an 8-bit "0" to "160" become converted to luminance limited pixel data D _P of the luminance level range in accordance with, and supplies it to the multi-gradation processing circuit 33. Further, 1 When the luminance distribution with respect to the pixel data for the display line is the pattern D in FIG. 4, the conversion characteristics of the first data conversion circuit 32 are set to the conversion characteristics as shown in FIG. , First data conversion circuit 32
Converts the luminance limited pixel data D _P of the luminance level range of "0" to "160" in 8-bit pixel data D of the display line according to the conversion characteristic of FIG. 9 (d), the multi-gradation this It is supplied to the processing circuit 33.

The multi-gradation processing circuit 33 performs multi-gradation processing such as error diffusion processing with bit compression according to luminance distribution and dither processing on the 8-bit luminance suppression pixel data D _P. Request multi-gradation pixel data D _S. That is, multi-gradation processing circuit 33, 1 if the luminance distribution for the display lines of pixel data a pattern A of Figure 4, the error of the luminance limited pixel data D _P of 8 bits in the display line Two bits are compressed by the diffusion processing and two bits are further compressed by the dither processing. Thus, multi-gradation processing circuit 33 obtains the multi-gradation pixel data D _S of 4 bits. On the other hand, when the luminance distribution with respect to the pixel data for one display line is one of the patterns B to D in FIG. 4, the multi-gradation processing circuit 33 outputs two bits by the error diffusion processing and further performs the dither processing 3
Perform bit compression. Thereby, the multi-gradation processing circuit 3
3, to obtain a multi-gradation pixel data D _S of 3 bits. The 3-bit or 4-bit multi-gradation pixel data D
_S is supplied to the second data conversion circuit 34.

The second data conversion circuit 34 is composed of, for example, a writable memory. The storage contents (conversion table) of this memory are updated with a conversion table corresponding to the luminance distribution supplied from the drive control circuit 2, and converted into a conversion table corresponding to the luminance distribution of the input pixel data D for one display line. Is set. That is, when the luminance distribution for the pixel data for one display line is the pattern A in FIG. 4, the conversion table of the second data conversion circuit 34 is set to the conversion table as shown in FIG. At this time, the second data conversion circuit 34 generates the 4-bit multi-gradation pixel data Ds of the display line according to the conversion table of FIG.
Is converted into 10-bit drive pixel data GD, and this is supplied to the memory 4. On the other hand, when the luminance distribution for the pixel data for one display line is any of the patterns B to D in FIG. 4, the conversion table of the second data conversion circuit 34 is set to the conversion table as shown in FIG. You.
The second data conversion circuit 34 generates 3-bit multi-gradation pixel data Ds for the display line according to the conversion table shown in FIG.
Is converted into 5-bit drive pixel data GD, and this is supplied to the memory 4.

The memory 4 sequentially writes the drive pixel data GD according to a write signal supplied from the drive control circuit 2. Here, when the writing of the drive pixel data GD _{11 to} GD _nm for one screen (n rows and m columns) is completed, the memory 4
The following read operation is performed. In the memory 4, the drive pixel data GD ₁₁ to GD _nm drive pixel data bit groups GDA-1 each were divided for each bit digit, GDA-
2, GDA-3, ..., GDA-N (N is 5 or 10)
Catch as. That is, the driving pixel data GD _{11 to} GD _nm
The grouping of only each first bit is GDA-
GDA-2 is obtained by grouping only the first and second bits.
It is caught as At this time, the drive pixel data bit group GDA is one screen (n rows, m columns) content of and a drive pixel data bits DB ₁₁ to DB _nm. Memory 4 is
The drive pixel data bit groups GDA-1, GDA-2,
GDA-3,..., GDA-N, in order of each driving pixel data bit group GDA, each driving pixel data bit DB
_{11 to} DB _nm are sequentially read out for each display line and supplied to the address driver 6.

The drive control circuit 2 takes in the accumulated frequency data AC for each display line for one field, and, based on the accumulated frequency data AC, the light emission drive format for each display line according to the ratio of the number of lines of each luminance distribution pattern. Set. Then, various timing signals for driving the PDP 10 in accordance with the set light emission drive format are supplied to each of the address driver 6, the first sustain driver 7, and the second sustain driver 8.

As described above, for example, when the luminance distribution in each display line of the input video signal has four patterns as shown in FIG. The display line for pattern A of No. 4 is set to the light emission drive format including ten subfields shown in FIG. FIG. 1 shows a display line in which the luminance distribution for the pixel data of one display line is the pattern B in FIG.
The light emission drive format including five subfields shown in FIG. 2 (b) is set. Also, for a display line in which the luminance distribution with respect to the pixel data for one display line is the pattern C in FIG. 4, a light emission drive format including five subfields shown in FIG. 12C is set.
FIG. 12 shows a display line in which the luminance distribution for the pixel data of one display line is the pattern D in FIG.
The light emission drive format including the five subfields shown in (d) is set.

In the drive formats shown in FIGS. 12A to 12D, at the beginning of the display period of one field, all the discharge cells of the PDP 10 are simultaneously set to "light emitting cells".
Alternatively, a simultaneous reset process Rc for initializing one of the “non-light emitting cells” is executed. In each subfield, each discharge cell is sequentially set for one display line to a "light-emitting cell" or a "non-light-emitting cell" state according to the pixel data, so that a pixel data writing scan for writing pixel data is performed. The incorporation process Wc is performed. Thereafter, the fourteen divided light emission sustaining processes I _{1 to} I _{14 in} which the light emission frequency ratio is [2: 5: 11: 16: 10: 12: 13: 14: 16: 18: 19: 21: 46: 52] Run intermittently.

Here, the light emission drive format is shown in FIG.
In the case of (a), the simultaneous reset process Rc and the divided light emission maintaining process
I₁During the divided light emission maintenance process I₁And I_TwoDuring the split
Travel I_TwoAnd I_ThreeDuring the divided light emission maintenance process I_ThreeAnd I_FourDuring
Split light emission maintenance process I_FourAnd I_FiveDuring the divided light emission maintenance process I₆
And I₇During the divided light emission maintenance process I₈And I₉During, split flash
Maintenance stroke I_TenAnd I₁₁During the divided light emission maintenance process I₁₂And I₁₃
During the divided light emission maintenance process I ₁₃And I₁₄Pixel data between
The data writing process Wc is executed.

[0029] Further, when the light emission driving format in FIG. 12 (b), between the all-resetting step Rc divided light emission sustain process I _1, between the divided light emission sustain process I ₁ and I _2, and the divided light emission sustain process I ₂ The pixel data writing process Wc is performed between I ₃ , the divided light emission sustaining processes I ₃ and I ₄ , and between the divided light emission sustaining processes I ₄ and I ₅ , respectively.
Execute Further, light emission driving format may of FIG. 12 (c), between the all-resetting step Rc divided light emission sustain process I _1, between the divided light emission sustain process I ₅ and I _6, the split light emission sustain process I ₇ and I ₈ during, between the divided light emission sustain process I ₉ and I _10, executes the respective pixel data writing process Wc between the divided light emission sustain process I ₁₁ and I _12.

The light emission drive format is shown in FIG.
In the case of (d), the simultaneous reset process Rc and the divided light emission maintaining process
I₁During the divided light emission maintenance process I₈And I₉During the split
Travel I_TenAnd I₁₁During the divided light emission maintenance process I₁₂And I₁₃of
, Divided light emission maintenance process I₁₃And I ₁₄Pixel data between
The writing process Wc is executed. That is, the simultaneous reset process
Rc and split light emission maintenance process I₁Between all display lines
Then, writing scan of pixel data is performed for one display line at a time.
U.

The divided light emission sustaining processes I ₁ and I ₂ , I ₂
Between I and I ₃ , between I ₃ and I ₄ , and between I ₄ and I ₅ , the luminance distribution is described above only for the discharge cells on the display line showing the pattern A or the pattern B in FIG. The writing scan of the pixel data as described above is performed. At this time, the luminance distribution is shown in FIG.
For the display line indicating the pattern C or the pattern D, the writing scan of the pixel data is not performed and skipped.

Further, during the divided light emission sustaining steps I ₅ and I ₆ ,
The writing scan of the pixel data as described above is performed only on the discharge cells on the display line whose luminance distribution indicates the pattern C in FIG. At this time, the writing scan of the pixel data is not performed on the display line whose luminance distribution indicates the pattern A, B, or D in FIG. Also, during the divided light emission sustaining steps I ₆ and I ₇ , only the discharge cells on the display line whose luminance distribution shows the pattern A in FIG.
The writing scan of the pixel data as described above is performed.
At this time, the writing scan of the pixel data is not performed on the display lines whose luminance distribution indicates the patterns B, C, and D in FIG.

Also, during the divided light emission sustaining steps I ₇ and I ₈ ,
The writing scan of the pixel data as described above is performed only on the discharge cells on the display line whose luminance distribution indicates the pattern C in FIG. At this time, the writing scan of the pixel data is not performed on the display line whose luminance distribution indicates the pattern A, B, or D in FIG. Further, between the divided light emission sustain process I ₈ and I _9, only the discharge cells on the display line indicating the pattern A及D of luminance distribution Figure 4, is implemented writing scanning-mentioned pixel data described above You. At this time, the writing scan of the pixel data is not performed on the display line whose luminance distribution indicates the pattern B or C in FIG.

[0034] Further, between the divided light emission sustain process I ₉ and I _10, only the discharge cells on the display line luminance distribution shows a pattern C in FIG. 4, exemplary writing scanning-mentioned pixel data described above Is done. At this time, the writing scan of the pixel data is not performed on the display line whose luminance distribution indicates the pattern A, B, or D in FIG. or,
Between the divisional light emission sustain process I ₁₀ and I _11, luminance distribution 4
Pixel data write scanning as described above is performed only on the discharge cells on the display lines showing the patterns A and D. At this time, the pixel data writing scan is not performed on the display line whose luminance distribution indicates the pattern B or C in FIG. 4 and skipped.

[0035] Further, between the divided light emission sustain process I ₁₁ and I _12, only the discharge cells on the display line indicating the pattern C of luminance distribution Figure 4, exemplary writing scanning-mentioned pixel data described above Is done. At this time, the pixel data writing scan is not performed on the display line whose luminance distribution indicates the pattern A, B, or D in FIG. 4 and skipped. Further, between the divided light emission sustain process I ₁₂ and I _13, only the discharge cells on the display line indicating the patterns A and D of the luminance distribution is 4, it is implemented writing scanning-mentioned pixel data described above You. At this time, the pixel data writing scan is not performed on the display line whose luminance distribution indicates the pattern B or C in FIG. 4 and skipped.

[0036] Then, between the divided light emission sustain process I ₁₃ and I _14, only the discharge cells on the display line luminance distribution shows a pattern A and D in FIG. 4, the writing scanning-mentioned pixel data described above Is performed. At this time, the pixel data writing scan is not performed on the display line whose luminance distribution indicates the pattern B or C in FIG. 4 and skipped.
A non-light-emitting period NE is provided between the divided light-emission sustaining steps, as shown by an inclined portion in FIG. 12, in which each light-emitting state is stopped for the same time as the time spent for the writing scan. Therefore, the pixel data writing process W
Assuming that the divided light emission sustaining steps in which c does not exist are collectively referred to as one light emission sustaining step Ic, in the light emission driving format shown in FIG. 12A, the display period of one field includes ten subfields SF1 to SF10. It has a subfield configuration. Therefore, the number of writing scans for one display line within the display period of one field is ten. On the other hand, in the light emission drive format shown in FIGS. 12B to 12D, the display period of one field has a configuration of five subfields including subfields SF1 to SF5. Therefore, 1 within the display period of 1 field
The number of writing scans for the display line is five.

Each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 realizes the above operations in each of the simultaneous reset process Rc, the pixel data write process Wc, the light emission sustain process Ic, and the erase process E. To
The column electrodes D _{1 to} D _m , the row electrodes X _{1 to} X _n and Y _{1 of the} PDP 10
To Y _n each applies various drive pulses. FIG. 13 is a diagram illustrating an example of the application timing of the driving pulse.

In FIG. 13, the first subfield SF1 in the light emission drive format of FIG.
Only the application timing in each of SF2 and SF2 is extracted and shown. First, in the simultaneous reset process Rc, the first sustain driver 7 and the second sustain driver 8
Simultaneously applies a negative reset pulse RP _x and positive polarity of the reset pulse RP _Y to occur row electrodes X ₁ to X _n and Y ₁ to Y _n. The application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge uniformly predetermined wall charge in each discharge cell is formed. That is, all the discharge cells in the PDP 10 are initially set to "light emitting cells" once.

Next, in the pixel data writing process Wc,
Driver 6 drives the drive image supplied from the memory 4.
It has a voltage corresponding to the logic level of the elementary data bit DB
And generates a pixel data pulse for each display line.
Column electrode D₁~ D_mTo be applied. For example, sub fee
In the drive SF1, the drive pixel data bit group G
DA-1 first corresponds to the first row, that is, drive
Pixel data bit DB ₁₁, DB₁₂, DB₁₃, ..., DB
_1mIs extracted. And the logical level of each of these DBs
Pixel data consisting of corresponding m pixel data pulses
Pulse group DP1 ₁And the column electrode D₁~ D_mApplied to
You. Next, in the above-mentioned drive pixel data bit group GDA-1
Pixel data bit DB corresponding to the second row₁₁, D
B₁₂, DB ₁₃, ..., DB_1mExtract each. And
M pixel data corresponding to the logic level of each of these DBs
Data pulse group DP1 composed of data pulses_TwoGenerate a
And column electrode D₁~ D_mIs applied. Hereinafter, similarly, 1
Pixel data pulse group DP1 for each display line_Three~ DP1_n
To the column electrode D₁~ D_mIs applied. Also,
In the subfield SF2, the driving pixel data
First, the driving image corresponding to the first row from the GDA-2
Raw data bit DB₁₁, DB₁₂, DB₁₃, ..., DB_1m
Is extracted. Then, for each logical level of these DBs,
Pixel data pulse consisting of m pixel data pulses corresponding to
Luth group DP2₁And the column electrode D₁~ D _mIs applied.
Next, from the driving pixel data bit group GDA-2,
Driving pixel data bit DB corresponding to the second row₁₁, D
B₁₂, DB₁₃, ..., DB_1mExtract each. And
M pixel data corresponding to the logic level of each of these DBs
Data pulse group DP2 composed of data pulses_TwoGenerate a
And column electrode D₁~ D_mIs applied. Hereinafter, similarly, 1
Pixel data pulse group DP2 for each display line_Three~ DP2_n
To the column electrode D₁~ D_mIs applied.

The address driver 6 generates a high-voltage pixel data pulse when the logic level of the driving pixel data bit DB is "1", and generates a low-voltage (0 volt) pulse when the logic level is "0". ) Is generated. Further, in the pixel data writing process Wc, the second sustain driver 8 applies the negative scan pulse SP as shown in FIG. 13 to the row electrode Y ₁ at the same timing as the application timing of each pixel data pulse group DP. successively applied to the ~Y _n. At this time, the “row” to which the scanning pulse SP is applied
Discharge (selective erase discharge) occurs only in the discharge cell at the intersection with the "column" to which the high-voltage pixel data pulse is applied, and the wall charges remaining in the discharge cell are selectively erased. You. By the selective erasing discharge, the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc are “
No discharge occurs in the discharge cells formed in the "column" to which the high-voltage pixel data pulse was not applied, and the cells are initialized in the simultaneous reset process Rc. In other words, the state of the “light emitting cell” is maintained, that is, by the pixel data writing process Wc performed in each subfield, sustain discharge is generated in each discharge cell in the subsequent light emission sustaining process Ic. This is set as a “light emitting cell” or a “non-light emitting cell” where no sustain discharge occurs.

Next, in the light emission sustaining step Ic, the first sustain driver 7 and the second sustain driver 8 are alternately applied to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n as shown in FIG. applying a positive sustain pulses IP _X and IP _Y of. Incidentally, stop the application of the non-luminescent section NE the sustain pulses IP _X, IP _Y, after such non-light emitting zone NE, resumes alternately applying sustain pulses IP _X, IP _Y. At this time, the discharge cells in which the wall charges in the pixel data writing process Wc are remain, i.e. only the "light emitting cell", sustain discharge every time the sustain pulses IP _X and IP _Y are applied Is raised. That is, while such a sustain discharge is generated intermittently, the light emitting state accompanying the sustain discharge is maintained.

The pixel data writing process Wc and the light emission sustaining process Ic as described above are similarly performed for other subfields. Here, the drive control circuit 2 determines that the luminance distribution for the pixel data for one display line is the pattern A in FIG. 4, that is, the entire luminance range in which the luminance level on one display line is "0" to "255". In this case, gradation driving is performed on this one display line in accordance with the light emission drive format shown in FIG. Therefore, each of the first sustain driver 7 and the second sustain driver 8 performs the SF1: 2 (divided light emission sustaining process) in the light emission sustaining process Ic in each of the ten subfields SF1 to SF10 shown in FIG. I ₁ of the number of emissions) SF2: 5 (number of times of light emission divided light emission sustain process I ₂₎ SF3: 11 (number of times of light emission divided light emission sustain process I ₃₎ SF4: 16 (number of times of light emission divided light emission sustain process I ₄₎ SF5: 22 (total number of light emissions of the split light emission sustain process _{I 5 ~I 6) SF6: 27} ( total number of light emissions of the split light emission sustain process _{I 7 ~I 8) SF7: 34} ( divided light emission sustain process I ₉ ~I ₁₀ emission total of) SF8: 40 (total number of light emissions of the split light emission sustain process _{I 11 ~I 12) SF9: 46} ( number of times of light emission divided light emission sustain process I ₁₃₎ SF10: 52 (light emission of the divided light emission sustain process I ₁₄ Number of times) Only the number of times the sustain pulses IP applied to the PDP10.

When the luminance distribution for the pixel data for one display line is the pattern B in FIG. 4, that is, when the luminance distribution on one display line is biased within the low luminance level range, the drive control is performed. The circuit 2 performs gradation driving on this one display line in accordance with the light emission driving format shown in FIG. Therefore, each of the first sustain driver 7 and the second sustain driver 8 is configured as shown in FIG.
In five light emission sustain process Ic of the subfield SF1~SF5 within each shown in (b), SF1: 2 (number of times of light emission divided light emission sustain process I ₁₎ SF2: 5 (number of times of light emission divided light emission sustain process I ₂₎ SF3: 11 (number of times of light emission divided light emission sustain process I ₃₎ SF4: 16 (number of times of light emission divided light emission sustain process I ₄₎ SF5: 221 (divided total number of light emissions of the light emission sustain process I ₅ ~I ₁₄₎ becomes number of times Only the sustain pulse IP is applied to the PDP 10.

When the luminance distribution for the pixel data for one display line is the pattern C in FIG. 4, that is, when the luminance distribution on one display line is biased within the middle luminance level range, the drive control is performed. The circuit 2 performs a gradation drive on the one display line according to the light emission drive format shown in FIG. Therefore, each of the first sustain driver 7 and the second sustain driver 8 is configured as shown in FIG.
In the light emission sustain process Ic of the five sub-fields SF1~SF5 within each shown in (c), SF1: 44 (total number of light emissions of the split light emission sustain process _{I 1 ~I 5) SF2: 25} ( divided light emission sustain process I ₆ total number of light emissions of ~I ₇₎ SF3: 30 (total number of light emissions of the split light emission sustain process _{I 8 ~I 9) SF4: 37} ( total number of light emissions of the split light emission sustain process I ₁₀ ~I ₁₁₎ SF5: 119 (total number of times of light emission in divided light emission sustaining steps I _{12 to} I ₁₄ ) The sustain pulse IP is applied for a certain number of times.

When the luminance distribution for the pixel data for one display line is the pattern D in FIG. 4, that is, when the luminance distribution for one display line is biased within the high luminance level range, the drive control circuit 2 Performs gradation driving on this one display line in accordance with the light emission driving format shown in FIG. Therefore, the first sustain driver 7
Each of the second sustain drivers 8 performs SF1: 83 (the number of times of light emission in the divided light emission sustaining processes I _{1 to} I ₈ ) in the light emission sustaining process Ic in each of the five subfields SF1 to SF5 shown in FIG. total) SF2: 34 (total number of light emissions of the split light emission sustain process _{I 9 ~I 10) SF3: 40} ( total number of light emissions of the split light emission sustain process _{I 11 ~I 12) SF4: 46} ( divided light emission sustain process I the number of light emissions ₁₃₎ SF5: 52 (to apply a number of emissions) becomes number of times only sustain pulses IP of divided light emission sustain process I _14.

As a result, a display luminance corresponding to the total number of sustain discharges generated in the sustain light emission process Ic in each of the subfields SF appears on the screen of the PDP 10. Whether or not to generate the above-described sustain discharge in the sustain emission process Ic of each subfield is determined by whether or not to generate the selective erase discharge in the pixel data writing process Wc in the subfield. 10 and 11
According to the driving pixel data GD shown in FIG.
The selective erase discharge is generated only in the pixel data writing process Wc in one subfield of F. Therefore, the simultaneous reset process Rc of the first subfield SF1 is performed.
The wall charges formed in step (1) remain until the selective erase discharge occurs, and each discharge cell maintains the state of the "light emitting cell". That is, a sustain discharge accompanied by light emission is generated in the light emission sustaining process Ic of each of the subfields (shown by white circles) existing therebetween. Here, the driving pixel data GD
If the luminance distribution for the pixel data for one display line is pattern A in FIG. 4, that is, if the luminance levels on one display line are uniformly distributed within the entire luminance level range,
There are 11 patterns as shown in FIG. Meanwhile, 1
When the luminance distribution for the pixel data for the display line is other than the pattern A in FIG. 4, that is, when the luminance level on one display line is unevenly distributed within a certain luminance level range,
There are six patterns as shown in FIG.

Therefore, when the luminance levels on one display line are uniformly distributed within the entire luminance level range, the driving based on the light emission driving format of FIG. Therefore, according to the ten light emission drive patterns shown in FIG. 10, {0, 2, 7, 18, 34, 56, 83, 117, 157, 203, 255} The display brightness is obtained.

That is, the gradation driving for 11 gradations is performed with the whole luminance range from "0" to "255" as the gradation driving target. On the other hand, when the luminance distribution on one display line is deviated within the low luminance level range, driving based on the light emission driving format of FIG. According to the light emission drive pattern, intermediate display luminance for six gradations of {0, 2, 7, 18, 34, 255} is obtained.

That is, the gradation driving for six gradations is performed only in the low luminance level range from "0" to "128". Further, when the luminance distribution on one display line is deviated within the middle luminance level range, the gradation drive based on the light emission drive format of FIG. According to the light emission driving pattern of the system, intermediate display luminance for six gradations of {0, 44, 69, 99, 136, 255} can be obtained.

In other words, the gradation drive for six gradations is performed only for the middle luminance level range of "64" to "192". When the luminance distribution on one display line is deviated within the high luminance level range, FIG.
Since the gradation drive based on the light emission drive format of (d) is performed, according to the six light emission drive patterns shown in FIG. 11, six gradations of {0, 83, 117, 157, 203, 255} are obtained. Is obtained.

That is, the gradation drive for six gradations is performed with only the high luminance level range of "128" to "255" being subjected to the gradation drive. Note that the luminance levels other than the intermediate luminance levels for the 10 gradations or 6 gradations are obtained in a pseudo manner by the multi-gradation processing circuit 33 described above. In the above embodiment, the ratio of the number of lines of each luminance distribution pattern is obtained based on the cumulative frequency data AC for each display line for one field, and the light emission drive format for each display line is set accordingly. Then, based on this light emission drive format, a conversion characteristic of the first data conversion circuit (first data conversion table) and a conversion characteristic of the second data conversion circuit 34 (second data conversion table) are generated.
The number of compression bits in the multiple gradation processing circuit 33 is set.

For example, if the capability of the driving device of the PDP is such that a display period of one field can be divided into seven sub-fields for gradation display, an average of seven sub-fields per line ( The number of subfields is changed based on the average number of scans per line being 7). For example, when the luminance level is uniformly distributed in the entire luminance range in the input video signal for one display line, ten subfields larger than the average number of subfields are allocated to the one display line. A gradation drive is performed to improve the gradation expression. On the other hand, when the luminance level of the input video signal for one display line is distributed in one of the high, medium, and low luminance level ranges, the average number of sub-fields for one display line is reduced. Six gradation driving is performed by allocating a small number of five subfields. At this time, when the luminance levels are distributed in a relatively narrow range in the input video signal for one display line, the gradation expression power does not decrease even if the number of subfields to be assigned is reduced.

As described above, in the present invention, the number of subfields within one field display period is changed for each display line according to the luminance distribution in the input video signal for one display line. . Therefore, optimal gradation display can be performed for each line according to the image content of the input video signal. In the above embodiment, the case where the luminance distribution in each display line for one field takes one of the four patterns A to D in FIG. 4 is described. However, in an actual video signal, the luminance distribution pattern is innumerable. is there. Therefore, the ratio of the number of lines of these patterns is calculated, and the light emission drive format (the number of divided subfields) of each display line is set so that the total pixel data writing process time within one field display period is substantially constant. ) Will be set.

In the above embodiment, the luminance distribution of the input video signal is measured for each display line, and the number of subfields within one field display period is changed for each display line. However, this may be performed for each of the plurality of display line groups. That is, the luminance distribution of the input video signal may be measured in units of a plurality of display lines, and the number of subfields within one field display period may be changed for each of the plurality of display line groups.

The luminance distribution of the input video signal may be measured in units of a plurality of lines, and the number of subfields within one field display period may be changed for each display line accordingly. In the above embodiment, as shown in FIGS. 10 and 11, the selective erase discharge is generated only in any one of the pixel data writing processes Wc in each subfield SF. However,
If the amount of charged particles remaining in the discharge cells is small, selective erasure discharge may not be satisfactorily generated, and pixel data may not be written normally. Therefore, FIG.
14 is employed instead of the conversion table and the light emission drive pattern of the second data conversion circuit 34 shown in FIG. Further, the one shown in FIG. 15 is employed instead of the conversion table and the light emission drive pattern of the second data conversion circuit 34 shown in FIG. According to the light emission drive patterns shown in FIGS. 14 and 15, the same selective erasing discharge is continuously performed for each discharge cell a plurality of times, so that the selective erasing discharge is reliably generated, and the pixel data of the pixel data is correctly written. Writing is performed.

In the above embodiment, as a method of writing pixel data, a wall charge is previously formed in each discharge cell, and the wall charge is selectively erased in accordance with the pixel data. The above description has been made on the case where a so-called selective erasing address method is adopted. However, the present invention can be similarly applied to a case where a so-called selective write address method in which wall charges are selectively formed according to pixel data as a method of writing pixel data.

FIGS. 16 (a) to 16 (d) are diagrams showing a light emission drive format used when the PDP 10 is driven for gradation by adopting the selective write address method. FIG.
FIG. 18 is a diagram showing a conversion table used in the second data conversion circuit 34 when such a selective write address method is employed, and a light emission drive pattern. FIG. 17 is a diagram showing a conversion table and a light emission drive pattern used in the second data conversion circuit 34 when the one shown in FIG. 10 is applied to the selective write address method. FIG. 18 shows the second data conversion circuit 34 when the one shown in FIG. 11 is applied to the selective write address method.
FIG. 3 is a diagram showing a conversion table and a light emission drive pattern used in the embodiment.

Here, when the selective write address method is employed, as shown in FIGS. 16 (a) to 16 (d), the subfield S when the selective erase address method is employed is employed.
The arrangement of F is inverted. That is, the subfield SF10 (or SF5) is set as the first subfield, and the subfield SF1 is set as the last subfield. In each subfield, the pixel data writing process W
c and the light emission sustaining process Ic are performed, and the simultaneous resetting process Rc is performed only in the first subfield.
This is similar to the case where the selective erase address method as shown in FIGS.

In performing the gradation drive according to the selective write address method, the drive control circuit 2 sets the light emission drive format for each display line according to the ratio of the number of lines of each luminance distribution pattern. For example, when the luminance distribution of each display line of the input video signal takes the four patterns shown in FIG. 4 and their ratios are approximately the same, the drive control circuit 2 sets the light emission drive format as follows. That is, the drive control circuit 2 determines that the luminance distribution for the pixel data for one display line is the pattern A in FIG.
The display line is set to a light emission drive format including ten subfields as shown in FIG. FIG. 1 shows a display line in which the luminance distribution for the pixel data of one display line is the pattern B in FIG.
A light emission drive format including five subfields shown in FIG. 6B is set. Also, for a display line in which the luminance distribution with respect to the pixel data for one display line is the pattern C in FIG. 4, the light emission drive format including five subfields shown in FIG. 16C is set.
FIG. 16 shows a display line in which the luminance distribution for one display line of pixel data is the pattern D in FIG.
The light emission drive format including the five sub-fields shown in (d) is set.

The drive control circuit 2 supplies to the address driver 6, the first sustain driver 7, and the second sustain driver 8 various timing signals for gray-scale driving the PDP 10 in accordance with the set light emission drive format. FIG. 19 shows that the address driver 6, the first sustain driver 7, and the second sustain driver 8 each have a PDP when the selective write address method is employed.
FIG. 3 is a diagram showing application timings of various drive pulses applied to the drive signal 10;

In FIG. 19, FIG.
Extraction of only the application timing in subfield SF5
Is shown. In FIG. 19, the simultaneous reset process R
In c, the first sustain driver 7 and the second sustain driver
The driver 8 resets the row electrodes X and Y of the PDP 10 by resetting.
Luz RP _xAnd RP_YImmediately after applying
The driver 7 applies the erase pulse EP to the row electrode X.₁~ X_nAll at once
Apply. By applying such an erase pulse, an erase discharge is generated.
The wall charges formed in all the discharge cells are erased.
Perish. That is, a selective write address as shown in FIG.
In the simultaneous reset process Rc when the dress method is adopted, P
All the discharge cells in DP10 are in the state of "non-light emitting cell".
Initialized to the state.

In the pixel data writing process Wc, as in the case where the selective erase address method is adopted, the address driver 6 is used.
Generates a pixel data pulse group DP for each row having a voltage corresponding to the logic level of the driving pixel data bit DB, and sequentially applies the group to the column electrodes D _{1 to} D _m for each row. . Further, in the pixel data writing process Wc, the second sustain driver 8 outputs the pixel data pulse group DP as described above.
In each application the same timing, and generates a negative scanning pulse SP, which sequentially applies to the row electrodes Y ₁ to Y _n. At this time, the scanning pulse SP is applied. "
Discharge (selective write discharge) occurs only in the discharge cells at the intersections of the rows and the columns to which the high-voltage pixel data pulse is applied, and wall charges are formed in the discharge cells. As shown in FIGS. 17 and 18, the selective write discharge is generated in the pixel data write process Wc in the subfield corresponding to the bit digit of the logic level "1" in the drive pixel data GD. According to the selective write discharge, the discharge cells initialized to the “non-light emitting cell” state in the simultaneous reset step Rc change to the “light emitting cell” state. No discharge occurs in the discharge cells formed in the "column" to which no data pulse is applied, and the state initialized in the simultaneous reset step Rc, that is, the state of the "non-light emitting cell" is maintained. .

In the light emission sustaining step Ic, the first sustain driver 7 and the second sustain driver 8 alternately apply positive electrodes to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n as shown in FIG. applying the sustain pulses IP _X and IP _Y sex. By applying the sustain pulse IP, a discharge cell in which wall charges are formed in the pixel data writing process Wc;
That is, only the “light-emitting cells” have sustain pulses IP _X and I
Each time P _Y is applied, sustain discharge is performed to maintain a light emitting state accompanying the discharge. At this time, according to the driving pixel data GD shown in FIG. 17 and FIG. In the light emission maintaining step Ic, light emission is maintained for the number of times (period) described in FIGS. 16 (a) to 16 (d).

In the case where the selective write address method as described above is employed, similarly to the case where the selective erase address method is employed, the same selective write discharge is continuously performed for each discharge cell a plurality of times. By doing so, the writing accuracy of the pixel data can be improved. FIGS. 20 and 21 are diagrams showing a conversion table and a light emission drive pattern employed in the second data conversion circuit 34 when the same selective write discharge is continuously performed twice on each discharge cell. It is.

[0065]

As described in detail above, in the present invention,
The luminance distribution of the input video signal is measured for each display line (or a plurality of display lines), and according to this luminance distribution, the sub-line within one field display period is displayed for each display line (or a plurality of display lines). I try to change the number of fields. As a result, it is possible to perform optimal gradation display according to the pattern of the input video signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a plasma display device for grayscale driving a plasma display panel according to a driving method according to the present invention.

FIG. 2 is a diagram showing an internal configuration of a 1H line luminance distribution analysis circuit 3.

FIG. 3 is a diagram showing a memory map of a luminance distribution memory 300.

FIG. 4 is a diagram illustrating an example of a classification form of a luminance distribution in a luminance distribution separating circuit 303;

FIG. 5 is a diagram illustrating an example of a luminance level of a video signal on one display line.

FIG. 6 is a diagram illustrating an example of a frequency for each luminance level in a video signal for one display line.

FIG. 7 is a diagram illustrating an example of an accumulated frequency in a video signal for one display line.

FIG. 8 is a diagram showing an internal configuration of a data conversion circuit 30.

9 is a diagram illustrating data conversion characteristics of the first data conversion circuit 32. FIG.

FIG. 10 is a diagram showing a data conversion table used by a second data conversion circuit and a light emission driving pattern when the luminance distribution for pixel data of one display line is the pattern A of FIG.

FIG. 11 is a diagram showing a case where the luminance distribution for pixel data for one display line is any of the patterns B to D in FIG. 4;
FIG. 3 is a diagram showing a data conversion table employed in a data conversion circuit and a light emission drive pattern.

FIG. 12 is a diagram showing an example of a light emission drive format based on a drive method according to the present invention.

FIG. 13 is a diagram showing application timings of various drive pulses applied when the PDP 10 is driven in gradation according to the light emission drive format shown in FIG.

14 is a diagram illustrating another example of a data conversion table used by the second data conversion circuit 34 when the luminance distribution with respect to pixel data for one display line is the pattern A in FIG. 4, and another example of a light emission driving pattern. is there.

FIG. 15 is a diagram showing a case where the luminance distribution for pixel data of one display line is any of the patterns B to D in FIG. 4;
FIG. 6 is a diagram illustrating another example of a data conversion table employed in the data conversion circuit and a light emission driving pattern.

FIG. 16 is a diagram showing an example of a light emission drive format used when a selective write address method is adopted.

17 shows a data conversion table used by the second data conversion circuit 34 when the luminance distribution for pixel data for one display line becomes the pattern A in FIG. It is a figure showing an example of a pattern.

18 is a data conversion table used by the second data conversion circuit 34 when the luminance distribution with respect to the pixel data for one display line is any of the patterns B to D in FIG. FIG. 7 is a diagram illustrating an example of a light emission drive pattern.

FIG. 19 is a diagram showing application timings of various drive pulses applied when the PDP 10 is driven in gradation according to the light emission drive format shown in FIG.

FIG. 20 shows a case where the selective write address method is adopted,
FIG. 9 is a diagram illustrating another example of a data conversion table used in the data conversion circuit 34 and a light emission drive pattern.

FIG. 21 shows a case where the selective write address method is adopted;
FIG. 9 is a diagram illustrating another example of a data conversion table used in the data conversion circuit 34 and a light emission drive pattern.

[Explanation of Signs of Main Parts]

 2 Drive control circuit 3 1H line luminance distribution analysis circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP 30 Data conversion circuit 32 First data conversion circuit 33 Multi-gradation processing circuit 34 Second data conversion circuit

Continued on the front page (72) Inventor Tetsuro Nagakubo 2680, Nishihanawa, Tatomi-cho, Nakakoma-gun, Yamanashi Prefecture Pioneer Corporation F-Term (reference) JJ05

Claims (15)

[Claims] 1. A display panel driving method for driving a display panel in which a plurality of pixel cells are arranged in a matrix according to a video signal, wherein a unit display period in the video signal is divided into a plurality of divided display periods. In each of the divided display periods, a pixel data writing step of setting each of the pixel cells to one of a light emitting cell and a non-light emitting cell in accordance with pixel data corresponding to the video signal; And performing a light emission sustaining step of emitting only the number of times of light emission allocated in accordance with the weighting of each of the divided display periods, and obtaining a luminance distribution of the video signal for each display line on the display panel. Changing the number of the divided display periods in the unit display period for each display line accordingly. Driving method of Ipanel. 2. The display panel driving method according to claim 1, wherein the luminance distribution is obtained based on a cumulative frequency of each luminance level in the video signal for one display line. 3. A reset step of initializing all the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, The pixel cell is set to one of the non-light emitting cell and the light emitting cell only in the pixel data writing process in any one of the divided display periods. The method for driving a display panel according to claim 1. 4. A reset step of initializing all of the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, In the pixel data writing process in any one of the divided display periods, the pixel cell is set to one of the non-light emitting cell and the light emitting cell, and the one divided display is performed. At least one that exists after the period
2. The display panel driving method according to claim 1, wherein said pixel cell is set to said one state again in said pixel data writing process in said divided display period. 5. The method according to claim 1, wherein the number of the divided display periods is increased when a luminance level range of the luminance distribution in the video signal for one display line is wide as compared with a case where the luminance level range is narrow. Driving method of display panel. 6. A display panel driving method for driving a display panel in which a plurality of pixel cells are arranged in a matrix in accordance with a video signal, wherein a unit display period in the video signal is divided into a plurality of divided display periods. In each of the divided display periods, a pixel data writing step of setting each of the pixel cells to one of a light emitting cell and a non-light emitting cell in accordance with pixel data corresponding to the video signal; And performing a light emission maintaining process of emitting only the number of times of light emission corresponding to the weight of each of the divided display periods, and obtaining a luminance distribution of the video signal for each of a plurality of display lines on the display panel. The number of the divided display periods in the unit display period is changed for each of a plurality of display lines in accordance with The driving method of the display panel. 7. The display panel driving method according to claim 6, wherein the luminance distribution is obtained based on a cumulative frequency for each luminance level in the video signal for a plurality of display lines. 8. A reset step of initializing all the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, The pixel cell is set to one of the non-light emitting cell and the light emitting cell only in the pixel data writing process in any one of the divided display periods. The method for driving a display panel according to claim 6. 9. A reset step of initializing all of the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, In the pixel data writing process in any one of the divided display periods, the pixel cell is set to one of the non-light emitting cell and the light emitting cell, and the one divided display is performed. At least one that exists after the period
7. The display panel driving method according to claim 6, wherein said pixel cell is set to said one state again in said pixel data writing process in said divided display period. 10. The method according to claim 6, wherein the number of the divided display periods is increased when a luminance level range of the luminance distribution in the video signal for a plurality of display lines is wide as compared with a narrow case. Driving method of display panel. 11. A method of driving a display panel in which a plurality of pixel cells are arranged in a matrix in accordance with a video signal, wherein a unit display period of the video signal is divided into a plurality of divided display periods. In each of the divided display periods, a pixel data writing step of setting each of the pixel cells to one of a light emitting cell and a non-light emitting cell according to pixel data corresponding to the video signal, and only the light emitting cell Performing a light emission maintaining process of emitting light for the number of times of light emission allocated in accordance with the weighting of each of the divided display periods. The number of the divided display periods in the unit display period is changed for each display line in response to the request. The driving method of the display panel. 12. The display panel driving method according to claim 11, wherein the luminance distribution is obtained based on a cumulative frequency for each luminance level in the video signal for a plurality of display lines. 13. A reset step of initializing all the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, The pixel cell is set to one of the non-light emitting cell and the light emitting cell only in the pixel data writing process in any one of the divided display periods. The method of driving a display panel according to claim 11. 14. A reset step of initializing all the pixel cells to one of the light emitting cells and the non-light emitting cells only in the divided display period at the head of the unit display period, In the pixel data writing process in any one of the divided display periods, the pixel cell is set to one of the non-light emitting cell and the light emitting cell, and the one divided display is performed. At least one that exists after the period
12. The display panel driving method according to claim 11, wherein said pixel cell is set to said one state again in said pixel data writing step in said divided display period. 15. The method according to claim 11, wherein the number of the divided display periods is increased when a luminance level range of the luminance distribution in the video signal for a plurality of display lines is wide as compared with a case where the luminance level range is narrow. Driving method of display panel.