WO2008062501A1

WO2008062501A1 - Plasma display panel driving method and plasma display

Info

Publication number: WO2008062501A1
Application number: PCT/JP2006/323110
Authority: WO
Inventors: Takashi Sasaki; Akihiro Takagi
Original assignee: Hitachi Plasma Display Limited
Priority date: 2006-11-20
Filing date: 2006-11-20
Publication date: 2008-05-29

Abstract

One field for displaying one screen of a plasma display panel is composed of a plurality of sub-fields. A scan operation for selecting a cell to be lit is performed for each display line in each of the sub-fields. An image is displayed in multi-level gradation by using sustained discharge to light the selected cell. For example, a gradation detecting circuit allocates the standard number of sustained discharge times allocated to other sub-fields to an unnecessary sub-field in order to continuously light cells in the same column as the cells on the display line on which the next scan operation is to be performed in the display line on which an unnecessary sub-field requiring no sustained discharge is present. Because of the continuous generation of address discharge in the cell in the same column, malfunction caused by an address discharge delay can be reduced and the sustained discharge can be normally generated. As a result, the quality of an image can be improved.

Description

Specification

TECHNICAL FIELD The present invention relates to a plasma display panel driving method and a plasma display device.

The present invention relates to a method for driving a plasma display panel and a plasma display device.

Background art

A plasma display panel (PDP) is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

In PDP, in order to display an image with multiple gradations, a field for displaying one screen is composed of a plurality of subfields. For example, the number of subfield discharges is sequentially set to 2 to the nth power (n is a positive integer). In each subfield, a multi-tone image is displayed by selectively lighting the cells in accordance with the luminance of the image. For example, in an image with high luminance (high gradation image), a subfield with a large number of discharges is selected In an image with low luminance (low gradation image), a subfield with a large number of discharges is not selected. The cell to be lit is selected by generating an address discharge. If the delay time (address discharge delay) from when a voltage is applied to the address electrode until force address discharge occurs is large, a malfunction may occur in which address discharge does not occur. A cell that does not generate an address discharge does not light up because a sustain discharge does not occur. For this reason, the pixel corresponding to the cell is not displayed, and the image quality deteriorates.

[0003] In order to reduce address discharge delay, a plasma display panel has been proposed in which a common electrode is provided for generating priming particles between a pair of sustain electrodes (a pair of sustain electrodes and scan electrodes). (For example, see Patent Document 1). Here, the priming particle is a charged particle for generating a discharge of free electrons or ions. In addition, in order to improve discharge characteristics, a plasma display is manufactured by forming a protective layer exposed in the discharge space of the PDP by forming a crystalline oxide-magnesium layer on the magnesium oxide layer. Panels have been proposed (see, for example, Patent Document 2).

[0004] In addition, there has been proposed a plasma display panel that detects the total amount of display data for each display line and adjusts the number of sustain discharges in the subfield according to the data amount (see, for example, Patent Document 3).

Patent Document 1: Japanese Patent Laid-Open No. 2001-185034

Patent Document 2: Japanese Patent Laid-Open No. 2006-245019

Patent Document 3: Japanese Patent Laid-Open No. 9-68945

Disclosure of the invention

Problems to be solved by the invention

[0005] Patent Document 1 has a more complicated structure (addition of a common electrode) than a general PDP. Patent Document 2 is a more complicated process (addition of a process for forming a crystalline magnesium oxide layer) than a general PDP. Further, as described above, in the display line of an image with low luminance, the upper subfield having a high number of discharges is not selected and is not lit. Thus, even if there is a subfield that does not contribute to discharge, no method has been proposed for utilizing this subfield.

[0006] An object of the present invention is to utilize a sub-field that does not contribute to discharge, thereby reducing luminance, reducing malfunction caused by address discharge delay of a display unit, and improving image quality.

Means for solving the problem

[0007] In the present invention, one field for displaying one screen of the plasma display panel is composed of a plurality of subfields. The display line is composed of pixels formed along the first electrode. In each subfield, a scanning operation for selecting a cell to be lit is performed by controlling the second and third electrodes for each display line. The selected cell is lit by the sustain discharge between the first and second electrodes, so that the image is displayed in multiple gradations. For example, the gray scale detection circuit detects whether or not there is a force in which an unnecessary subfield that does not require sustain discharge exists for each display line. Then, when there is an unnecessary subfield in the first display line, the gradation detection circuit detects whether or not the cell in the second display line is lit in the subfield of interest. Here, the first display line is continuously scanned. The display line in which the scan operation is performed first, and the second display line is the display line in which the scan operation is performed next to the first display line. Line. The target subfield is the subfield of the second display line corresponding to the unnecessary subfield of the first display line. When the cell of the second display line lights up in the target subfield, the sustain control circuit sets the preset standard number of times in the adjustment subfield which is at least one of the subfields of the first display line excluding the unnecessary subfield. The operation of the first and second drive circuits is controlled in order to generate a smaller number of sustain discharges. Further, the sustain control circuit controls the operations of the first and second drive circuits in order to generate the sustain discharge of the number of times reduced in the adjustment subfield in the unnecessary subfield.

The invention's effect

[0008] According to the present invention, the luminance is low! In the display unit, malfunction caused by address discharge delay can be reduced, and the image quality can be improved.

Brief Description of Drawings

FIG. 1 is an exploded perspective view showing a first embodiment of the present invention.

2 is an exploded perspective view showing details of a main part of the PDP shown in FIG.

FIG. 3 is an explanatory diagram showing a configuration example of a field for displaying an image of one screen.

4 is a waveform diagram showing an example of a discharge operation in the subfield shown in FIG.

FIG. 5 is a block diagram showing an outline of the circuit unit shown in FIG. 1.

6 is a flowchart showing the operation of the control unit shown in FIG.

7 is a circuit diagram showing details of the Y driver and the X driver shown in FIG. 5. FIG.

FIG. 8 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3.

FIG. 9 is an explanatory diagram when the flow shown in FIG. 6 is performed in the same order as the scanning operation is performed.

FIG. 10 is an explanatory diagram when the flow shown in FIG. 6 is performed in the reverse order of the scanning operation.

FIG. 11 shows details of the Y driver and the X driver in the second embodiment of the present invention. It is a road map.

12 is a circuit diagram showing an example of a scan driver circuit shown in FIG. 11.

FIG. 13 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3 in the second embodiment of the present invention.

FIG. 14 is an explanatory diagram showing another example when the flow shown in FIG. 6 is performed in the same order as the scanning operation is performed.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. A plasma display device (hereinafter also referred to as a PDP device) is a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), and an optical filter provided on the image display surface 12 side (light output side) of the PDP10. 20, PDP10 image display surface 12 is mounted on the front housing 30 side, PDP10 rear panel 40 is mounted on the back side 14 and base chassis 50, base chassis 50 is mounted on the rear housing 40 side, PDP10 Circuit unit 60 for driving the PDP 10 and a double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit part 60 is composed of a plurality of parts, it is indicated by a dashed box in the figure.

The PDP 10 includes a front substrate 16 (first substrate) that forms the image display surface 12 and a rear substrate 18 (second substrate) that faces the front substrate 16. A discharge space (cell) (not shown) is formed between the front substrate 16 and the rear substrate 18. The front substrate 16 and the back substrate 18 are formed of, for example, a glass substrate. The optical filter 20 is attached to a protective glass (not shown) attached to the opening 32 of the front housing 30.

FIG. 2 shows details of a main part of the PDP 10 shown in FIG. The front substrate 16 has X electrodes 16b (first electrode, sustain electrode) and Y electrodes 16c (first electrode and sustain electrode) formed in parallel and alternately on the glass substrate 16a (lower side in the figure) in order to generate discharge repeatedly. Second electrode, running electrode). The X electrode 16b and the Y electrode 16c are composed of a bus electrode BE (electrode line) extending in the horizontal direction in the figure and a transparent electrode TE connected to the bus electrode BE. The electrodes 16b and 16c are covered with a dielectric layer 16d, and the surface of the dielectric layer 16d is covered with a protective layer 16e such as MgO. [0013] The rear substrate 18 facing the front substrate 16 through the discharge space DS has address electrodes 18b (third electrodes) formed in parallel with each other on the glass base material 18a. The address electrode 18b is arranged in a direction orthogonal to the bus electrode BE. The address electrode 18b is covered with a dielectric layer 18c. On the dielectric layer 18c, partition walls (ribs) 18d are formed at positions corresponding to between the adjacent address electrodes 18b. The side wall of the cell is constituted by the partition wall 18d. Furthermore, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall 18d and on the dielectric layer 18c between the partition walls 18d adjacent to each other by being excited by ultraviolet rays. The phosphors 18e, 18f, and 18g are applied respectively.

[0014] One cell (one color pixel) of the PDP 10 is formed in a region including a pair of transparent electrodes TE in a region surrounded by a pair of adjacent partition walls 18d. That is, the cell is formed at the intersection of the electrodes 16b and 16c and the electrode 18b. As described above, the PDP 10 is configured by arranging cells in a matrix to display an image, and alternately arranging a plurality of types of cells that generate light of different colors. Note that one pixel PX shown in FIG. 5 described later is composed of three cells that generate red, blue, and green light. Although not specifically shown, a display line is constituted by cells formed along the electrodes 16b and 16c.

[0015] The PDP 10 is configured by bonding the front substrate 16 and the rear substrate 18 so that the protective layer 16e and the partition wall 18d are in contact with each other and enclosing a discharge gas such as Ne or Xe. The bus electrode BE is connected to the X driver XDRV and the Y driver YDRV shown in FIG. The address electrode 18b is connected to the address driver ADRV shown in FIG.

FIG. 3 shows a configuration example of the field FLD for displaying an image of one screen. One Fino Red FLD has a length of 1Z60 seconds (about 16.7 ms), and is composed of, for example, 8 subfields SF (SF1-SF8). Each subfield SF includes a reset period RST, an address period ADR, a sustain period SUS, and an erase period ERS. Note that the erasing period ERS is defined as being included in the sustaining period SUS because it is a period for generating a discharge for erasing the wall charges of only the lit cells. Here, the wall charges are, for example, positive charges and negative charges accumulated on the MgO layer 16e shown in FIG. 2 in each cell. [0016] Sustain period The length of SUS differs depending on the subfield SF, and depends on the number of discharges (luminance) of the cell. For this reason, it is possible to display an image with multiple gradations by changing the combination of the subfields SF to be lit. In this example, the standard number of sustain discharges (standard number of discharge cycles) preset in subfield SF1-8 on the display line where there is no unnecessary subfield, which will be described later, is 4, 8, 16, 32, respectively. 64, 128, 256, 512. For this reason, the upper subfields SF8 and SF7 are used for high luminance (high gradation) images, and the upper subfields SF8 and SF7 are not used for low luminance (low gradation) images. Here, the number of discharge cycles indicates the number of sustain pulses applied to the X electrode 16b (or Y electrode 16c). As shown in Figure 4 below, the cell discharges twice during one discharge cycle CYC (white star in the figure).

FIG. 4 shows an example of the discharge operation of subfield SF shown in FIG. A white or black star in the figure indicates the occurrence of a discharge. The black star indicates the address discharge that occurred during the address period ADR! /

First, in the reset period RST, a negative write voltage is applied to the sustain electrode X (X electrode 16b), and a positive write voltage (write blunt wave) that gradually increases is applied to the scan electrode Y1—Yi (hereinafter, scan electrode Y (Also referred to as Y electrode 16c)) (FIG. 4 (a)). As a result, positive and negative wall charges are accumulated in the sustain electrode X and the scan electrode Y, respectively, while suppressing the light emission of the cell. Next, a positive adjustment voltage is applied to the sustain electrode X, and a negative adjustment voltage (adjusted blunt wave) is applied to the scan electrode Y (FIG. 4 (b)). This reduces the amount of wall charges and makes the wall charges of all cells equal. For example, the positive adjustment voltage is a voltage lower than the voltage VsZ2, and the negative adjustment voltage is a voltage higher than the voltage VsZ2.

[0018] In the address period ADR, a positive scan voltage is applied to the sustain electrode X, a negative scan pulse is applied to the scan electrode Y, and a positive address pulse (voltage Vsa) force is applied to the address electrode Al corresponding to the lighted cell. (18b) (Fig. 4 (c, d)). The address pulses shown in the waveform of the address electrode Al (18b) are sequentially applied to select the cells to be lit for each display line. That is, a scanning operation for selecting a cell to be lit is performed for each display line.

For example, the first address pulse shown in the waveform of the address electrode Al (18b) Applied to select the cell of the display line controlled by the electrode Yl (Fig. 4 (c)). The second address pulse shown in the waveform of the address electrode Al (18b) is applied to select the cell of the display line controlled by the scan electrode Yi (Fig. 4 (d)).

A cell selected by the address pulse temporarily generates an address discharge. Time td (address discharge delay) is the time from when the address pulse (voltage Vsa) is applied to the address electrode Al (18b) until the address discharge occurs. In the present invention, the address discharge of the address period ADR should not be included in the discharge cycle CYC!

Due to the address discharge, wall charges are accumulated in the sustain electrode X and the scan electrode Y corresponding to the selected cell. If the address discharge does not occur in the selected cell having a large address discharge delay, the wall charge is not accumulated in the sustain electrode X and the scan electrode Y corresponding to the selected cell. In this case, a cell that does not generate an address discharge does not light because a sustain discharge does not occur. For this reason, the pixel corresponding to the cell is not displayed, and the image quality deteriorates. As will be described later, in the present invention, by using unnecessary subfields, it is possible to reduce malfunctions in which address discharge does not occur by reducing address discharge delay.

[0021] In the sustain period SUS, negative and positive sustain pulse force are applied to the sustaining electrode X and the scanning electrode Y, respectively (Fig. 4 (e, f)). As a result, the discharge state of the lit cell is maintained. Sustain pulse forces having different polarities are repeatedly applied to the sustain electrode X and the scan electrode Y, so that the cells lit in the sustain period SUS are repeatedly discharged. As explained in Fig. 3, two discharges are performed during one discharge cycle CYC. For example, subfield SF4 is composed of 32 discharge cycles CYC, and 64 discharges are performed. As will be described in detail with reference to FIG. 8, in the discharge inhibition period DIS, the scan electrode Y is maintained at the high voltage VSZ2, and therefore no discharge occurs.

[0022] In the erase period ERS, a negative pre-erase pulse and a positive high-voltage pre-erase pulse force X are applied to the sustain electrode X and the scan electrode Y, respectively, and discharge is generated (FIG. 4 (g)). As a result, wall charges are accumulated in the sustain electrode X and the scan electrode Y. At this time, since a voltage higher than the voltage VsZ2 is applied to the scan electrode Y, the amount of accumulated wall charges is relatively large. Next, the positive erase pulse and the negative erase pulse force lower than the voltage VsZ2 sustain electrode X and It is applied to each scan electrode Y (Fig. 4 (h)). As a result, discharge occurs and the amount of wall charges decreases. Finally, in order to shift to the next reset period RST, a negative voltage (blunt wave) that gradually falls is applied to the sustain electrode X, and a positive pulse is applied to the scan electrode （(Fig. 4). (i)). In the present invention, the discharge in the erase period ERS is not included in the discharge cycle. This completes one subfield period SF. In the example shown in the figure, the number of discharge cycles is “3” (sustain period SUS 6 discharges), which is the same as the number of pulses of the scan electrode Y.

[0023] It should be noted that the Y driver YDRV and the X driver XDRV shown in FIGS. 7 and 11 to be described later have predetermined voltages (eg, positive adjustment voltage, negative The description of the circuit for applying the adjustment voltage to the sustain electrode X and the scan electrode Y is omitted.

FIG. 5 shows an outline of the circuit unit 60 shown in FIG. The circuit unit 60 includes an X driver XDRV (first drive circuit) that applies a common pulse to the X electrode 16b, a Y driver YDRV (second drive circuit) that selectively applies a pulse to the Y electrode 16c, and an address electrode. It has an address driver ADRV (third drive circuit) that selectively applies pulses to 18b, a control unit CNT that controls the operation of the drivers XDRV, YDRV, and AD RV, and a power supply unit PWR. Drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10.

The control unit CNT includes a gradation detection circuit 62 and a sustain control circuit 64. Image data RO-7, GO-7, and BO-7 are 8-bit data for displaying red, green, and blue, respectively. Input sequentially. In this example, 256 different luminances (256 gradations) are represented according to the bit values of the image data RO-7, GO-7, BO-7. Here, a bit with a small number (low order bit) has a high weight for a bit with a small number (high order bit) with a small weight.

The gradation detection circuit 62 obtains a subfield SF to be used for displaying an image for each pixel based on the image data RO-7, GO-7, BO-7. In other words, the subfield SF to be lit for each pixel PX is obtained by calculation. By this calculation, a display line including a high luminance (high gradation) image and a display line not including a high luminance image are detected. Here, as described above, the display line is configured by the pixels PX arranged along the electrodes 16b and 16c. Here, one image PX generates red, blue and green light as explained in Figure 2 It consists of three cells. Each pixel PX may be composed of three or more cells.

[0026] For example, a display line including a high-luminance image is a display line having pixels that display an image by turning on the subfield SF8 (or SF7-8). In a display line that does not include a high-luminance image, subfield SF8 (or SF7-8) is an unnecessary subfield that does not require sustain discharge (lighting) in the sustain period SUS. In other words, all the red (R), green (G), and blue (B) cells are not lit in the unnecessary subfield.

In addition, the gradation detection circuit 62 is a display line (second display line) on which a scanning operation is performed next to this display line (first display line) in the display line where the unnecessary subfield exists. Is detected in the target subfield corresponding to this unnecessary subfield. Here, the target subfield is the subfield SF of the second display line in which the same standard number as the standard number of times set in the unnecessary subfield of the first display line is set. That is, the number of the unnecessary subfield (for example, SF8) and the target subfield (for example, SF8) are the same. Hereinafter, in a pair of display lines in which the scanning operation is continuously performed, the display line in which the scanning operation is performed first is also referred to as the first display line, and the display line in which the scanning operation is performed next to the first display line. Is also called the second display line.

[0028] Then, when the cell of the second display line lights up in the target subfield, the gradation detection circuit 62 uses at least one of the subfields SF1-8 except the unnecessary subfield of the first display line. Select an adjustment subfield. Here, the adjustment subfield is a distribution-source subfield when distributing the number of sustain discharges to the unnecessary subfields in order to generate a sustain discharge in the unnecessary subfields. An example of the adjustment subfield selection method will be described later with reference to FIG. The gradation detection circuit 62 outputs information indicating the presence / absence of unnecessary subfields and adjustment subfields to the sustain control circuit 64 for each display line.

[0029] The sustain control circuit 64 has no adjustment subfield, and in the display line, in order to generate a preset standard number of sustain discharges in each subfield SF1-8. Outputs control signals YCNT and XCNT to YDRV and XDRV, and driver Outputs control signal ACNT to ADRV. At this time, the sustain control circuit 64 outputs control signals YCNT and XCNT to display a 256-gradation image corresponding to the 8-bit image data RO-7, GO-7, and BO-7.

Here, the control signal YCNT includes switch control signals SW1, SW2, SW3, SW4, SW5n, SW5m, SW6n, and SW6m shown in FIG. 8 to be described later. The control signal XCNT includes switch control signals SW7, SW8, SW9, and SW10 shown in FIG. The control signal ACNT is a timing signal for generating an address pulse.

On the other hand, the sustain control circuit 64 generates a standard number of sustain discharges set in the adjustment subfield in the display line in which the adjustment subfield exists, in order to separately generate the adjustment subfield and the unnecessary subfield. Controls the operation of XDRV and ADR V. For example, the sustain control circuit 64 outputs control signals YCNT and XCNT to generate the standard number of times (64 times) of sustain discharge set in the subfield SF5 16 times in the subfield SF3 and 48 times in the subfield SF5. (Unnecessary subfield = SF3, adjustment subfield = SF5).

[0031] Note that the display line in which the adjustment subfield exists is an unnecessary subfield in the first display line, and the first display line that satisfies the! / Condition when the cell in the second display line lights in the target subfield. 1 display line.

The scan operation is performed later by continuously generating the address discharge of the cells controlled by the common address electrode 18b on the pair of display lines on which the scan operation is continuously performed. Priming particles existing in the discharge space of the display line can be increased. Here, the priming particles are charged particles for generating a discharge of free electrons, ions, etc., and are most frequently generated immediately after the discharge, and gradually decrease.

[0032] Since the priming particles diffuse to the periphery, in the case of the cell structure shown in Fig. 2 described above, the priming particles diffuse in the direction in which the partition walls (ribs) 18d extend, that is, in the direction perpendicular to the display lines. As a result, a part of the priming particles generated by the address discharge moves to the discharge space DS of the display line where the scanning operation is performed later, and the address discharge delay in the display line can be reduced. Therefore, malfunctions due to address discharge delay can be reduced, sustain discharge can be normally generated in the selected cell, and image quality can be improved. [0033] The power supply unit PWR generates power supply voltages Vsc, Vs / 2, one VsZ2, and Vsa to be supplied to the drivers YDRV, XDRV, and ADRV. Y driver YDRV has a scan driver circuit SD for each Y electrode 16c. As a result, a desired number of sustain pulses can be selectively applied to each Y electrode 16c.

FIG. 6 shows the operation of the control unit CNT shown in FIG. FIG. 6 shows only control for setting the number of sustain discharges in subfield SF1-8, and does not show control related to address period ADR and sustain period SUS. The number of sustain discharges in subfield SF 1-8 is set in advance to, for example, the standard number shown in FIG. 3 described above before step S10, and is reset by executing the flow in FIG. The The flow in Fig. 6 may be realized by controlling the hardware, which may be realized only by hardware, by software.

[0034] First, in step S10, the gradation detection circuit 62 outputs image data R0-7 for at least two display lines in which the scanning operation is successively performed among the image data received by the control unit CNT. , GO-7, BO-7 are received. Note that the control unit CNT shown in FIG. 5 continuously receives image data of a plurality of display lines and a plurality of screens. Therefore, the gradation detection circuit 62 performs the flow of FIG. 6 for each display line in a pair of display lines (first and second display lines) on which the scanning operation is continuously performed.

[0035] In step S12, the gradation detection circuit 62, based on the received image data of the display lines (first and second display lines), the subfield SF of each display line that is lit to display an image. For each pixel PX. As described above, the upper subfields SF8 and SF7 are used in the pixel PX that displays an image with high luminance. That is, the gradation detection circuit 62 detects whether or not there is an unnecessary subfield SF that does not require sustain discharge for each display line. Here, the unnecessary subfield SF is a subfield in which the sustain discharge is detected to be unnecessary in all the cells (red, blue and green) of one pixel PX.

In step S14, the gradation detection circuit 62 determines whether or not an unnecessary subfield that is not lit to display an image exists in the first display line. If there are no unnecessary subfields in the first display line, the processing for the first display line ends. . That is, the gradation detection circuit 62 does not change the number of sustain discharges in the subfield SF1-8 nor the preset standard number power. This operation is, for example, an operation for displaying a display line L2 in FIG. 9 to be described later.

[0037] On the other hand, if there is an unnecessary subfield in the first display line, in step S20, the grayscale detection circuit 62 detects the second display line in the target subfield that is a subfield corresponding to the unnecessary subfield. It is determined whether or not the cell is lit. If the cell on the second display line does not light in the subfield of interest, the process for the first display line ends.

If it is determined in step S20 that the cell of the second display line is lit in the target subfield, the process proceeds to step S22. In step S22, an adjustment subfield that is at least one of the subfields SF1-8 except the unnecessary subfield of the first display line is selected.

[0038] In step S24, the gradation detection circuit 62 sets the standard number of sustain discharges set in the adjustment subfield separately for the adjustment subfield and the unnecessary subfield. In other words, in the adjustment subfield, the number of sustain discharges less than the standard number is set, and in the unnecessary subfield, the number of sustain discharges reduced in the adjustment subfield is set. Thereby, the PDP 10 can light the unnecessary subfield without changing the luminance of the display image. The operation in step S24 is, for example, an operation for displaying a display line L1 in FIG.

Then, sustain control circuit 64 uses subfield SF1-8 to control the operation of drivers XDRV and YDRV in order to generate the sustain discharge for the number of times set by the above-described flow. The above-described flow may be performed for each display line in the same order as the order of scanning operations. Specifically, the above-described flow is performed in the order of display lines L1, L2, L3, and L4 shown in FIG. 9 described later. Further, it may be performed for each display line in the reverse order of the scan operation. Specifically, the above-described flow is performed in the order of display lines L4, L3, L2, and L1 shown in FIG. Note that the display line L5 shown in FIGS. 9 and 10 does not have the above-described flow because there is no display line on which scanning operation is performed last, that is, the second display line. FIG. 7 shows details of the Y driver YDRV and the X driver XDRV shown in FIG. The Y driver YDRV has a driver circuit DRV (Y) and a scan driver circuit SD. The X driver XDRV has a driver circuit DRV (X). The switches SW1, SW2, SW3, SW4, SW6 (SW6n, SW6m), SW7, SW8, SW9, SWIO shown in the figure are composed of, for example, nMOS transistors (MOSFETs). Each nMOS transistor has a parasitic diode that connects between the source and the drain, as shown in the figure. Further, the switch SW5 (SW5n, SW5m) is configured by, for example, an IGBT (Insulated Gate Bipolar Transistor). An IGBT is a neuropolar transistor that incorporates a MOSFET in the gate. Unlike an nMOS transistor, an IGBT does not have a parasitic diode between the source and drain.

The driver circuit DRV (Y) has a coin La, a switch SW1, SW2, SW3, SW4 and a diode. Coil La and switch SW1–4 operate as a resonance circuit to generate a resonance pulse on the Y electrode (Yn, Ym, etc.). The resonant pulse is a signal common to all Y electrodes. Switches SW1–4 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received.

[0042] The drain of the switch SW1 and the source of the switch SW3 are connected to the ground line G1. The source of the switch SW1 is connected to the node ND1, which is one end of the coil La, via a forward-connected diode. The drain of switch SW3 is connected to node ND1 through a diode connected in the reverse direction. The node ND1 is connected to the power supply Vs / 2 and one Vs / 2 through diodes connected in the reverse direction. In the switch SW2, the drain is connected to the power source VsZ2, and the source is connected to the node ND2, which is the other end of the coil La. Switch SW4 has its source connected to the power supply—Vs / 2 and its drain connected to node ND2. Node ND2 is connected to each scan driver circuit SD

[0043] Each scan driver circuit SD has a switch SW5 (SW5n, SW5m, etc.) and a switch SW6 (SW6n, SW6m, etc.) arranged in series between the power supply Vsc and the node ND2. In the switch SW5, the drain is connected to the power supply Vsc via a diode connected in the forward direction, and the source is connected to the Y electrode (Yn, Ym, etc.). The drain of switch SW5 is Connected to node ND2 through capacitor Ca. Switch SW6 has a source connected to node ND2 and a drain connected to the Y electrode.

[0044] The driver circuit DRV (X) of the X driver XDRV has the same circuit configuration as the driver circuit DRV (Y). That is, the driver circuit DRV (X) has a coil Lb, switches SW7, SW8, SW9, SW10 and a diode. The coil Lb and switch SW7-10 operate as a resonance circuit for generating a resonance pulse on the X electrode (Xn, Xm, etc.). Switches SW7-10 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received. Capacitor Cp indicates the capacitance of PDP10.

FIG. 8 shows details of operations in the address period ADR and the sustain period SUS shown in FIG. In the figure, a signal for controlling on / off of the switch SW1-10 is referred to as a switch control signal SW1-10. The switch SW1-10 is turned on during the high logic level of the switch control signal SW1-10, and is turned off during the low logic level of the switch control signal SW1-10. The star in the figure indicates the occurrence of discharge.

In the address period ADR, the switches SW4 and SW8 are always turned on (FIGS. 8 (a, b)). Therefore, the node ND2 shown in Fig. 7 is set to a voltage of 1 Vs / 2. X electrodes Xn and Xm are set to voltage VsZ2 (Fig. 8 (c, d)). In the address period ADR, the switches SW5n and SW5m are turned on and the switches SW6n and SW6m are turned off during the period when the selection operation of the pixel PX is not performed (FIG. 8 (e)). For this reason, the Y electrodes Yn and Ym are set to the voltage Vsc (Fig. 8 (f, g)). When the pixel PX is selected for lighting, the corresponding switch SW5n (or SW5m) is turned off and the corresponding switch SW6n (or SW6m) is turned on in synchronization with the driving of the address electrode A1. As a result, the Y electrode Yn (or Ym) is temporarily set to the voltage—VsZ2 (FIG. 8 (h, i)). Then, the scanning operation force for selecting the pixel PX to be lit is performed for each display line.

[0047] When the address period ADR is switched to the sustain period SUS, the voltages of the X electrodes Xn and Xm are initialized to the same voltage Vs / 2 by turning on the switch SW10 (Fig. 8 (j, k) ). The voltages of the Y electrodes Yn and Ym are initialized to 1 VsZ 2 by turning on the switches SW6n and SW6m (Fig. 8 (1, m)). Switches SW5n and SW5m are in the sustain period SUS Always be off.

[0048] After that, when switch SW1 is turned on and switch SW4 is turned off, ground line G1 is connected to capacitor Cp via switch SW1, coil La, switch SW6n, SW6m, and Y electrodes Yn and Ym. The The voltages of the Y electrodes Yn and Ym rise due to the LC resonance effect of the coil La and the capacitor Cp. Next, when the switch SW2 is turned on, the voltage of the Y electrodes Yn and Υm is clamped to the voltage VsZ2 (FIG. 8 (n, o)).

Next, when the switch SW3 is turned on, the capacitor Cp is connected to the ground line G1 via the Y electrodes Yn and Ym, the switches SW6n and SW6m, the coil La, and the switch SW3. The voltage of the Y electrodes Yn and Ym drops due to the LC resonance effect of the coil La and the capacitor Cp. Next, when the switch SW4 is turned on, the voltages of the Y electrodes Yn and Ym are clamped to the voltage VsZ2 (FIG. 8 (p, q)). In this way, the sustain pulses are applied to the Y electrodes Yn and Ym by sequentially turning on the switches SW1-4. Similarly to the sustain pulses of the Y electrodes Yn and Ym, the sustain pulses of the X electrodes Xn and Xm are generated by sequentially turning on the switches SW7-10.

[0050] In the display line (for example, Ym) in which the adjustment subfield is selected by the gradation detection circuit 62 shown in FIG. 5, the adjustment subfield selects the number of sustain pulses (discharge cycles) in the adjustment subfield. It is set to be smaller than the display line that is not set (for example, Yn). In other words, in the display line Ym, the discharge prohibition period DIS for prohibiting discharge is set during the sustain period SUS. The discharge inhibition period DIS is generated by clamping the Y electrode Ym to the voltage VsZ2 and then turning off the switch SW6m (Fig. 8 (r)). By clamping the Y electrode Ym to the voltage VsZ2, it is possible to prevent current from flowing to the capacitor Cp via the parasitic diode shown in Fig. 7 after the switch SW6m is turned off. As a result, the Y electrode Ym enters a high impedance state, and maintains the state (voltage) immediately before the switch SW6m is turned off.

[0051] When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state and maintains the state (voltage) immediately before turning off, which is not related to the operation of the switch SW1-4. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage. That is, the pixel PX of the corresponding display line is not lit during the discharge inhibition period DIS. The discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW3 being turned on. In the example shown in Fig. 8, the off period of switch SW6m is set to the same length as one discharge cycle. For this reason, the number of discharge cycles of the display line Ym is set to be smaller by one discharge cycle than the display line Yn. In this embodiment, the discharge inhibition period DIS is set at the end of the sustain period SUS. However, the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the DIS during the discharge inhibition period, it is possible to prevent false contours and improve the display image quality.

Thus, in the present invention, the switch SW6 (SW6n, SW6m) of the scan driver circuit SD used for the address period ADR is turned off during the sustain period SUS, so that the resonance pulse applied to the Y electrode is reduced. The number (number of discharge cycles) can be easily adjusted for each display line. In other words, even when the resonance pulse force common to all Y electrodes is generated by the driver circuit DRV (Y), the number of discharge cycles in the sustain period SUS can be adjusted independently only by controlling the switch SW6. . Furthermore, since the number of discharge cycles can be adjusted simply by controlling the on / off state of the switch SW6, the logic for generating the discharge inhibition period DIS in the sustain control circuit 64 can be easily configured.

FIG. 9 shows a case where the flow shown in FIG. 6 is performed in the same order as the order of the scanning operation. In this example, the scanning operation is performed in the order of the display lines Ll, L2, L3, L4, and L5, and the flow shown in FIG. 6 is also performed in the order of the display lines Ll, L2, L3, and L4. Note that the reset processing for the number of sustain discharges for the display line L5 (the flow shown in FIG. 6) is not performed because there is no display line for which the scan operation is performed last, that is, the second display line.

In order to simplify the description, a PDP having pixels in 5 rows (display lines L1-5) × 8 columns (column C1-8) will be described. Also, one pixel shown in the figure is composed of, for example, three cells of red (R), green (G), and blue (B). Therefore, in the unnecessary subfield (for example, subfield SF1 of display line L1 in state ST10), all the cells of red (R), green (G), and blue (B) are not lit!

[0055] Black portions and shaded portions in the figure indicate pixels that are lit. The shaded part is This indicates the pixels that are lit when the standard number of adjustment subfields is assigned to the adjustment subfield and the unnecessary subfield. The numbers in parentheses in the figure indicate the standard number of sustain discharges for each subfield SF, and the numbers above the arrows are reset to the subfields of the display lines indicated by the arrows. Indicates the number of sustain discharges.

[0056] Further, the triangle in the figure shows the display line where the unnecessary subfield detected in step S14 shown in FIG. 6 exists, and the circle shows the adjustment selected in step S22 shown in FIG. The display line in which a subfield exists is shown. Hereinafter, the unnecessary subfield, the adjustment subfield, and the target subfield may be referred to with the corresponding subfield code SF1-8.

[0057] State STIOi corresponds to the state in which the process up to steps S10, S12, S14, S20, and S22 shown in FIG. That is, the gradation detection circuit 62 performs the processing of Steps S 10-22 on the display line L1 with the display line L1 as the first display line and the display line L2 as the second display line.

The grayscale detection circuit 62 detects that the unnecessary subfield SF1 exists in the display line L1 and that the pixel of the display line L2 is lit in the target subfield SF1 (step S10-20 shown in FIG. 6). ). Then, the gradation detection circuit 62 selects the adjustment subfield SF3 from the subfield SF2-8 of the display line L1 (step S22 shown in FIG. 6).

[0058] The adjustment subfield is a subfield in which the number of cells controlled by the address electrode 18b (third electrode) common to the cell to be lit in the target subfield SF1 of the display line L2 is lit up most. In this example, the gradation detection circuit 62 has the subfield SF3 of the display line L1 in which all pixels in the same column (columns Cl, C3, C5, and C8) as the pixels that light up in the target subfield SF1 of the display line L2 are lit. As the adjustment subfield SF3.

[0059] State ST20 is step S24 shown in FIG. 6 relating to display line L1, step S10-14 of display line L2, step S10-20 of display line L3, step SI 0-14 of display line L4, S20-22 This corresponds to the state in which the processes up to are completed. That is, the gradation detection circuit 62 divides the standard number of sustain discharges (16 times) of the adjustment subfield SF3 of the display line L1 (first display line) into the adjustment subfield SF3 and the unnecessary subfield SF1. Reset (step S24 shown in FIG. 6). In other words, the gradation detection circuit 62 sets the number of sustain discharges in the adjustment subfield SF3 of the display line L1 to 12 times, which is 4 times less than the standard number (16 times). Then, the gradation detection circuit 62 sets the number of sustain discharges of the unnecessary subfield SF1 of the display line L1 to 4 times that is the number of times reduced in the adjustment subfield, and ends the processing relating to the display line L1.

[0060] Next, the gradation detection circuit 62 sets the display line L2 as the first display line and the display line L3 as the second display line, and proceeds to processing related to the display line L2. The grayscale detection circuit 62 ends the process for the display line L2 because there is no unnecessary subfield in the display line L2 (first display line). Therefore, the number of sustain discharges in the subfield SF1-8 of the display line L2 is the standard number shown in FIG.

[0061] Then, the gradation detection circuit 62 sets the display line L3 as the first display line and the display line L4 as the second display line, and proceeds to processing related to the display line L3. In the gradation detection circuit 62, since the subfield SF3 of interest is not lit on the display line L4 (second display line) (the unnecessary subfield of the display line L3-4 is the same), the display line L3 (first display The processing for (line) ends. Therefore, the number of sustain discharges in subfield SF1-8 of display line L3 is not changed by the standard number of times shown in FIG.

[0062] Next, the gradation detection circuit 62 sets the display line L4 as the first display line and the display line L5 as the second display line, and proceeds to processing related to the display line L4. The gradation detection circuit 62 repeats the same processing as that for the display line L1 in the state ST10, and selects the adjustment subfield SF2 from the subfields SF1-2 and SF4-8 of the display line L4. In this case, for example, the gradation detection circuit 62 is connected to the display line L4 in which the pixels in the same column (columns Cl, C4, C5, C7) as the pixels that are lit in the target subfield SF3 of the display line L5 are lit up most. Select subfield SF2 (pixels in columns Cl, C5 and C7 are lit) as the adjustment subfield.

[0063] State ST30 corresponds to the state in which the process of step S24 shown in Fig. 6 has been completed on display line L4. The gradation detection circuit 62 performs the same processing as the display line L1 in the state ST20. That is, the gradation detection circuit 62 sets the number of sustain discharges in the adjustment subfield SF2 of the display line L4 to 4 times, which is 4 times less than the standard number (8 times). Then, the gradation detection circuit 62 performs sustain discharge of the unnecessary subfield SF3 of the display line L4. Set the number of times to 4 times, which is the number of times reduced in the adjustment subfield, and end the processing for display line L4. Thereby, the resetting process of the number of sustain discharges in each subfield SF of the display line L14 is completed.

[0064] With the above-described processing, in a pair of display lines in which a scanning operation is continuously performed, pixels in the same column as the pixels of the second display line can be lit first on the first display line. For example, in the subfield SF1 of the ideographic lines L1 and L2, and the subfield SF3 of the display lines L4 and L5, at least one of the pixels in the same column as the pixels of the second display line is lit first on the first display line. To do. Therefore, when the scan operation is performed, at least one of the cells in the same column as the cells of the second display line is first subjected to the address discharge on the first display line.

As a result, the number of priming particles existing in the discharge space is increased in the cells in the second display line in the same column as the cells in which the address discharge has occurred in the first display line (cells controlled by the common address electrode 18b). be able to. This can reduce the address discharge delay in the second display line of the cells that are continuously lit in the first and second display lines. Therefore, malfunctions due to address discharge delay can be reduced, and sustain discharge can be normally generated in the selected cell, thereby improving the image quality.

[0066] Further, since sustain discharge is generated by dividing it into a plurality of subfields SF (adjustment subfield and unnecessary subfield), the address discharge does not occur, and the image quality deteriorates when the number of sustain discharges is insufficient. The amount can be reduced. For example, in the subfield SF2 of the display line L4, when the address discharge does not occur due to the delay of the address discharge, when the present invention is not applied, the number of sustain discharges is insufficient eight times, and the luminance is deteriorated accordingly. Occurs.

[0067] On the other hand, when the present invention is applied, if the address discharge does not occur due to the delay of the address discharge in the subfield SF2 of the display line L4, the present invention is applied to the number of sustain discharge shortages. This can be reduced to 4 times, which is less than when not (8 times), and the amount of luminance degradation can be suppressed. Therefore, it is possible to reduce the amount of image quality degradation caused by address discharge malfunction.

Fig. 10 shows the case where the flow shown in Fig. 6 is executed in the reverse order of the scan operation. Is shown. In this example, the scanning operation is performed in the order of the display lines L1, L2, L3, L4, and L5, and the flow shown in FIG. 6 is performed in the order of the display lines L4, L3, L2, and L1. In this case as well, the reset process for the number of sustain discharges related to the display line L5 (the flow shown in FIG. 6) is performed because there is no display line on which scanning operation is performed last, that is, the second display line. Not. The same elements as those described in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

State ST10A corresponds to a state in which the processes up to steps S10, S12, S14, S20, and S22 shown in FIG. 6 have been completed on display line L4. That is, the gradation detection circuit 62 performs the processing of Steps S10-22 regarding the display line L4 with the display line L4 as the first display line and the display line L5 as the second display line.

The gradation detection circuit 62 detects that the unnecessary subfield SF3 exists in the display line L4 and that the pixel of the display line L5 lights up in the target subfield SF3. Then, the gradation detection circuit 62 selects the adjustment subfield SF2 from the subfields SF1-2 and SF4-8 of the display line L4.

[0069] State ST20A corresponds to a state in which the processes up to step S24 shown in FIG. 6 relating to display line L4 and steps S10-14 and S20-22 of display line L3 are completed. That is, the gradation detection circuit 62 determines the standard number of sustain discharges (8 times) for the adjustment subfield SF2 of the display line L4 (first display line), the adjustment subfield SF2 (4 times), and the unnecessary subfield SF3 ( (4 times) and reset.

Next, the gradation detection circuit 62 sets the display line L3 as the first display line and the display line L4 as the second display line, and proceeds to processing relating to the display line L3. The grayscale detection circuit 62 selects the adjustment subfield SF4 from the subfields SF1-2 and SF4-8 of the display line L3 in order to illuminate the target subfield SF3 force display line L4 (second display line). Here, by the processing related to the display line L4 in the state ST20A, in the unnecessary subfield SF3 of the display line L4, the cells of the columns Cl, C5, and C7 are assigned to generate the sustain discharge four times.

[0071] When the unnecessary subfields of the first and second display lines are the same as each other, the second display line is unnecessary by performing the flow shown in FIG. 6 in the reverse order of the scan operation. Pixels to be lit in the subfield can be assigned. Therefore, it is possible to reduce the address discharge delay in the second display line of the cells that are continuously lit in the first and second display lines. Therefore, malfunctions due to address discharge delay can be reduced, sustain discharge can be normally generated in the selected cell, and image quality can be improved.

State ST30A corresponds to a state in which the processes up to step S24 shown in FIG. 6 relating to display line L3 and steps S10-14 and S20-22 of display line L2 are completed. The gradation detection circuit 62 determines the standard number of sustain discharges (32 times) of the adjustment subfield SF4 for the display line L3 (first display line), the adjustment subfield SF4 (16 times), and the unnecessary subfield SF3 (16 times). ) And set again. Next, the processing related to the display line L2 is performed with the display line L2 as the first display line and the display line L3 as the second display line. Finally, the processing related to the display line L1 is performed with the display line L1 as the first display line and the display line L2 as the second display line.

State ST40 corresponds to a state in which the processing up to step S24 shown in FIG. 6 relating to display line L1 is completed. Thereby, the resetting process of the number of sustain discharges in each subfield SF of the display line L1-4 is completed. In this case as well, similar to the operation shown in FIG. 9, malfunctions due to address discharge delay can be reduced, sustain discharge can be normally generated in the selected cell, and image quality can be improved. In addition, it is possible to reduce the amount of image quality degradation caused by address discharge malfunction. Furthermore, even when the unnecessary subfields of the first and second display lines are the same, the address discharge can be continuously generated in the cells in the same column, so that the above-described effect can be obtained.

As described above, in the first embodiment, when unnecessary subfields exist, cells in the same column are displayed on the pair of display lines in which the scanning operation is continuously performed using the unnecessary subfields. Subfields that are continuously lit can be configured. As a result, the address discharge can be generated first in the cell in the same column as the cell of the display line to be scanned later. As a result, it is possible to increase the number of priming particles existing in cells in the same column (discharge space) as the cells in which the address discharge has been generated earlier, and to delay the address discharge over the display line where the scanning operation is performed later. Caused malfunctions can be reduced.

[0075] Therefore, the sustain discharge can be normally generated in the selected cell. , Image quality can be improved. In addition, since sustain discharge is generated separately for the adjustment subfield and the unnecessary subfield, the amount of degradation in image quality due to malfunction of address discharge can be dispersed.

Even when the resonance pulse force common to all Y electrodes is generated by the driver circuit DRV (Y), the number of discharge cycles in the sustain period SUS can be adjusted independently for each display line only by controlling the switch SW6. Therefore, the control for adjusting the number of discharge cycles can be simplified. In other words, in the sustain control circuit 64, the logic for generating the discharge inhibition period DIS can be easily configured.

[0076] FIG. 11 shows details of the Y dry YDRV and the X driver XDR V in the second embodiment of the present invention. In this embodiment, the scan driver circuit SD of the Y driver YDRV is different from the first embodiment. The configuration excluding the scan driver circuit SD is the same as that of the first embodiment (FIGS. 1 to 6). The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the switch SW6 (SW6n, SW6m) of the scan driver circuit SD is configured by an IGBT instead of an nMOS transistor. Unlike an nMOS transistor, an IGBT does not have a parasitic diode between the source and drain. For example, when the node ND2 rises to VsZ2 while the switch SW6m is off, the voltage at the Y electrode Ym changes. do not do.

FIG. 12 shows an example of the scan driver circuit SD shown in FIG. The drain (D) and source (S) of switch SW 5n are connected to the collector (C) and emitter (E) of IGBT 5nl, respectively. In other words, the drain (D) of the switch SW5n is the collector (C) of the IGBT 5nl, and the source (S) of the switch SW5n is the emitter (E) of the IGBT 5nl.

[0079] The switch SW6n includes IGBT6nl, IGBT6n2, and diodes D6nl, D6n2. The collector (C) of the IGBT 6nl is connected to the drain (D) terminal of the switch SW6n, and the emitter (E) of the IGBT 6nl is connected to the emitter (E) of the IGBT 6n2. The collector (C) of IGBT6n2 is connected to the source (S) terminal of switch SW6n. The diode and force sword of diode D6nl are connected to the collector (C) and emitter (E) of IGBT6nl, respectively. Similarly, the diode D6n2 is connected in parallel with the IGBT 6n2. [0080] When the IGBT switch SW6n is on, the Y electrode Yn and the node ND2 are connected via the IGBT 6nl and the diode D6n2 (or the IGBT 6n2 and the diode D6nl). The diodes D6nl and D6n2 prevent a large reverse bias voltage (for example, a reverse noise voltage having a magnitude of the voltage Vs) from being applied to the IGBT 6nl and IGBT6n2 when the switch SW6n is off.

FIG. 13 shows details of operations in the address period ADR and the sustain period SUS shown in FIG. Detailed description of the same operations as those in FIG. 8 described above will be omitted. This embodiment differs from the first embodiment in the method of setting the discharge inhibition period DIS (control method of the switch SW6m) and the voltage of the Y electrode Ym in the discharge inhibition period DIS. Other waveforms are the same as those in the first embodiment (FIG. 8).

The discharge inhibition period DIS is generated by turning off the switch SW6m after the Y electrode Ym is clamped to the voltage −VsZ2 and before the switch SW1 is turned on. When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state and maintains the state (voltage) immediately before the switch SW6m is turned off. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage. The discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW4 being turned on. Note that the discharge inhibition period DIS may be generated after the Y electrode Ym is clamped to the voltage VsZ2 by controlling at the same timing as in the first embodiment.

[0083] In this embodiment, the switch SW6m is turned off throughout the sustain period SUS, and as shown by a thick broken line in the figure, during the sustain period SUS, a specific Y electrode (Ym in this example) Discharge can be prohibited. At this time, discharge occurs only in the address period ADR and the erase period ERS.

In this embodiment as well, the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the discharge inhibition period DIS, it is possible to prevent false contours and improve the quality of the display image.

As described above, also in the second embodiment, it is possible to obtain the same effect as in the first embodiment described above. Furthermore, by forming a scan driver circuit SD with an IGBT having no parasitic diode between the source and drain, the discharge inhibition period DIS can be generated regardless of whether the voltage of the Y electrode Ym is clamped to either the voltage VsZ2 or VsZ2. . Therefore, the discharge size Control for adjusting the number of vehicles can be simplified. In other words, the logic for generating the discharge inhibition period DIS can be easily configured in the sustain control circuit 64.

[0085] In the above-described embodiment, the present invention is configured so that one field has eight subfields SF1.

The example applied to the plasma display panel consisting of 8 was described. The invention is not limited to the powerful embodiments. For example, the present invention may be applied to a plasma display panel in which one field is composed of 10 or more subfields. Further, the number of subfield discharge cycles is not limited to 2 to the nth power (n is an integer of 2 or more). Furthermore, the subfields SFl-8 (Fig. 3) in the field FLD need not be arranged sequentially. For example, subfield SF8 may be arranged near the center of field FLD.

In the above-described embodiment, an example in which one pixel PX force is constituted by three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel PX may be composed of four or more cells. Alternatively, one pixel PX may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel PX force red (R), green ( It may contain cells that generate colors other than G) and Blue (B).

In the above-described embodiment, the example in which the scanning operation is continuously performed on the display lines adjacent to each other has been described. The invention is not limited to the powerful embodiments. For example, the scanning operation may not be continuously performed on display lines adjacent to each other. When scanning operation is performed every other line (one display line) or every other line (for example, display lines Ll, L3, L5, L2, L4 shown in Fig. 9 above, or display lines Ll, L Even in the order of 4, L2, L5, and L3), the priming particles diffuse up to several display lines ahead, so the priming particles in the cells (discharge space) of the display lines that will be scanned later increase. Also in this case, malfunction due to address discharge delay can be prevented, and the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, the example in which one adjustment subfield is selected has been described.

The invention is not limited to the powerful embodiments. For example, two adjustment subfields may be selected as shown in FIG. Figure 14 shows the same sequence of scan operations Fig. 6 shows another example when the flow shown in Fig. 6 is executed. The same elements as those described in FIG. 9 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

The gradation detection circuit 62 selects the subfield SF2 and the subfield SF3 as the adjustment subfield, and sets the number of sustain discharges in the adjustment subfields SF2 and SF3 to 4 times and 12 times, respectively. Then, the gradation detection circuit 62 sets the number of sustain discharges of the unnecessary subfield SF1 to 4 times. As a result, the address discharge of the display lines Ll and L2 can be continuously generated in the cells of the columns Cl, C3, C5, and C8.

[0090] In the cells in columns C3 and C8 of display line L1, eight sustain discharges, which are the same number as before the resetting of the number of discharge cycles, are generated using adjustment subfield SF2 and unnecessary subfield SF1. In cell C1 and C5 of display line L1, 16 sustain discharges, which are the same number as before the resetting of the number of discharge cycles, are generated using adjustment subfield SF3 and unnecessary subfield SF1. Also in this case, the same effect as the above-described embodiment can be obtained.

[0091] While the present invention has been described in detail above, the above-described embodiment and its modifications are merely examples of the invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

Industrial applicability

The present invention can be applied to a plasma display panel driving method and a plasma display apparatus.

Claims

The scope of the claims

[1] A first electrode and a second electrode formed in parallel to each other on a first substrate, and a second substrate disposed opposite to the first substrate through a discharge space, the first electrode A third electrode extending in a direction perpendicular to the electrode; a pixel formed by a cell formed at an intersection of the first electrode, the second electrode, and the third electrode; and formed along the first electrode. The display line is composed of a plurality of pixels, one field for displaying one screen is composed of a plurality of subfields, and the scanning operation for selecting a cell to be lit in each subfield is the display. This is performed for each line by controlling the second and third electrodes, and the selected cell is turned on by a sustain discharge between the first and second electrodes, and a plasma display panel that displays images in multiple gradations is provided. A driving method comprising:

For each display line, it is detected whether there is an unnecessary subfield that does not require sustain discharge,

If the unnecessary subfield is present in the first display line on which the scanning operation is performed first before the pair of display lines on which the scanning operation is performed continuously, the scanning is performed next to the first display line. Detecting whether or not the cell of the second display line on which the operation is performed is lit in a target subfield which is a subfield corresponding to the unnecessary subfield of the first display line;

When the cell of the second display line is lit in the target subfield, the standard number of times set in advance in the adjustment subfield that is at least one of the subfields of the first display line excluding the unnecessary subfield. A method for driving a plasma display panel, wherein a sustain discharge is generated a smaller number of times, and a sustain discharge is generated in the unnecessary subfield, the number of which is reduced in the adjustment subfield.

[2] According to the driving method of the plasma display panel according to claim 1,

A method for driving a plasma display panel, wherein the unnecessary subfield detection process is performed for each display line in an order reverse to the order of the scanning operation of the display lines.

[3] According to the driving method of the plasma display panel according to claim 1,

The adjustment subfield is lit in the target subfield of the second display line A method of driving a plasma display panel, characterized by being a sub-field that lights up most cells controlled by the third electrode in common with a cell to be operated.

[4] According to the driving method of the plasma display panel according to claim 1,

The pixel is composed of cells that respectively generate red, green, and blue light, and the unnecessary subfield is a subfield in which sustain discharge is detected to be unnecessary in all cells of one pixel. To drive a plasma display panel.

[5] According to the driving method of the plasma display panel according to claim 1,

The sustain discharge is performed by applying a pulse to the first and second electrodes,

The method of driving a plasma display panel, wherein the number of pulses applied to the second electrode is reduced when sustain discharge is generated less than the standard number in the adjustment subfield.

[6] A plasma display panel, a drive unit that drives the plasma display panel, and a control unit that controls the operation of the drive unit,

The plasma display panel is:

A first substrate and a second substrate facing each other through a discharge space;

A first electrode and a second electrode disposed in parallel with each other on the first substrate; a third electrode disposed on the second substrate in a direction orthogonal to the first and second electrodes; A pixel constituted by a cell formed at an intersection of the first and second electrodes and the third electrode;

A display line composed of pixels formed along the first electrode, one field for displaying one screen is composed of a plurality of subfields, and a cell to be lit in each subfield. A scan operation is performed for each display line by controlling the second and third electrodes, the selected cells are turned on by a sustain discharge between the first and second electrodes, and an image is displayed in multiple gradations. Display with

The drive unit is

A first drive circuit for applying a common pulse to the first electrode;

A second drive circuit for selectively applying a pulse to the second electrode; A third drive circuit that selectively applies a pulse to the third electrode, and the control unit includes:

For each of the display lines, whether or not there is an unnecessary subfield that does not require a sustain discharge is detected, and a scan operation is performed first on a pair of display lines that are continuously scanned. When the unnecessary subfield exists in one display line, a cell of the second display line on which a scanning operation is performed next to the first display line is a subfield corresponding to the unnecessary subfield of the first display line. A gradation detection circuit for detecting whether or not the power to light in the target subfield is,

In the first display line that is detected by the grayscale detection circuit that the unnecessary subfield exists, when the cell of the second display line is lit in the target subfield, the first display line excluding the unnecessary subfield is excluded. The adjustment subfield, which is at least one of the subfields of the display line, controls the operation of the first and second drive circuits in order to generate a sustain discharge that is less than a preset standard number of times. And a sustain control circuit for controlling the operation of the first and second drive circuits to generate a sustain discharge of the number of times reduced in the adjustment subfield in the subfield. apparatus.

[7] The plasma display device according to claim 6,

The plasma display device, wherein the gradation detection circuit performs the detection process of the unnecessary subfield for each display line in an order reverse to the scanning operation order of the display lines.

[8] The plasma display device according to claim 6,

The plasma display device characterized in that the adjustment subfield is a subfield for lighting the most cells controlled by the third electrode in common with the cells lit in the target subfield of the second display line. .

[9] The plasma display device according to claim 6, wherein

The pixel is composed of cells that respectively generate red, green, and blue light, and the unnecessary subfield is a subfield in which sustain discharge is detected to be unnecessary in all cells of one pixel. Plasma display device.

[10] In the plasma display device according to claim 6,

The plasma display apparatus, wherein the sustain control circuit reduces the number of pulses applied to the second electrode when the sustain sub-circuit generates a sustain discharge that is less than the standard number in the adjustment subfield.

[11] The plasma display device according to claim 6,

The second drive circuit is

A driver that generates a common signal waveform to be applied to the second electrode; and a switch that is formed corresponding to the second electrode and that selectively supplies the signal waveform to the second electrode. Prepared,

When the sustain control circuit generates a sustain discharge less than the standard number of times in the adjustment subfield, the sustain control circuit turns off a corresponding switch, thereby reducing the number of pulses applied to the second electrode. Plasma display device characterized by