KR20060091202A - Apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel that can improve manufacturing driving board of a plasma display panel, thereby reducing manufacturing costs as the plasma display panel is enlarged and securing a driving margin according to the driving method.

The apparatus for driving a plasma display panel according to the present invention supplies a reset pulse, an addressing pulse, and a sustain pulse to each of a plurality of subfields divided into a reset period, an address period, and a sustain period to a plasma display panel having a plurality of electrodes. In the plasma display panel driver including a scan driver, a sustain driver, an address driver, and a control board, each of the scan driver, the sustain driver, the address driver, and the control board is a plurality, and each of the plurality of control boards includes at least one scan driver, At least one sustain driver and at least one address driver.

Description

Device for Plasma Display Panel {Apparatus for driving Plasma Display Panel}

1 is a view showing the structure of a typical plasma display panel.

FIG. 2 is a diagram illustrating an electrode arrangement structure of the plasma display panel of FIG. 1. FIG.

3 is a view illustrating a driving waveform for driving the plasma display panel of FIG.

4 is a view showing a driving apparatus of a conventional plasma display panel.

5 is a view showing a driving device of a plasma display panel according to the present invention;

6 is a view showing an example of a plasma display device in which a driving device of the plasma display panel of the present invention is coupled.

7 is a view for explaining an example of a method of controlling with a different control board for each region of a plasma display panel.

FIG. 8 is a view showing an example of a driving method using the driving apparatus of the plasma display panel according to the present invention of FIG. 5;

<Description of the symbols for the main parts of the drawings>

500a, 500b, 500c, 500d, 501a, 501b, 501c, 501d: address driver

502a and 502b: scan driver 503a and 503b: sustain driver

504a, 504b: control board

The present invention relates to a plasma display panel, and more particularly, to improve the driving board of the plasma display panel, thereby reducing the manufacturing cost as the plasma display panel is enlarged, and driving the plasma according to the driving method. It relates to a drive of a display panel.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As shown in FIG. 1, a plasma display panel includes a front panel in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are arranged on a front glass 101 that is a display surface on which an image is displayed. The rear panel 110 in which the plurality of address electrodes 113 are arranged so as to intersect the plurality of sustain electrode pairs on the back glass 111 forming the back surface 100 and the rear surface is coupled in parallel with a predetermined distance therebetween. .

The front panel 100 is made of a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode (a) formed of a transparent ITO material and a metal material to mutually discharge and maintain light emission of the cells in one discharge cell. The scan electrode 102 and the sustain electrode 103 provided as the bus electrode b are included in pairs. The scan electrode 102 and the sustain electrode 103 are covered by one or more upper dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and to facilitate the discharge conditions on the upper dielectric layer 104 top surface. A protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear panel 110 is arranged such that a plurality of discharge spaces, that is, barrier ribs 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 which perform address discharge to generate vacuum ultraviolet rays are arranged in parallel with the partition wall 112. On the upper side of the rear panel 110, R, G, and B phosphors 114 which emit visible light for image display during address discharge are coated. A lower dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

The plasma display panel having such a structure is formed of a plurality of discharge cells in a matrix structure, and is driven with a drive module including a drive circuit for supplying a predetermined pulse to the discharge cells.

FIG. 2 is a diagram illustrating an electrode arrangement structure of the plasma display panel of FIG. 1.

As shown in FIG. 2, in the typical plasma display panel, the discharge cells 30 cross the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. It can be seen that each point is configured.

The scan electrode lines Y1 to Ym supply the scan pulses and the sustain pulses so that the discharge cells 30 are scanned in units of lines, and the discharges are maintained in the discharge cells 30.

The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to maintain the discharge in the discharge cells 30 together with the scan electrode lines Y1 to Ym. The address electrode lines X1 to Xn supply data pulses synchronized with the scan pulse in line units so that the discharge cells 30 to be discharged are selected according to the logic value of the data pulses.

The plasma display panel is driven by dividing one frame into a plurality of subfields. An example of such a driving method is an ADS (Address and Display Separation) driving method which is driven by being divided into an address period and a display period, that is, a sustain period. .

In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. Each of these subfields has the same reset period (RPD) and address period (APD) and gives different weights to the sustain period (SPD). Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data. Looking at such a drive waveform as shown in FIG.

3 is a diagram illustrating a driving waveform for driving the plasma display panel of FIG. 1.

As shown in FIG. 3, a general plasma display panel uses the reset pulse RP in the reset period RPD to generate front lighting discharge, and then erases wall charges so that all the discharge cells 30 are wall charged. Reset to the remaining off state. To this end, the scan electrode lines Y1 to Ym have a reset pulse RP, which gradually decreases to a rising ramp pulse and a base voltage (0V) that gradually increase to the peak voltage Vr based on the step voltage Vs. A falling ramp pulse is supplied. Primary dark discharge occurs in all the discharge cells 30 by the rising ramp pulse. Next, secondary dark discharge occurs in all the discharge cells 30 by the falling ramp pulse and the bias pulse BP supplied to the sustain electrode lines Z1 through Zm. Subsequently, the wall charges formed in the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm decrease according to the falling ramp pulse, and thus all the discharge cells 30 are initialized to the off state where the wall charges remain. do. In this reset period RPD, the voltages of the data electrode lines X1 to Xn are fixed to the base voltage 0V.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and data is stored in each of the address electrode lines X1 to Xn in synchronization with the scan pulse SP. The pulse DP is selectively supplied. As a result, address discharge is generated in the discharge cells supplied with the data pulse DP together with the scan pulse SP, so that the wall charge for the next sustain discharge is sufficiently formed. On the other hand, in the discharge cells to which the data pulse DP is not supplied together with the scan pulse SP, the address discharge does not occur, thereby maintaining the off state.

In the sustain period SPD, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the address period APD. The state of the discharge cell is maintained. Specifically, the discharge cells in the on state in which the wall charges are sufficiently formed in the address period APD remain in the on state by the discharge by the Y and Z sustain pulses SUSPy and SUSPz, and the discharge cells in the off state are in the off state without discharge. Keep it. The wall charges present in all the discharge cells 30 are generated by supplying the erase pulse EP to the sustain electrode lines Z1 to Zm in the erase period EPD subsequent to the sustain period SPD. To be cleared.

In order to supply these driving waveforms to the discharge cells 30 of the plasma display panel shown in FIG. 2, the driving device is provided on the rear side of the frame located on the rear side of the plasma display panel. An example in which a driving device is installed in the plasma display panel is shown in FIG. 4.

4 is a view showing a driving apparatus of a conventional plasma display panel.

As shown in FIG. 4, the driving apparatus of the plasma display panel includes a scan driver 45 for driving the scan electrode lines Y1 to Ym of the plasma display panel 40, and the sustain electrode lines Z1 to Zm. ), A sustain driver 48 for driving), a data driver 50 for driving address electrode lines X1 to Xm, the scan driver 45, a sustain driver 48, and a data driver 50. And a power supply board (not shown) for supplying power to each of the scan, sustain, data driver, and control parts 42, 45, 48, and 50.

The scan driver 45 includes a scan driver board 44 that generates the reset pulse RP and the scan pulse SP shown in FIG. 3 of the plasma display panel 40, and a Y that generates the Y sustain pulse SUSPy. A sustain driver board 46 is provided. The scan driver board 44 transmits the scan pulse SP to the scan electrode lines Y1 to Ym of the PDP 40 via the Y flexible printed circuit (FPC) 51. Supply. The Y sustain driver board 46 supplies the Y sustain pulse SUSPy to the scan electrode lines Y1 to Ym via the scan driver board 44 and the Y FPC 51.

The sustain driver 47 includes a Z sustain driver board 48 for generating the bias pulses BP and Z sustain pulses SUSz shown in FIG. 3, and the Z sustain driver board passes through the Z FPC 52. Supply to sustain electrode lines Z1 to Zm of the plasma display panel 40.

The data driver 49 includes an X data driver board 50 for generating the data pulse DP shown in FIG. 3, and the X data driver board 50 is connected to the plasma display panel via the X FPC 54. Supply to the address electrode lines X1 to Xn of 40.

The control unit 42 generates the timing control signals of the scan, sustain, and data driver units, respectively. The control unit 42 sends the Y timing control signal to the scan driver 45 through the first FPC 56 and the Z timing control signal to the sustain driver 47 via the second FPC 58. The X timing control signal is supplied to the data driver 49 via the third FPC 60.

Meanwhile, as the high resolution products of the plasma display panel become full-fledged, large plasma display panel products that implement Full HD (1920 * 1080) resolution have been developed. Products of such a large plasma display panel also form a drive structure as shown in FIG. That is, the Y scan driver including the sustain circuit and the Z sustain driver are composed of one.

However, such a structure has a problem that when the plasma display panel is enlarged, it is not easy to handle and the production cost increases because the drive unit is also enlarged to a single unit.

In addition, there is a problem that control of driving is complicated because one large driving unit is responsible for switching of driving pulses applied to all electrodes. As the control of such driving becomes complicated, there is a problem that the driving margin decreases.

Accordingly, an object of the present invention is to provide a driving apparatus of a plasma display panel which can improve handling driving and production cost by improving a driving unit of a plasma display panel and at the same time improve driving margin by changing driving methods.

In order to solve the above technical problem, a plasma display panel driving apparatus according to the present invention includes a reset pulse and an addressing pulse in each period of a plurality of subfields divided into a reset period, an address period, and a sustain period in a plasma display panel having a plurality of electrodes. In the plasma display panel driver including a scan driver, a sustain driver, an address driver, and a control board for supplying a sustain pulse, a plurality of scan drivers, a sustain driver, an address driver, and a control board are provided, respectively. At least one scan driver, at least one sustain driver, and at least one address driver.

Here, the plurality of control boards are characterized in that each control the same number of scan drivers.

In addition, the plurality of control boards may respectively control driving of a predetermined region of the plasma display panel.

In addition, the plurality of control boards include a first control board and a second control board, the plasma display panel is divided into an upper panel and a lower panel with respect to the center, the first control board controls the driving of the upper panel, 2 control board is characterized in that for controlling the drive of the lower panel.

The scan driver and the sustain driver may be independently driven or simultaneously driven in at least one of a reset period, an address period, and a sustain period.

In addition, the scan driver includes a first scan driver and a second scan driver, the first scan driver supplies a reset pulse to the panel in the odd-numbered reset period of the subfield, and the second scan driver supplies the even number of the subfields. The reset pulse is supplied to the panel in the reset period.

In addition, the scan driver includes a first scan driver and a second scan driver, the first scan driver supplies a reset pulse to the panel during the low gradation reset period of the subfield, and the second scan driver supplies the high gradation reset of the subfield. A reset pulse is supplied to the panel during the period.

In addition, the scan driver includes a first scan driver and a second scan driver, the first scan driver supplies the scan pulse to the panel in the odd-numbered address period of the subfield, and the second scan driver is the even number of the subfield. A scan pulse is supplied to the panel in the address period.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a view showing a driving device of a plasma display panel according to the present invention.

As illustrated in FIG. 5, a scan driver 502a supplies a reset pulse, an addressing pulse, and a sustain pulse to each of a plurality of subfields divided into a reset period, an address period, and a sustain period to a plasma display panel having a plurality of electrodes. In the plasma display panel driver including a sustain driver (503a, 503b), an address driver (500a, 500b, 500c, 500d, 501a, 501b, 501c, 501d), and a control board (504a, 504b). The aforementioned scan drivers 502a and 502b, sustain drivers 503a and 503b, address drivers 500a, 500b, 500c, 500d, 501a, 501b, 501c and 501d, and a plurality of control boards 504a and 504b, respectively, Each of the plurality of control boards 504a and 504b includes at least one scan driver 502a and 502b, at least one sustain driver 503a and 503b, and at least one address driver 500a, 500b, 500c, 500d, 501a and 501b. , 501c, 501d).

That is, the plasma display panel of the present invention includes a plurality of scan drivers 502a and 502b, a plurality of sustain drivers 503a and 503b, and a plurality of address drivers 500a, 500b, 500c, 500d, 501a, 501b, 501c, and 501d. And a plurality of control boards 504a and 504b. Here, in FIG. 5, the number of the scan driver is 2, the number of the sustain driver is 2, the number of the address driver is 2, and the number of the control board is 2, but the present invention is not limited thereto. will be.

6 illustrates a plasma display apparatus in which the driving apparatus of the plasma display panel of the present invention is mounted. Here, the aforementioned plasma display apparatus means that a driving unit for driving is coupled to the plasma display panel.

The driving device of the plasma display panel according to the present invention will be described with reference to FIG. 6.

6 is a view showing an example of a plasma display device combined with a driving device of the plasma display panel of the present invention.

Referring to FIG. 6, the scan drivers 502a and 502b described above drive the scan electrode lines Y1 to Ym, and the reset pulse RP and the reset period and the address period when the plasma display panel 400 is driven. The scan pulse SP is supplied to the scan electrode line. As described above, the scan drivers 502a and 502b are plural and the number of the scan drivers 502a and 502b is set in consideration of the screen size of the plasma display panel. The scan driving units 502a and 502b may scan scan lines SP of the plasma display panel 400 via a flexible printed circuit (FPC) 510a and 510b. The Y sustain pulse SUSPy is supplied to the scan electrode lines Y1 to Ym.

The sustain drivers 503a and 503b drive the sustain electrode lines Z1 to Zm, and apply a bias pulse BP and a Z sustain pulse SUSz to the sustain electrode line during the address period during the driving of the plasma display panel 400. do. The sustain drivers 503a and 503b are also plural and preferably provided in proportion to the screen size of the plasma display panel 400. The sustain drivers 503a and 503b supply the bias pulses BP and the Z sustain pulses SUSz to the sustain electrode lines Z1 to Zm of the plasma display panel 400 via the FPCs 520a and 520b. .

The address drivers 500a, 500b, 500c, 500d, 501a, 501b, 501c, and 501d drive the address electrode lines X1 to Xm, and the data pulse DP in the address period when the plasma display panel 400 is driven. Is supplied to the address electrode lines X1 to Xn of the plasma display panel 400 via the FPC 540.

The control boards 504a and 504b include a plurality of scan drivers 502a and 502b, a plurality of sustain drivers 503a and 503b, and a plurality of address drivers 500a, 500b, 500c, 500d, 501a, 501b, 501c and 501d. Each of the timing control signals. There are a plurality of control boards 504a and 504b as described above, and the Z timing control via the FPCs 580a and 580b via the FPCs 580a and 580b via the FPCs 560a and 560b. The signal is supplied to the sustain drivers 503a and 503b, and the X timing control signal is supplied to the address drivers 500a, 500b, 500c, 500d, 501a, 501b, 501c, and 501d via the FPC 600.

Since the control boards 504a and 504b described above are plural, the control boards 504a and 504b may perform different control operations. For example, the control board includes a first control board 504a and a second control board 504b as shown in FIG. 5, and the first control board 504a and the second control board 504b are different from each other. The scan driver or the sustain driver or the address driver is controlled. In other words, the first control board 504a controls the operations of the address driver 500a, 500b, 500c, and 500d, the scan driver 502a, and the sustain driver 503a as shown in FIG. 504b controls the operation of the address driver 501a, 501b, 501c and 501d, the scan driver 502b and the sustain driver 503b. Accordingly, by controlling the plurality of scan, sustain and address drivers for driving one plasma display panel according to different control paths, the control operation can be relatively simple. This is because the absolute number of scan or sustain or address drivers whose switching is controlled by one control board is reduced.

Here, the control boards 504a and 504b described above may control the same number of scan drivers 502a and 502b or the sustain drivers 503a and 503b or control different numbers of scan or sustain drivers. More preferably, however, in order to balance control, each of the plurality of control boards 504a and 504b controls the same number of scan drivers or sustain drivers.

On the other hand, from the perspective of the plasma display panel 400, assuming that the plasma display panel 400 is divided into regions having a predetermined size, the plurality of control boards 504a and 504b respectively drive certain regions of the plasma display panel. It is preferable to control each. An example of such a method will be described with reference to FIG. 7.

FIG. 7 is a view for explaining an example of a method of controlling by a different control board for each region of the plasma display panel.

Referring to FIG. 7, the plasma display panel 700 is divided into two regions, for example, region A and region B, as shown in FIG. 7. In this divided region, the control board 504a controls driving, and the region B The control board at 504b controls the drive.

More preferably, the plasma display panel 700 is divided into two areas in the horizontal direction with respect to the center of the panel and divided into the A area and the B area, and the divided areas are controlled by using different control boards. . For example, the plurality of control boards include a first control board 504a and a second control board 504b, and the plasma display panel is divided into an upper panel A and a lower panel B based on the center portion. Assuming, the first control board 504a controls the driving of the upper panel A, and the second control board 504b controls the driving of the lower panel B. As shown in FIG.

As described above, the driving device of the plasma display panel according to the present invention can solve the mass production problem caused by the increase in size of the plasma display panel by configuring each driving unit or control board in plurality, and the plurality of driving units According to the control of each control board, the driving waveform can be generated independently in the reset section, the address section and the sustain section, or the driving waveform can be generated at the same time, thereby improving the driving margin. It is also possible to improve the exothermic characteristics.

In the driving method according to the driving apparatus of the plasma display panel of the present invention having such a structure, a plurality of subfields are divided into a reset period, an address period, and a sustain period, and a predetermined pulse is supplied in each period to express an image. As such, an example of driving one plasma display panel using the plurality of control boards 504a and 504b will be described with reference to FIG. 8.

8 is a diagram illustrating an example of a driving method using the driving apparatus of the plasma display panel according to the present invention of FIG. 5.

As shown in FIG. 8, first, during the reset period RPD, the front writing discharge is generated by using the reset pulse RP, and then the wall charge is erased so that all of the discharge cells (not shown) remain. To the off state. To this end, a scan driver including a plurality of scan driver boards supplies a plurality of reset pulses RP to the scan electrode lines Y1 to Ym.

More specifically, the plurality of reset pulses RP1 and RP2 supplied by the scan driver 502a are supplied to the panel independently during the reset period of each subfield, and preferably, the scan driver is the first as described above with reference to FIG. 5. And a scan driver 502a and a second scan driver 502b, each of which supplies reset pulses RP1 and RP2 to the panel. At this time, as shown in (a), the first reset pulse RP1 by the first scan driver 502a is supplied to the panel during the odd-numbered reset period of the subfield SF, and is supplied to the second scan driver 502b. The second reset pulse RP2 is supplied to the panel during the even reset period of the subfield. Alternatively, as shown in (b), the first reset pulse RP1 by the first scan driver 502a is supplied to the panel during the low gradation reset periods SF1, SF2, SF3, SF4 of the subfield, and the second scan driver The second reset pulse RP2 by 502b is supplied to the panel during the high gradation reset periods SF5, SF6, SF7, SF8 of the subfield. The operation of the first scan driver 502a and the second scan driver 502b is more preferably performed by different control boards.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and data is provided to each of the data electrode lines X1 to Xn in synchronization with the scan pulse SP. Pulses DP (not shown) are optionally supplied. To this end, the plurality of scan drivers 502a and 502b respectively supply a plurality of scan pulses SP to the scan electrode lines Y1 to Ym.

More specifically, the plurality of reset pulses SP1 and SP2 generated by the scan drivers 502a and 502b are supplied to the panel independently in the address period of each subfield, and preferably, as shown in (c), the first scan The first scan pulse SP1 by the driver 502a is supplied to the panel during the odd-numbered address period of the subfield SF, and the second scan pulse SP2 by the second scan driver 502b is applied to the subfield. It is supplied to the panel during the even address period.

In the sustain period SPD, the Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the discharge determined in the address period APD. Maintain the state of the cell. In detail, the scan driver and the sustain driver supply a plurality of sustain pulses to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm.

As described above, it will be understood by those skilled in the art that the above-described technical configuration may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention can reduce manufacturing costs incurred as the plasma display panel is enlarged. In addition, the driving margin can be improved by supplying independent driving waveforms to the panel in each section when the plasma display panel is driven. have.

Claims (8)

A scan driver, a sustain driver, an address driver, and a control board for supplying reset pulses, addressing pulses, and sustain pulses in each of the plurality of subfields divided into a reset period, an address period, and a sustain period to a plasma display panel having a plurality of electrodes. In the plasma display panel driving apparatus comprising: The scan driver, the sustain driver, the address driver and the control board are each in plural number, And each of the plurality of control boards controls at least one or more of the scan driver, at least one sustain driver, and at least one address driver. The method of claim 1, The plurality of control boards And driving the same number of scan drivers as possible. The method of claim 1, The plurality of control boards And controlling driving of a predetermined area of the plasma display panel, respectively. The method of claim 3, wherein The plurality of control boards Including a first control board and a second control board, The plasma display panel is divided into an upper panel and a lower panel with respect to the center. And the first control board controls the driving of the upper panel, and the second control board controls the driving of the lower panel. The method of claim 1, The scan driver and the sustain driver And at least one of the reset period, the address period, and the sustain period is independently driven or simultaneously driven. The method of claim 1, The scan driver includes a first scan driver and a second scan driver, The first scan driver supplies the reset pulse to the panel in the odd-numbered reset period of the subfield, And wherein the second scan driver supplies the reset pulse to the panel in an even numbered reset period of a subfield. The method of claim 1, The scan driver includes a first scan driver and a second scan driver, The first scan driver supplies the reset pulse to the panel during the low gradation reset period of the subfield, And the second scan driver supplies the reset pulse to the panel during the high gradation reset period of the subfield. The method of claim 1, The scan driver includes a first scan driver and a second scan driver, The first scan driver supplies the scan pulse to a panel in an odd numbered address period of the subfield, And the second scan driver supplies the scan pulse to the panel in an even address period of the subfield.

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