KR100692821B1 - Device for driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving device of a plasma display panel.

In the plasma display panel driving apparatus of the present invention, a plurality of subfields are divided into a reset period, an address period, and a sustain period, and a scan driver, a sustain driver, and an address driver for supplying a reset pulse, an addressing pulse, and a sustain pulse according to each period. The scan driver includes a plurality of scan driver boards and a first sustain driver board, the sustain driver includes a plurality of second sustain driver boards, and the scan driver and the sustain driver include the reset period and the address period. And independently driven or simultaneously driven for each subfield in at least one of the sustain periods.

Description

Plasma Display Panel Driver {Device for driving Plasma Display Panel}

1 is an enlarged view of one discharge cell constituting a conventional AC PDP.

FIG. 2 is a diagram illustrating an overall electrode arrangement structure of a PDP including a discharge cell 30 shown in FIG. 1.

FIG. 3 is a diagram showing a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 of a plurality of subfields.

4 is a view showing a driving apparatus of a conventional PDP.

5 is a view showing a driving device of the PDP according to the present invention;

6 illustrates a method of driving a PDP according to the present invention.

***** Explanation of symbols for the main parts of the drawings *****

400: PDP 420: control unit

450: scan driver 470: sustain driver

490: data driver

The present invention relates to a plasma display panel, and more particularly, to improve the driving board of the plasma display panel, thereby reducing the manufacturing cost as the plasma display panel is enlarged, and driving the plasma according to the driving method. It relates to a drive of a display panel.

In general, a plasma display panel (hereinafter referred to as "PDP") displays an image including a character or a graphic by emitting phosphors by 147 nm ultraviolet rays generated when a He + Xe or Ne + Xe inert mixed gas is discharged. Done.

1 is an enlarged view of one discharge cell constituting a conventional AC PDP. The discharge cells 30 shown in FIG. 1 are sustain electrode pairs 12A and 12B sequentially formed on the upper substrate 10. FIG. And an upper plate having an upper dielectric layer 14 and a protective film 16, and a data electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed on the lower substrate 18. It has a bottom plate.

Each of the sustain electrode pairs 12A and 12B is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 12A and 12B are separated into the scan electrode 12A and the sustain electrode 12B. The scan electrode 12A mainly supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12B mainly supplies a sustain signal. The data electrode 20 is formed to cross the sustain electrode pairs 12A and 12B. The data electrode 20 supplies a data signal for address discharge. The charges generated by the discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside. The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the data electrode 20 to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge. The discharge cell 30 having such a structure is selected as the counter discharge by the data electrode 20 and the scan electrode 12A, and then maintains the discharge by surface discharge by the sustain electrode pairs 12A and 12B. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

FIG. 2 illustrates the overall electrode arrangement structure of the PDP including the discharge cells 30 shown in FIG. 1. In FIG. 2, it can be seen that the discharge cells 30 are configured at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the data electrode lines X1 to Xn. The scan electrode lines Y1 to Ym supply the scan pulses and the sustain pulses so that the discharge cells 30 are scanned in units of lines, and the discharges are maintained in the discharge cells 30. The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to maintain the discharge in the discharge cells 30 together with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn supply data pulses synchronized with the scan pulse in line units so that the discharge cells 30 to be discharged are selected according to the logic value of the data pulses.

The PDP driving method is typically an ADS (Address and Display Separation) driving method which is driven separately into an address period and a display period, that is, a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. Each of these subfields has the same reset period (RPD) and address period (APD) and gives different weights to the sustain period (SPD). Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

FIG. 3 illustrates a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 among a plurality of subfields.

As shown in FIG. 3, the PDP initializes all of the discharge cells 30 to an off state in which wall charge remains by erasing wall charges after the front writing discharge is generated using the reset pulse RP in the reset period RPD. Let's do it. To this end, the scan electrode lines Y1 to Ym have a reset pulse RP, which gradually decreases to a rising ramp pulse and a base voltage (0V) that gradually increase to the peak voltage Vr based on the step voltage Vs. A falling ramp pulse is supplied. Primary dark discharge occurs in all the discharge cells 30 by the rising ramp pulse. Next, secondary dark discharge occurs in all the discharge cells 30 by the falling ramp pulse and the bias pulse BP supplied to the sustain electrode lines Z1 through Zm. Subsequently, the wall charges formed in the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm decrease according to the falling ramp pulse, and thus all the discharge cells 30 are initialized to the off state where the wall charges remain. do. In this reset period RPD, the voltages of the data electrode lines X1 to Xn are fixed to the base voltage 0V.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and data is provided to each of the data electrode lines X1 to Xn in synchronization with the scan pulse SP. The pulse DP is selectively supplied. As a result, address discharge is generated in the discharge cells supplied with the data pulse DP together with the scan pulse SP, so that the wall charge for the next sustain discharge is sufficiently formed. On the other hand, in the discharge cells to which the data pulse DP is not supplied together with the scan pulse SP, the address discharge does not occur, thereby maintaining the off state.

In the sustain period SPD, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the address period APD. The state of the discharge cell is maintained. Specifically, the discharge cells in the on state in which the wall charges are sufficiently formed in the address period APD remain in the on state by discharges by the Y and Z sustain pulses SUSPy and SUSPz, and the discharge cells in the off state are discharged without discharge. Keep off. The wall charges present in all the discharge cells 30 are generated by supplying the erase pulse EP to the sustain electrode lines Z1 to Zm in the erase period EPD subsequent to the sustain period SPD. To be cleared.

In order to supply these driving waveforms to the PDP shown in FIG. 2, the driving device is provided on the rear surface of the heat sink 64 located on the back side of the PDP 40 as shown in FIG. 4.

The driving apparatus of the PDP shown in FIG. 4 includes a scan driver 45 for driving the scan electrode lines Y1 to Ym of the PDP 40 and a sustain driver for driving the sustain electrode lines Z1 to Zm. 48, a data driver 50 for driving the data electrode lines X1 to Xm, a control unit for controlling the scan driver 45, the sustain driver 48, and the data driver 50 ( 42) and a power board (not shown) for supplying power to each of the scan, sustain, data driver, and control units 42, 45, 48, and 50.

The scan driver 45 includes a scan driver board 44 for generating the reset pulse RP and the scan pulse SP shown in FIG. 3 of the PDP 40, and a Y sustain driver for generating the Y sustain pulse SUSPy. Board 46 is provided. The scan driver board 44 transmits the scan pulse SP to the scan electrode lines Y1 to Ym of the PDP 40 via the Y flexible printed circuit (FPC) 51. Supply. The Y sustain driver board 46 supplies the Y sustain pulse SUSPy to the scan electrode lines Y1 to Ym via the scan driver board 44 and the Y FPC 51.

The sustain driver 47 includes a Z sustain driver board 48 for generating the bias pulses BP and Z sustain pulses SUSz shown in FIG. 3, and the Z sustain driver board passes through the Z FPC 52. Supply to sustain electrode lines Z1 to Zm of the PDP 40.

The data driver 49 has an X data driver board 50 for generating the data pulse DP shown in FIG. 3, and the X data driver board 50 is connected to the PDP 40 via the X FPC 54. To the data electrode lines X1 to Xn.

The controller 42 generates each of the timing control signals of the scan, sustain, and data drivers. The control unit 42 sends the Y timing control signal to the scan driver 45 through the first FPC 56 and the Z timing control signal to the sustain driver 47 via the second FPC 58. The X timing control signal is supplied to the data driver 49 via the third FPC 60.

On the other hand, as PDP's high resolution products become full-fledged, large PDP products that implement Full HD (1920 * 1080) resolution have been developed. Such a large PDP product also has a drive structure as shown in FIG. 4. That is, the Y scan driver including the sustain circuit and the Z sustain driver are composed of one.

However, such a structure is difficult to handle as the drive unit is also enlarged to a single large sized PDP, there is a problem that the production cost increases.

Accordingly, an object of the present invention is to provide a driving apparatus of a plasma display panel which can improve handling driving and production cost by improving a driving unit of a plasma display panel and at the same time improve driving margin by changing driving methods.

In the plasma display panel driving apparatus according to the present invention for solving the above technical problem, a plurality of subfields are divided into a reset period, an address period, and a sustain period, and a scan for supplying a reset pulse, an addressing pulse, and a sustain pulse according to each period is provided. And a driver, a sustain driver, and an address driver, wherein the scan driver includes a plurality of scan driver boards and a first sustain driver board, the sustain driver includes a plurality of second sustain driver boards, and the scan driver and the sustain driver. The driving unit may be driven independently or simultaneously for each subfield in at least one of the reset period, the address period, and the sustain period.

The scan driver includes a first scan driver board and a second scan driver board, the scan driver supplies a reset pulse generated from the first scan driver board to the panel in the reset period of the odd number of subfields, The reset pulse generated from the second scan driver board is supplied to the panel in the even-numbered reset period of the subfield.

The scan driver includes a first scan driver board and a second scan driver board, the scan driver supplies a reset pulse generated from the first scan driver board to the panel during the low gray level reset period of the subfield, And a reset pulse generated from the second scan driver board to the panel during the high gradation reset period of the subfield.

The scan driver includes a first scan driver board and a second scan driver board, the scan driver supplies a scan pulse generated from the first scan driver board to a panel in an odd-numbered address period of the subfield, The scan pulse generated from the second scan driver board is supplied to the panel in the even address period of the subfield.

The plurality of scan driver boards, the first sustain driver board, and the second sustain driver board may be electrically connected to the same driver boards to supply predetermined pulses to the panel.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a view showing a driving device of a plasma display panel according to the present invention. As shown, the driving apparatus of the plasma display panel according to the present invention includes a scan driver 450 for driving scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm. The control unit for controlling the sustain driver 480, the data driver 500 for driving the data electrode lines X1 to Xm, the scan driver 450, the sustain driver 480, and the data driver 500. 420 and a power board (not shown) for supplying power to each of the scan, sustain, data driver and control units 420, 450, 480, and 500.

The scan driver 450 includes scan driver boards 440a and 440b which generate a reset pulse RP and a scan pulse SP during a reset period and an address period when the PDP 400 is driven, and a Y sustain pulse SUSPy during the sustain period. A plurality of first sustain driver boards 460a and 460b for generating a) are provided. The number of scan driver boards and first sustain driver boards is provided in proportion to the screen size of the PDP. As such, the scan driver including the plurality of scan driver boards and the first sustain driver board may be configured via the scan driver boards 440a and 510b through Y flexible printed circuits (hereinafter referred to as FPCs) 510a and 510b. The scan pulse SP generated from the 440b is supplied to the scan electrode lines Y1 to Ym of the PDP 400, and the first scan pulses SP are supplied through the scan driver boards 440a and 440b and the Y FPCs 510a and 510b. The Y sustain pulse SUSPy generated from the sustain driver boards 460a and 460b is supplied to the scan electrode lines Y1 to Ym.

The sustain driver 470 includes a plurality of second sustain driver boards 480a and 480b for generating a bias pulse BP and a Z sustain pulse SUSz in an address period when the PDP 400 is driven, and the second sustain driver The number of boards is also provided in proportion to the screen size of the PDP. As such, the sustain driver 470 having the plurality of second sustain driver boards receives the bias pulses BP and Z sustain pulses SUSz generated by the second sustain driver board via the FPCs 520a and 520b. Supply to sustain electrode lines Z1 to Zm of 400.

The data driver 490 includes an X data driver board 500 that generates data pulses DP in an address period when the PDP 400 is driven. The data pulses DP pass through the X FPC 540. Data electrode lines X1 to Xn of 400 are supplied.

The controller 420 generates timing control signals of the scan driver 450, the sustain driver 470, and the data driver 490, respectively. The control unit 420 transmits the Y timing control signal to the scan driver 450 via the first FPCs 560a and 560b and the Z timing control signal through the second FPCs 580a and 580b. 480, the X timing control signal is supplied to the data driver 490 via the third FPC 600.

As described above, the driving device of the plasma display panel according to the present invention can solve the mass production problem caused by the increase in the size of the PDP by forming a plurality of driver boards of each driving unit. In addition, the driving waveform can be generated independently or simultaneously at any one of the address section and the sustain section, thereby improving the driving margin and improving the heat generation characteristics of the PDP.

On the other hand, in the driving device of the plasma display panel according to the present invention, the waveforms in each section generated from the plurality of driver boards should appear as the same function in the panel. Therefore, the plurality of scan driver boards, the first sustain driver board, and the second sustain driver board included in the scan driver 450, the sustain driver 470, and the data driver 490 of the present invention may include electrical connection means such as connectors (c). Use the) to connect the same driver boards electrically.

In the driving method according to the driving apparatus of the plasma display panel of the present invention having such a structure, a plurality of subfields are divided into a reset period, an address period, and a sustain period, and a predetermined pulse is supplied in each period to express an image. This will be described with reference to FIG. 6.

6 is a view showing a plasma display panel driving method of the present invention. As shown, first, in the reset period RPD, the front lighting discharge is generated by using the reset pulse RP, and then the wall charges are erased to turn off all the discharge cells 30 in the off state where the wall charges remain. Initialize To this end, a scan driver including a plurality of scan driver boards supplies a plurality of reset pulses RP to the scan electrode lines Y1 to Ym.

More specifically, the plurality of reset pulses RP1 and RP2 generated from the plurality of scan driver boards 440a and 440b of the scan driver 450 are supplied to the panel independently in the reset period of each subfield, and preferably the scan is performed. The driving unit includes two first scan driver boards 440a and A and two second scan driver boards 440b and B to supply reset pulses RP1 and RP2 to the panel. At this time, as shown in (a), the first reset pulse RP1 generated from the first scan driver boards 440a and A is supplied to the panel during the odd-numbered reset period of the subfield SF, and the second scan driver The second reset pulse RP2 generated from the boards 440b and B is supplied to the panel during the even reset period of the subfield. Alternatively, as shown in (b), the first reset pulse RP1 generated from the first scan driver boards 440a and A is supplied to the panel during the low gradation reset periods SF1, SF2, SF3, SF4 of the subfield, The second reset pulse RP2 generated from the second scan driver boards 440b and B is supplied to the panel during the high gradation reset periods SF5, SF6, SF7, SF8 of the subfield.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and data is provided to each of the data electrode lines X1 to Xn in synchronization with the scan pulse SP. Pulses DP (not shown) are optionally supplied. To this end, a scan driver including a plurality of scan driver boards supplies the plurality of scan pulses SP to the scan electrode lines Y1 to Ym.

More specifically, the plurality of reset pulses SP1 and SP2 generated from the plurality of scan driver boards 440a and 440b of the scan driver 450 are supplied to the panel independently in the address period of each subfield, and preferably the scan is performed. The driving unit includes two first scan driver boards 440a and A and second scan driver boards 440b and B to supply the scan pulses SP1 and SP2 to the panel. At this time, as shown in (c), the first scan pulse SP1 generated from the first scan driver boards 440a and A is supplied to the panel during the odd-numbered address period of the subfield SF, and the second scan driver. The second scan pulse SP2 generated from the boards 440b and B is supplied to the panel during the even address period of the subfield.

In the sustain period SPD, the Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the discharge determined in the address period APD. Maintain the state of the cell. In detail, the plurality of first sustain driver boards and the second sustain driver boards included in the scan driver and the sustain driver apply a plurality of sustain pulses to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm. Supply.

As described above, the technical configuration of the present invention described above will be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. . Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention can reduce the manufacturing cost caused by the enlargement of the PDP, and also improve the driving margin by supplying independent driving waveforms to the panels in each section during the PDP driving.

Claims (5)

In a plasma display panel driving apparatus, a plurality of subfields are divided into a reset period, an address period, and a sustain period and include a scan driver, a sustain driver, and an address driver for supplying a reset pulse, an addressing pulse, and a sustain pulse according to each period. The scan driver includes a plurality of scan driver boards and a first sustain driver board. The sustain driver includes a plurality of second sustain driver boards, The scan driver and the sustain driver And at least one of the reset period, the address period, and the sustain period is independently driven for each subfield for the same electrode. The method of claim 1, The scan driver includes a first scan driver board and a second scan driver board, The scan driver A reset pulse generated from the first scan driver board is supplied to the panel in the odd-numbered reset period of the subfield, And a reset pulse generated from the second scan driver board to the panel in the even-numbered reset period of the subfield. The method of claim 1, The scan driver includes a first scan driver board and a second scan driver board, The scan driver A reset pulse generated from the first scan driver board is supplied to the panel in the low gradation reset period of the subfield, And a reset pulse generated from the second scan driver board to the panel during the high gradation reset period of the subfield. The method of claim 1, The scan driver includes a first scan driver board and a second scan driver board, The scan driver A scan pulse generated from the first scan driver board is supplied to the panel in the odd-numbered address period of the subfield, And a scan pulse generated from the second scan driver board to the panel in the even address period of the subfield. The method of claim 1, The plurality of scan driver boards, the first sustain driver board, and the second sustain driver board are electrically connected to the same driver board, respectively, and supply a predetermined pulse to the panel.

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