KR100646215B1 - Plasma display device and method of driving the same - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof that can improve reliability and reduce power consumption and cost.

In the plasma display device according to the present invention, scan electrode lines and sustain electrode lines are formed, and the first common electrode line and the sustain are connected in common with a first sustain electrode line group positioned in an upper region of the sustain electrode lines. A plasma display panel including an upper plate on which a second common electrode line is commonly connected to a second sustain electrode line group positioned in a lower region of the electrode lines, and a lower plate on which address electrode lines are formed; A Y-Z integrated board for generating reset pulses and scan pulses to be supplied to the scan electrode lines, and commonly generating sustain pulses to be supplied to the scan electrode lines and the sustain electrode lines; A data driver board for generating data pulses to be supplied to the address electrode lines; And a control board for controlling the Y-Z integration board and the data driver board.

Description

Plasma display and driving method {PLASMA DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 3 is a diagram illustrating a general driving waveform for driving the plasma display panel shown in FIG. 2.

4 is a diagram illustrating a conventional plasma display device.

FIG. 5 is an equivalent view of a plasma display panel, a Y driving board, and a Z sustainer board in the plasma display device shown in FIG. 4.

6 is a diagram illustrating a plasma display device according to a first embodiment of the present invention.

FIG. 7 is a diagram illustrating the plasma display panel shown in FIG. 6.

FIG. 8 is a partial circuit diagram of the plasma display shown in FIG. 6.

FIG. 9 is a diagram illustrating a first embodiment of driving waveforms and on / off timings of switches of the plasma display device illustrated in FIG. 8.

FIG. 10 is a diagram illustrating a second embodiment of driving waveforms and on / off timings of switches of the plasma display device illustrated in FIG. 8.

FIG. 11 is a diagram illustrating a third embodiment of driving waveforms and on / off timings of switches of the plasma display device illustrated in FIG. 8.

FIG. 12 is a diagram illustrating a fourth embodiment of driving waveforms and on / off timings of switches of the plasma display device illustrated in FIG. 8.

13 illustrates a plasma display device according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating the plasma display panel shown in FIG. 13.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: Metal electrode 14: Upper dielectric layer

16: protective film 18: lower substrate

22: lower dielectric layer 24: partition wall

26 phosphor layer 30 discharge cell

32, 132, 232: top plate 34, 134, 234: bottom plate

36, 136, 236: PDP 38, 138, 238: heat sink

40: Y drive board 42, 142, 242: scan driver board

44: Y Sustainer Board 46: Z Sustainer Board

48, 148, 248: data driver board 50, 150, 250: control board

52, 54, 56, 58, 60, 62, 152, 154, 156, 158, 162, 172, 174, 176, 252, 254, 256, 258, 262, 272, 274, 276

64: Y pad area 66: Z pad area

70, 100, 102: scan driver 72: Y sustain circuit

74: Z sustain circuit 104: Y-Z integrated sustain circuit

140, 240: Y-Z integrated board 144, 244: Y-Z integrated sustainer board

146, 246: switch board 164, 264: second area

166, 266: first area 180, 280a, 280b: Z pad

182a, 182b, 182c, 182d, 282a, 282b, 282c, 282d: common electrode line

184, 284: Y pad 294a, 294b: connection cable

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device and a driving method thereof capable of improving reliability and reducing power consumption and cost.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell of a typical three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP has a scan electrode Y, a sustain electrode Z, an upper dielectric layer 14, and a protective layer 16 sequentially formed on the upper substrate 10. And a lower plate having an address electrode X, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed on the upper and lower substrates 18.

 Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one edge of the transparent electrodes 12Y and 12Z. (13Y, 13Z). Indium tin oxide (ITO) is generally used for the transparent electrodes 12Y and 12Z. The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) on the transparent electrodes 12Y and 12Z to reduce the voltage drop by the transparent electrodes 12Y and 12Z having high resistance.

 Wall charges generated during discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during plasma discharge and increases emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective film 16 can lower the discharge voltage applied from the outside. At this time, magnesium oxide (MgO) is normally used as the protective film 16.

 The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays generated by the gas discharge from leaking to the adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green, or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas mixed with these, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 of the PDP having such a structure is selected as counter discharge by the address electrode Y and the scan electrode Y, and then sustains the discharge by surface discharge by the scan electrode Y and the sustain electrode Z. do. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

2 is a view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 2, the discharge cells 30 are formed at the intersections of the scan electrode lines Y1 to Yn, the sustain electrode lines Z, and the address electrode lines X1 to Xm.

The scan electrode lines Y1 to Yn supply scan pulses to scan the discharge cells 30 line by line, and supply sustain pulses to maintain the sustain discharges generated in the discharge cells 30. The sustain electrode lines Z commonly supply a sustain pulse to maintain the sustain discharge generated in the discharge cells 30 together with the scan electrode lines Y1 to Yn. The address electrode lines X1 to Xm supply the data pulses synchronized with the scan pulses in line units to select the discharge cells 30 in which discharges are to be maintained according to the logic value of the data pulses.

Such a driving method of the PDP is an ADS (Address and Display Separation) driving method which is driven separately by an address period and a display period, that is, a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. In this case, while the reset period and the address period of each subfield are the same for each subfield, the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Increase to give different weights. Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

 FIG. 3 is a diagram illustrating a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 among a plurality of subfields.

Referring to FIG. 3, each of the subfields SF includes a reset period RP for initializing the discharge cell 30 of the full screen, an address period AP for selecting the discharge cell 30, and a selected discharge cell ( 30 is divided into the sustain period SP for maintaining the discharge.

In the reset period RP, during the setup period SU, the rising ramp waveform PR rising at a predetermined slope from the sustain voltage Vs to the peak voltage Vs + Vsetup is simultaneously applied to all the scan electrodes Y. Is approved. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. In the set-down period SD, a falling ramp waveform (falling from the positive sustain voltage Vs lower than the peak voltage Vs + Vsetup of the rising ramp waveform PR to the negative scan voltage (-Vy)) NR) is applied to all scan electrodes Y simultaneously. This falling ramp waveform (NR) causes weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly retaining wall charges required for the address discharges in the full screen cells. Let's go.

In the address period AP, the negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and the positive data pulse DP is applied to the address electrodes X. do. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain voltage Vs is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, sustain pulses SUSPy and SUSPz are applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is added between the scan electrode Y and the sustain electrode Z whenever the sustain pulses SUSPy and SUSPz are applied while the wall voltage and the sustain pulses SUSPy in the cell are added. Sustain discharge occurs in the form of surface discharge. Here, the sustain pulses SUSPy and SUSPz have the same voltage value as the sustain voltage Vs.

4 is a diagram illustrating a conventional plasma display device.

Referring to FIG. 4, the conventional plasma display device includes a PDP 36 for displaying an image, a heat sink 38 provided on the back of the PDP 36, a Y drive board 40 provided on the back of the heat sink 38, Z sustainer board 46, data driver board 48 and control board 50.

The PDP 36 has a structure in which the upper plate 32 and the lower plate 34 are joined while providing a gas discharge space. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z are formed in parallel on the upper plate 32, and address electrode lines X1 to Xm are formed on the lower plate 34. do. In addition, a Y pad region 64 is formed at one side of the upper plate 32 to form Y pads (not shown) connected to the scan electrode lines Y1 to Yn, and a Z pad region 66 is formed at the other side. ) Are formed to form Z pads (not shown) connected to the sustain electrode lines Z. In addition, an X pad region (not shown) is formed at one side of the lower plate 34 to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 32 and the lower plate 34 are bonded to expose the Y pad region 64, the Z pad region 66, and the X pad region (not shown).

The heat sink 38 is installed so as to overlap with the rear surface of the PDP 36 as a whole, and serves to release heat generated from the PDP 36.

The Y driving board 40 generates a scan driver board 42 for generating reset pulses PR and NR and a scan pulse SCNP, and a sustain voltage Vs and a Y sustain pulse SUSPy shown in FIG. The Y sustainer board 44 is comprised. The scan driver board 42 supplies the reset pulses PR and NR and the scan pulse SCNP to the scan electrodes Y1 to Yn of the PDP 36 via the Y conductive path 52. The Y sustainer board 44 has a sustain voltage Vs and a Y sustain pulse suspy at the scan electrodes Y1 to Yn of the PDP 36 via the scan driver board 42 and the Y conductive path 52. To supply. To this end, the scan driver board 42 includes a scan driver for generating reset pulses PR and NR and a scan pulse SCNP, and the Y sustain board 44 includes a sustain voltage Vs and a Y sustain pulse. Y sustain circuit that generates SUSPy).

The Z sustain board 46 generates the sustain voltage Vs and the Z sustain pulse SUSPz shown in FIG. 3, and the sustain voltage Vs and the Z sustain pulse SUSPz via the Z conductive path 54. Is supplied to the common sustain electrodes Z of the PDP 36. To this end, the Z sustainer board 46 includes a Z sustain circuit for generating a sustain voltage Vs and a Z sustain pulse SUSPz.

The data driver board 48 generates the data pulse DP shown in FIG. 3, and supplies the data pulse DP to the address electrodes X1 to Xm via the X conductive path 56.

The control board 50 generates X, Y, and Z timing control signals, respectively. The control board 50 supplies the Y timing control signal to the Y driving board 40 via the first conductive path 58 and the Z timing control signal Z via the second conductive path 60. The X timing control signal is supplied to the data driver board 48 via the third conductive path 62. That is, the control board 50 controls the data driver board 48, the Y driving board 40, and the Z sustainer board 46 by using X, Y, and Z timing control signals, respectively.

Here, each of the conductive paths 52, 54, 56, 58, 60, and 62 is one of a flexible flat cable or a flexible printed cable.

FIG. 5 is an equivalent view of a PDP, a Y driving board, and a Z sustainer board in the plasma display shown in FIG. 4.

Referring to FIG. 5, the conventional plasma display device is configured to supply reset pulses PR and NR and scan pulses SCNP to the panel capacitor Cp and the scan electrodes Y1 to Yn of the panel capacitor Cp. The scan driver 70, the Y sustain circuit 72 for supplying the Y sustain pulse SUSPy to the scan electrodes Y1 to Yn of the panel capacitor Cp, and the sustain electrodes Z of the panel capacitor Cp. And a Z sustain circuit 74 for supplying Z sustain pulses (SUSPz).

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP 36. The panel capacitor Cp generates sustain discharge by sustain pulses SUSPy and SUSPz having opposite polarities.

The scan driver 70 simultaneously supplies the reset pulses PR and NR to all the scan electrodes Y1 to Yn during the reset period RP, and scans the scan electrodes Y1 to Yn during the address period AP. The pulses SCNP are supplied sequentially.

The Y sustain circuit 72 supplies the sustain voltage Vs to the scan electrodes Y1 to Yn during the reset period RP, and the Y sustain pulses to the scan electrodes Y1 to Yn during the sustain period SP. SUSPy).

The Z sustain circuit 74 supplies the sustain voltage Vs to the sustain electrodes Z during the set down period SD and the address period AP, and the Y sustain to the sustain electrodes Z during the sustain period SP. The Z sustain pulse SUSPz is alternately supplied with the pulse SUSPy.

 In the plasma display device, when the resolution of the PDP 36 is increased or the size of the PDP 36 is increased, the capacitance of the PDP 36 is increased. The current will increase. As a result, in the conventional plasma display, a heat generation problem and a reliability problem of the circuit occur. In addition, in the conventional plasma display device, reset pulses PR and NR formed of high positive voltages Vs and Vsetup and negative voltages -Vy are applied to the scan electrodes Y1 to Yn. do. Accordingly, in the conventional plasma display device, since the additional switch elements Path_B and Path_T are added between the switch element or the driving circuit having a high breakdown voltage to control the voltage difference between the two voltages, the cost of the plasma display device increases. there is a problem.

Accordingly, an object of the present invention is to provide a plasma display device and a driving method thereof which can improve reliability.

In addition, another object of the present invention is to provide a plasma display device and a driving method thereof capable of reducing power consumption and cost.

In order to achieve the above object, a plasma display device according to the present invention includes scan electrode lines and sustain electrode lines formed thereon, and are connected in common with a first sustain electrode line group positioned in an upper region of the sustain electrode lines. A plasma display panel including an upper plate on which a common electrode line and a second common electrode line commonly connected to a second sustain electrode line group positioned in a lower region of the sustain electrode lines are formed, and a lower plate on which address electrode lines are formed; A Y-Z integrated board for generating reset pulses and scan pulses to be supplied to the scan electrode lines, and commonly generating sustain pulses to be supplied to the scan electrode lines and the sustain electrode lines; A data driver board for generating data pulses to be supplied to the address electrode lines; And a control board for controlling the Y-Z integration board and the data driver board.

A first Y pad is formed at one side of the upper plate to be connected to a first scan electrode line group positioned in an upper region of the scan electrode lines, and a second scan electrode line positioned in a lower region of the scan electrode lines. And a second Y pad connected to the group.

A third common electrode line connected to the first common electrode line and a first Z pad connected to the third common electrode line are formed at an upper side of the upper plate, and the second common electrode line is formed at a lower side of the upper plate. And a fourth common electrode line connected to the second common electrode line and a second Z pad connected to the fourth common electrode line.

A third common electrode line for supplying a sustain pulse to the first common electrode line and a first Z pad connected to the third common electrode line are formed at an upper portion of the lower plate, and the lower portion of the lower plate is formed at the lower portion of the lower plate. A fourth common electrode line and a second Z pad for supplying a sustain pulse to the second common electrode line are formed.

The first common electrode line is connected to the third common electrode line by a first connecting cable, and the second common electrode line is connected to the fourth common electrode line by a second connecting cable.

The first connection cable and the second connection cable is any one of a flexible flat cable and a flexible printed cable.

The Y-Z integrated board may include: a scan driver board generating reset pulses and scan pulses to be supplied to the first scan electrode line group and the second scan electrode line group; A Y-Z integrated sustainer board which commonly generates sustain pulses to be supplied to the first scan electrode line group and the second scan electrode line group and the first sustain electrode line group and the second sustain electrode line group; And a switch board for supplying sustain pulses supplied from the YZ integrated sustainer board to the first scan electrode line group and the second sustain electrode line group, the second scan electrode line group, and the first sustain electrode line group. .

The scan driver board may include a first scan driver for supplying a reset pulse and a scan pulse to the first scan electrode line group; And a second scan driver for supplying a reset pulse and a scan pulse to the second scan electrode line group.

The YZ integrated sustainer board may include a YZ integrated sustain circuit for supplying a sustain pulse to the first scan electrode line group and the second scan electrode line group, the first scan electrode line group, and the second sustain electrode line group in common. Include.

The switch board includes: a first switch connected between the Y-Z integrated sustain circuit and the first scan driver to simultaneously supply the sustain pulses to the first scan electrode line group and the second sustain electrode line group; And a second switch connected between the Y-Z integrated sustain circuit and the second scan driver to simultaneously supply the sustain pulses to the second scan electrode line group and the first sustain electrode line group.

The first switch is turned on when an odd number of sustain pulses is supplied to the first scan electrode line group and the second sustain electrode line group, and the second switch is an even number of sustain pulses. Is turned on when supplied to the second scan electrode line group and the first sustain electrode line group.

The first switch is turned on when the even-numbered sustain pulses of the sustain pulses are supplied to the first scan electrode line group and the second sustain electrode line group, and the second switch is the odd-numbered sustain pulses of the sustain pulses. Is turned on when supplied to the second scan electrode line group and the first sustain electrode line group.

The first and second switches may be turned on only during a period of 1/2 in which the sustain pulse maintains the sustain voltage level.

The first and second switches are turned on for one period in which the sustain pulse maintains the sustain voltage level and the base voltage level.

The first to fourth common electrode lines may be formed in the non-display area of the upper plate.

The plasma display device according to the present invention includes a first Y conductive path and a second Y conductive path connected between the first Y pad and the second Y pad and one side of the scan driver board, respectively; A first Z pad and a second Z conductive path connected between the first Z pad and the second Z pad and one side portion and the other side portion of the switch board, respectively; A first conductive path connected between the Y-Z integrated sustainer board and one side of the control board; A second conductive path connected between one side of the data driver board and a lower side of the control board; A third conductive path connected between one side of the switch board and an upper side of the control board; And an X conductive path connected between the other side of the data driver board and the X pad region provided in the lower side of the upper plate.

The conductive path may be any one of a flexible flat cable and a flexible printed cable.

A driving method of a plasma display device according to an embodiment of the present invention is a driving method of a plasma display device which is divided into a reset period, an address period and a sustain period, wherein the scan electrode lines and the sustain electrode lines formed in the panel during the sustain period. A first scan electrode line group positioned in an upper region of the panel, a first sustain electrode line group positioned in a lower region of the panel, a second scan electrode line group positioned in a lower region of the panel, and an upper region of the panel And alternately supplying sustain pulses to a second group of sustain electrode lines positioned at.

The sustain pulse may be supplied to the first scan electrode line group and the first sustain electrode line group and then supplied to the second scan electrode line group and the second sustain electrode line group.

The sustain pulse may be supplied to the second scan electrode line group and the second sustain electrode line group, and then supplied to the first scan electrode line group and the first sustain electrode line group.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 14.

6 is a diagram illustrating a plasma display device according to a first embodiment of the present invention, and FIG. 7 is a diagram illustrating a PDP shown in FIG. 6.

6 and 7, a plasma display device according to a first embodiment of the present invention includes a plasma display panel (PDP) 136 and a PDP 136 for displaying an image. It includes a heat sink 138 installed on the back of the, YZ integrated board 140, a data driver board 148 and the control board 150 installed on the back of the heat sink 138.

As illustrated in FIG. 7, the PDP 136 has a structure in which the upper plate 132 and the lower plate 134 are bonded while providing a gas discharge space. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z1 to Zn are formed in parallel on the upper plate 132, and address electrode lines X1 to Xm are formed on the lower plate 134. In addition, a first region 166 is formed at one side of the upper plate 132 which is a non-display region, and is connected to the sustain electrode lines Z1 to Zn / 2 formed in the upper region 190 of the PDP 136. A second common electrode line 182b is formed in common with the first common electrode line 182a and the sustain electrode lines Zn / 2 + 1 to Zn formed in the lower region 192 of the PDP 136. Here, the upper region 190 and the lower region 192 of the PDP 136 do not mean that the display region is divided into upper and lower portions, but rather, the display region is divided into upper and lower portions by a spatial concept. In addition, a third common electrode line 182c connected to the first common electrode line 182a is formed at an upper side of the upper plate 132 that is a non-display area, and a lower portion of the upper plate 132 that is a non-display area is formed. A fourth common electrode line 182d is formed to be connected to the second common electrode line 182b. In addition, a second region 164 is provided at the other side of the upper plate 132, which is a non-display region, so that the Y pads 184 connected to the scan electrodes Y1 to Yn, and the third and fourth common electrode lines ( Z pads 180 connected to 182c and 182d are formed. In addition, an X pad region (not shown) is provided at one side of the lower plate 134 to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 132 and the lower plate 134 are bonded to expose the first region 166, the second region 164, and the X pad region (not shown).

The heat sink 138 is installed to overlap with the rear surface of the PDP 136 as a whole to radiate heat generated from the PDP 136 to the outside.

The YZ integrated board 140 generates a scan driver board 142 for generating reset pulses PR and NR and a scan pulse SCNP, a sustain voltage Vs and a ground voltage GND shown in FIG. It consists of an integrated sustainer board 144 and a scan driver board 142 and a switch board 146 for connecting the YZ integrated sustainer board 144.

In response to the Y timing control signal supplied from the control board 150, the scan driver board 142 may reset pulses PR and NR to be supplied to the scan electrodes Y1 to Yn in the reset period RP as shown in FIG. 3. And a scan pulse SCNP to be supplied to the scan electrodes Y1 to Yn during the address period AP. The scan driver board 142 scans the reset pulses PR and NR and scans the scan electrodes Y1 to Yn of the PDP 136 via the Y conductive paths 152 and 154 and the Y pads 184. Supply a pulse (SCNP). In this case, the first Y conductive path 152 is connected to the first Y pad group 184a connected to the scan electrodes Y1 to Yn / 2 formed in the upper region 190 of the PDP 136, and the second The Y conductive path 154 is connected to the second Y pad group 184b connected to the scan electrodes Yn / 2 + 1 to Yn formed in the lower region 192 of the PDP 136. Here, the first and second Y conductive paths 152 and 154 may use one conductive path. The first scan driver board 142 includes a scan driver (not shown) that generates reset pulses PR and NR and scan pulses SCNP.

The YZ integrated sustainer board 144 may scan the scan electrodes Y1 to Yn and the sustain electrodes in the sustain period SP as shown in FIG. 3 in response to the Y and YZ integrated timing control signals supplied from the control board 150. Z1 to Zn) generate sustain pulses (SUSP) to be supplied. The YZ integrated sustainer board 144 is configured to scan electrodes Y1 to Yn via the switch board 146, the scan driver board 142, the Y conductive paths 152 and 154, and the Y pads 184. The sustain electrodes may be supplied through the switch board 146, the Z conductive paths 172 and 174, the Z pads 180, and the third and fourth common electrode lines 182c and 182d. Sustain pulses SUSP are supplied to the sustain electrode lines Z1 to Zn by supplying the first and second common electrode lines 182a and 182b which are connected to Z1 to Zn in common. At this time, the sustain pulse SSUS includes the scan electrodes Y1 to Yn / 2 formed in the upper region 190 of the PDP 136 and the sustain electrodes Zn / 2 formed in the lower region 192 of the PDP 136. +1 to Zn) at the same time. In addition, the sustain pulse SSUS includes scan electrodes Yn / 2 + 1 to Yn formed in the lower region 192 of the PDP 136 and sustain electrodes Z1 formed in the upper region 190 of the PDP 136. To Zn / 2) at the same time. Such a Y-Z integrated sustainer board 144 includes a Y-Z integrated sustain circuit (not shown) for generating a sustain pulse (SUSP).

The switch board 146 scans the sustain pulses SUSP supplied from the YZ integrated sustainer board 144 in response to a switch control signal supplied from the control board 150 to scan electrodes Y1 to Yn and the sustain electrodes (S). Z1 to Zn). That is, the switch board 146 includes scan electrodes formed in the upper region 190 of the PDP 136 via the scan driver board 142, the first Y conductive path 152, and the first Y pad group 184a. Sustain pulse (SUSP) is supplied to (Y1 to Yn / 2). At the same time, the switch board 146 is connected to the PDP 136 via the second Z conductive path 174 and the second Z pad 180b, the fourth common electrode line 182d, and the second common electrode line 182b. The sustain pulse SSUS is supplied to the sustain electrodes Zn / 2 + 1 to Zn formed in the lower region 192 of the substrate. In addition, the switch board 146 may include scan electrodes formed in the lower region 192 of the PDP 136 via the scan driver board 142, the second Y conductive path 154, and the second Y pad group 184b. It is supplied to (Yn / 2 + 1 to Yn). At the same time, the switch board 146 is connected to the PDP 136 via the first Z conductive path 172 and the first Z pad 180a, the third common electrode line 182c, and the first common electrode line 182a. The sustain pulse SSUS is supplied to the sustain electrodes Z1 to Zn / 2 formed in the upper region 190 of the substrate. Such a switch board 146 includes a plurality of switch elements (not shown). In this case, the switch board 146 may be formed of one board with the Y-Z integrated board 140.

In response to the X timing control signal supplied from the control board 150, the data driver board 148 generates a data pulse DP to be supplied to the address electrode lines X1 to Xm in the address period AP as shown in FIG. 3. Is generated and supplied to the address electrode lines X1 to Xm of the PDP 136 via the X conductive path 156. Here, the X conductive path 156 is connected to an X pad region (not shown) provided in the lower portion of the data driver board 148 and the upper plate 132.

The control board 150 controls Y and YZ integrated timing control signals for controlling the YZ integration board 140, X timing control signals for controlling the data driver board 148, and switch control for controlling the switch board 144. Generate a signal. The control board 150 supplies the Y and YZ integrated timing control signals to the YZ integrated board 140 via the first conductive path 158 and the X timing control signals via the second conductive path 162. Is supplied to the data driver board 148 and the switch control signal is supplied to the switch board 144 via the third conductive path 176.

 In this case, each of the conductive paths 152, 154, 156, 158, 162, 172, 174, and 176 may use one of a flexible flat cable and a flexible printed cable.

FIG. 8 is a partial circuit diagram of the plasma display shown in FIG. 6.

Referring to FIG. 8, in the plasma display device according to an exemplary embodiment, scan electrode lines Y1 to Yn of the first and second panel capacitors CP1 and CP2 and the first and second panel capacitors Cp are provided. And the scan electrode lines Y1 to Yn of the YZ integrated sustain circuit 104 and the first and second panel capacitors Cp1 and Cp2 for supplying the sustain pulse SSUS to the sustain electrode lines Z1 to Zn. First and second scan drivers 102 for supplying reset pulses PR, NR and scan pulses SCNP to the sustain voltage Vs and ground voltage GND from the YZ integrated sustain circuit 104, respectively. And second switches SW1 and SW2 for selectively supplying to the scan electrode lines Y1 to Yn and the sustain electrode lines Z1 to Zn of the first and second panel capacitors Cp1 and Cp2. It includes.

The first panel capacitor Cp1 is equivalent to the capacitance formed between the first scan electrode line group YG1 and the first sustain electrode line group ZG1 formed in the upper region 190 of the full surface of the PDP 136. It is shown as. Here, the first scan electrode line group YG1 refers to the scan electrodes Y1 to Yn / 2 formed in the upper region 190 of the PDP 136, and the first sustain electrode line group ZG1 refers to the PDP ( The sustain electrodes Z1 to Zn / 2 formed in the upper region of the capacitor 136 are represented. The first panel capacitor Cp1 may be a group of the first scan electrode line group YG1 and the first sustain electrode line group from the YZ integrated sustain circuit 104 according to the switching operation of the first and second switches SW1 and SW2. Sustain discharge is generated by the sustain pulse SUSP alternately supplied to (ZG1).

The second panel capacitor Cp2 is equivalent to the capacitance formed between the second scan electrode line group YG2 and the second sustain electrode line group ZG2 formed in the lower region 192 of the full surface of the PDP 136. It is shown as. Here, the second scan electrode line group YG2 refers to scan electrodes Yn / 2 + 1 to Yn formed in the lower region 192 of the PDP 136, and the second sustain electrode line group ZG1 is It refers to the sustain electrodes Zn / 2 + 1 to Zn formed in the lower region of the PDP 136. The second panel capacitor Cp2 is connected to the second scan electrode line group YG2 and the second sustain electrode line group from the YZ integrated sustain circuit 104 according to the switching operations of the first and second switches SW1 and SW2. Sustain discharge is generated by the sustain pulse SUSP alternately supplied to (ZG2).

The first scan driver 100 is connected between the first switch SW1 and the second sustain electrode line group ZG2 and the first scan electrode line group YG1. The first scan driver 100 supplies the reset pulses PR and NR to the first scan electrode line group YG1 during the reset period RP and the first scan electrode line group during the address period AP. YG1) is sequentially supplied with scan pulses (SCNP).

The second scan driver 102 is connected between the second switch SW2 and the first sustain electrode line group ZG1 and the second scan electrode line group YG2. The second scan driver 102 supplies the reset pulses PR and NR to the second scan electrode line group YG2 simultaneously with the first scan driver 100 during the reset period RP and the address period AP. Scan pulse SCNP is sequentially supplied to the second scan electrode line group YG2. In this case, the scan pulse SCNP supplied to the second scan electrode line group YG2 is supplied after the scan pulse SCNP is supplied to the first scan electrode line group YG1. That is, the second scan driver 102 supplies the scan pulse SCNP to the first scan electrode line group YG1 after the first scan driver 100 supplies the scan pulse to the second scan electrode line group YG2. SCNP).

The Y-Z integrated sustain circuit 104 generates a sustain voltage Vs and a ground voltage GND in response to the Y-Z integrated timing control signal supplied from the control board 150. The YZ integrated sustain circuit 104 supplies the sustain voltage Vs to the first and second scan electrode line groups YG1 and YG2 during the reset period RP, and the sustain voltage Vs during the sustain period AP. ) And a plurality of sustain pulses SSUS formed at the ground voltage GND level are supplied to the first and second scan electrode line groups YG1 and YG2 and the first and second sustain electrode line groups ZG1 and ZG2. .

The first switch SW1 is connected between the YZ integrated sustain circuit 104 and the first scan driver 100 and the second sustain electrode line group ZG2, and according to a switch control signal supplied from the control board 150, the YZ is connected to the first switch SW1. The sustain voltage Vs and the ground voltage GND supplied from the integrated sustain circuit 104 are supplied to the first scan electrode line group YG1 and the second sustain electrode line group ZG2.

The second switch SW2 is connected between the YZ integrated sustain circuit 104 and the second scan driver 102 and the first sustain electrode line group ZG1 to supply the YZ according to a switch control signal supplied from the control board 150. The sustain voltage Vs and the ground voltage GND supplied from the integrated sustain circuit 104 are supplied to the second scan electrode line group YG2 and the first sustain electrode line group ZG1. The second switch SW2 is alternately operated with the first switch SW1.

9 is a diagram illustrating a first embodiment of driving waveforms and on / off timings of switches of a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 9, the YZ integrated sustain circuit 104 generates a plurality of sustain pulses (SUSP) having a sustain voltage (Vs) and a ground voltage (GND) level according to a Y timing control signal supplied from the control board 150. Occurs. At this time, the first switch SW1 is turned on when the odd-numbered sustain pulses SUSP_odd of the plurality of sustain pulses SSUS are supplied, and the second switch SW2 is supplied with the even-numbered sustain pulses SUSP_even. When it is turned on. The first and second switches SW1 and SW2 are turned on only while the sustain pulse SUSP maintains the sustain voltage level Vs, that is, during the 1/2 cycle of the sustain pulse SUSP. Accordingly, odd-numbered sustain pulses SUSP_odd are supplied to the first scan electrode line group YG1 and the second sustain electrode line group ZG2, and even-numbered sustain pulses SUSP_even are supplied to the second scan electrode line group YG2. And the first sustain electrode line group ZG1.

FIG. 10 is a diagram illustrating a second embodiment of driving waveforms and switches on / off timings of a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 10, the YZ integrated sustain circuit 104 generates a plurality of sustain pulses (SUSPs) having a sustain voltage (Vs) and a ground voltage (GND) level according to a Y timing control signal supplied from the control board 150. Occurs. At this time, the first switch SW1 is turned on when the odd-numbered sustain pulses SUSP_odd of the plurality of sustain pulses SSUS are supplied, and the second switch SW2 is supplied with the even-numbered sustain pulses SUSP_even. When it is turned on. The first and second switches SW1 and SW2 are turned on for one period in which the sustain pulse SSUS maintains the sustain voltage level Vs and the ground voltage level GND. Accordingly, odd-numbered sustain pulses SUSP_odd are supplied to the first scan electrode line group YG1 and the second sustain electrode line group ZG2, and even-numbered sustain pulses SUSP_even are supplied to the second scan electrode line group YG2. And the first sustain electrode line group ZG1.

FIG. 11 is a diagram illustrating a third embodiment of driving waveforms and on / off timings of switches of a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 11, the YZ integrated sustain circuit 104 includes a plurality of sustain pulses (SUSPs) having a sustain voltage (Vs) and a ground voltage (GND) level according to a Y timing control signal supplied from the control board 150. Occurs. In this case, the first switch SW1 is turned on when the even-numbered sustain pulse SSUS_even is supplied among the plurality of sustain pulses SSUS, and the second switch SW2 is supplied with the odd-numbered sustain pulse SUSP_odd. When it is turned on. The first and second switches SW1 and SW2 are turned on only while the sustain pulse SUSP maintains the sustain voltage level Vs, that is, during the 1/2 cycle of the sustain pulse SUSP. Accordingly, the odd-numbered sustain pulses SUSP_odd are supplied to the second scan electrode line group YG2 and the first sustain electrode line group ZG1, and the even-numbered sustain pulses SUSP_even are supplied to the first scan electrode line group YG1. ) And a second sustain electrode line group ZG2.

FIG. 12 is a diagram illustrating a fourth embodiment of driving waveforms and on / off timings of switches of a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 12, the YZ integrated sustain circuit 104 generates a plurality of sustain pulses (SUSP) having a sustain voltage (Vs) and a ground voltage (GND) level according to a Y timing control signal supplied from the control board 150. Occurs. In this case, the first switch SW1 is turned on when the even-numbered sustain pulse SSUS_even is supplied among the plurality of sustain pulses SSUS, and the second switch SW2 is supplied with the odd-numbered sustain pulse SUSP_odd. When it is turned on. The first and second switches SW1 and SW2 are turned on for one period in which the sustain pulse SSUS maintains the sustain voltage level Vs and the ground voltage GND. Accordingly, the odd-numbered sustain pulses SUSP_odd are supplied to the second scan electrode line group YG2 and the first sustain electrode line group ZG1, and the even-numbered sustain pulses SUSP_even are supplied to the first scan electrode line group YG1. ) And a second sustain electrode line group ZG2.

FIG. 13 is a diagram illustrating a plasma display device according to a second exemplary embodiment of the present invention, and FIG. 14 is a diagram illustrating a PDP shown in FIG. 13.

13 and 14, a plasma display device according to a second exemplary embodiment of the present invention includes a PDP 236 for displaying an image, a heat sink 238 installed on a rear surface of the PDP 236, and a heat sink 238. And a YZ integrated board 240, a data driver board 248, and a control board 250 installed on the rear surface.

The PDP 236 has a structure in which the upper plate 232 and the lower plate 234 are bonded while providing a gas discharge space, as shown in FIG. 14. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z1 to Zn are formed in parallel on the upper plate 232, and address electrode lines X1 to Xm are formed on the lower plate 234. In addition, a first region 266 may be provided at one side of the upper plate 232 of the PDP 236, which is a non-display region, to support the sustain electrode lines Z1 to Zn / 2 formed in the upper region 290 of the PDP 236. Second common electrode line 282b commonly connected to the first common electrode line 282a and the sustain electrode lines Zn / 2 + 1 to Zn formed in the lower region 292 of the PDP 236. ) Is formed. Here, the upper area 290 and the lower area 292 of the PDP 236 do not mean that the display area is divided into upper and lower parts, but rather, the display area is divided into upper and lower parts by a spatial concept. In addition, a second region 264 is provided at the other side of the upper plate 232, which is a non-display area, to form Y pads 284 connected to the scan electrodes Y1 to Yn. In addition, a first Z pad 280a and a third common electrode line 282c are formed at an upper side of the lower plate 234, which is a non-display area, and a second Z pad 280b and a lower side of the lower plate 234. A fourth common electrode line 284d is formed. An X pad region (not shown) is provided at one side of the lower plate 234 to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 232 and the lower plate 234 are bonded to expose the first region 266, the second region 264, and the X pad region (not shown).

The heat sink 238 is installed to overlap with the rear surface of the PDP 236 as a whole to radiate heat generated from the PDP 236 to the outside.

The YZ integrated board 240 generates the scan driver board 242 generating the reset pulses PR and NR and the scan pulse SCNP, the sustain voltage Vs and the ground voltage GND shown in FIG. It consists of an integrated sustainer board 244 and a scan driver board 242 and a switch board 246 for connecting the YZ integrated sustainer board 244.

In response to the Y timing control signal supplied from the control board 250, the scan driver board 242 may reset pulses PR and NR to be supplied to the scan electrodes Y1 to Yn in the reset period RP as shown in FIG. 3. And a scan pulse SCNP to be supplied to the scan electrodes Y1 to Yn during the address period AP. The scan driver board 242 scans the reset pulses PR and NR and scans the scan electrodes Y1 to Yn of the PDP 236 via the Y conductive paths 252 and 254 and the Y pads 284. Supply a pulse (SCNP). In this case, the first Y conductive path 252 is connected to the first Y pad group 284a connected to the scan electrodes Y1 to Yn / 2 formed in the upper region 290 of the PDP 236. The Y conductive path 254 is connected to the second Y pad group 284b connected to the scan electrodes Yn / 2 + 1 to Yn formed in the lower region 292 of the PDP 236. The scan driver board 242 includes a scan driver for generating reset pulses PR and NR and scan pulses SCNP.

The YZ integrated sustainer board 244 may scan the scan electrodes Y1 to Yn and the sustain electrodes in the sustain period SP as shown in FIG. 3 in response to the Y and YZ integrated timing control signals supplied from the control board 250. Z1 to Zn) generate sustain pulses (SUSP) to be supplied. The YZ integrated sustainer board 244 is configured to scan electrodes Y1 to Yn via the switch board 246, the scan driver board 242, the Y conductive paths 252 and 254, and the Y pads 284. Sustain electrodes through the switch board 246, the Z conductive paths 272 and 274, the Z pads 280a and 280b, and the third and fourth common electrode lines 282c and 282d, as well as supplying sustain pulses (SUSP). The sustain pulse SSUS is supplied to the sustain electrode lines Z1 through Zn by being supplied to the first and second common electrode lines 282a and 282b which are commonly connected to the fields Z1 through Zn. In this case, the third and fourth common electrode lines 282c and 282d and the first and second common electrode lines 282a and 282b are connected by the first and second connection cables 294a and 294b. Here, the first and second connection cables (294a, 294b) is used any one of the flexible flat cable (Flexible Flat Cable) and the flexible printed cable (Flexible Printed Cable). The sustain pulse SSUS includes the scan electrodes Y1 to Yn / 2 formed in the upper region 290 of the PDP 236 and the sustain electrodes Zn / 2 formed in the lower region 292 of the PDP 236. +1 to Zn) at the same time. In addition, the sustain pulse SSUS includes scan electrodes Yn / 2 + 1 to Yn formed in the lower region 292 of the PDP 236 and sustain electrodes Z1 formed in the upper region 290 of the PDP 236. To Zn / 2) at the same time. Such a Y-Z integrated sustainer board 244 includes a Y-Z integrated sustain circuit (not shown) for generating a sustain pulse (SUSP).

The switch board 246 scans the sustain pulse SUSP supplied from the YZ integrated sustainer board 244 in response to the switch control signal supplied from the control board 250 to scan electrodes Y1 to Yn and the sustain electrodes (S). Z1 to Zn). That is, the switch board 246 includes scan electrodes formed in the upper region 290 of the PDP 236 via the scan driver board 242, the first Y conductive path 252, and the first Y pad group 284a. Sustain pulse (SUSP) is supplied to (Y1 to Yn / 2). At the same time, the switch board 246 includes the second Z conductive path 274 and the second Z pad 280b, the fourth common electrode line 282d, the second connection cable 294b and the second common electrode line 282b. Sustain pulses SUSP are supplied to the sustain electrodes Zn / 2 + 1 to Zn formed in the lower region 292 of the PDP 236 via? The switch board 246 also includes scan electrodes formed in the lower region 292 of the PDP 236 via the scan driver board 242, the second Y conductive path 254, and the second Y pad group 284b. It is supplied to (Yn / 2 + 1 to Yn). At the same time, the switch board 246 includes the first Z conductive path 272 and the first Z pad 280a, the third common electrode line 282c, the first connection cable 294a and the first common electrode line 282a. Sustain pulses SUSP are supplied to the sustain electrodes Z1 to Zn / 2 formed in the upper region 290 of the PDP 236 via the C1). The switch board 246 may be formed of one board with the Y-Z integrated board 240.

The data driver board 248 may be supplied to the address electrode lines X1 to Xm in the address period AP as shown in FIG. 3 in response to the X timing control signal supplied from the control board 250. Is generated and supplied to the address electrode lines X1 to Xm of the PDP 236 via the X conductive path 256. Here, the X conductive path 256 is connected to an X pad region (not shown) provided under the data driver board 248 and the upper plate 232.

The control board 250 includes Y and Z timing control signals for controlling the YZ integrated board 240, X timing control signals for controlling the data driver board 248, and switch control signals for controlling the switch board 244. Occurs. The control board 250 supplies the Y and Z timing control signals to the YZ integrated board 240 via the first conductive path 258 and the X timing control signals via the second conductive path 262. The data driver board 248 is supplied, and a switch control signal is supplied to the switch board 244 via the third conductive path 276.

 In this case, each of the conductive paths 252, 254, 256, 258, 262, 272, 274, and 276 may use one of a flexible flat cable and a flexible printed cable.

The plasma display device according to the second embodiment of the present invention has the same equivalent circuit as that of the plasma display device according to the first embodiment of the present invention. Accordingly, the driving method of the plasma display device according to the second embodiment of the present invention is also the same as the driving method of the plasma display device according to the first embodiment of the present invention. Therefore, a detailed description of the plasma display device according to the second embodiment of the present invention will be replaced with the details described with reference to FIGS. 8 to 12.

As described above, the plasma display device and the driving method thereof according to the present invention can reduce the number of logic and driving switches of the circuit by integrating a sustain circuit for supplying sustain pulses to the scan electrodes and the sustain electrodes during the sustain period. Not only can the cost of the device be reduced, but the sustain circuit is composed of a single board, thereby improving the space utilization of the plasma display device. In addition, since the PDP is divided up and down, the load applied to the PDP during sustain driving, that is, the capacitance of the PDP can be reduced, thereby reducing power consumption and loss, thereby improving reliability. In addition, since the PDP is divided up and down, the interference due to the phase difference between the scan electrode and the sustain electrode and the electromagnetic interference (EMI) can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

Scan electrode lines and sustain electrode lines are formed, and the first common electrode line and the first common electrode line commonly connected to the first sustain electrode line group positioned in an upper region of the sustain electrode lines are positioned in a lower region of the sustain electrode lines. A plasma display panel including an upper plate on which a second common electrode line is commonly connected to the second sustain electrode line group, and a lower plate on which address electrode lines are formed; A Y-Z integrated board for generating reset pulses and scan pulses to be supplied to the scan electrode lines, and commonly generating sustain pulses to be supplied to the scan electrode lines and the sustain electrode lines; A data driver board for generating data pulses to be supplied to the address electrode lines; And And a control board for controlling the Y-Z integrated board and the data driver board. The method of claim 1, A first Y pad is formed at one side of the upper plate to be connected to a first scan electrode line group positioned in an upper region of the scan electrode lines, and a second scan electrode line positioned in a lower region of the scan electrode lines. And a second Y pad connected to the group. The method of claim 2, A third common electrode line connected to the first common electrode line and a first Z pad connected to the third common electrode line are formed at an upper side of the upper plate, and the second common electrode line is formed at a lower side of the upper plate. And a fourth common electrode line connected to the second common electrode line and a second Z pad connected to the fourth common electrode line. The method of claim 2, A third common electrode line for supplying a sustain pulse to the first common electrode line and a first Z pad connected to the third common electrode line are formed at an upper portion of the lower plate, and the lower portion of the lower plate is formed at the lower portion of the lower plate. And a fourth common electrode line and a second Z pad for supplying a sustain pulse to the common electrode line. The method of claim 4, wherein The first common electrode line is connected to the third common electrode line by a first connecting cable, and the second common electrode line is connected to the fourth common electrode line by a second connecting cable. Display. The method of claim 5, And the first connection cable and the second connection cable are any one of a flexible flat cable and a flexible printed cable. The method according to claim 3 or 6, wherein The Y-Z integrated board, A scan driver board generating reset pulses and scan pulses to be supplied to the first scan electrode line group and the second scan electrode line group; A Y-Z integrated sustainer board which commonly generates sustain pulses to be supplied to the first scan electrode line group and the second scan electrode line group and the first sustain electrode line group and the second sustain electrode line group; And And a switch board for supplying sustain pulses supplied from the YZ integrated sustainer board to the first scan electrode line group, the second sustain electrode line group, the second scan electrode line group, and the first sustain electrode line group. Plasma display device characterized in that. The method of claim 7, wherein The scan driver board, A first scan driver for supplying a reset pulse and a scan pulse to the first scan electrode line group; And And a second scan driver for supplying a reset pulse and a scan pulse to the second scan electrode line group. The method of claim 8, The YZ integrated sustainer board may include a YZ integrated sustain circuit for supplying a sustain pulse to the first scan electrode line group and the second scan electrode line group, the first scan electrode line group, and the second sustain electrode line group in common. Plasma display device comprising a. The method of claim 9, The switch board, A first switch connected between the Y-Z integrated sustain circuit and the first scan driver to simultaneously supply the sustain pulses to the first scan electrode line group and the second sustain electrode line group; And And a second switch connected between the YZ integrated sustain circuit and the second scan driver to simultaneously supply the sustain pulses to the second scan electrode line group and the first sustain electrode line group. Device. The method of claim 10, The first switch is turned on when an odd number of sustain pulses is supplied to the first scan electrode line group and the second sustain electrode line group, and the second switch is an even number of sustain pulses. Is turned on when is supplied to the second scan electrode line group and the first sustain electrode line group. The method of claim 10, The first switch is turned on when the even-numbered sustain pulses of the sustain pulses are supplied to the first scan electrode line group and the second sustain electrode line group, and the second switch is the odd-numbered sustain pulses of the sustain pulses. Is turned on when is supplied to the second scan electrode line group and the first sustain electrode line group. The method according to claim 11 or 12, And the first and second switches are turned on only during a period of 1/2 where the sustain pulse maintains a sustain voltage level. The method according to claim 11 or 12, And the first and second switches are turned on for one period in which the sustain pulse maintains the sustain voltage level and the ground voltage level. The method according to claim 3 or 6, wherein And the first to fourth common electrode lines are formed in a non-display area of the upper plate. The method of claim 7, wherein First and second Y conductive paths connected between the first and second Y pads and one side of the scan driver board, respectively; A first Z pad and a second Z conductive path connected between the first Z pad and the second Z pad and one side portion and the other side portion of the switch board, respectively; A first conductive path connected between the Y-Z integrated sustainer board and one side of the control board; A second conductive path connected between one side of the data driver board and a lower side of the control board; A third conductive path connected between one side of the switch board and an upper side of the control board; And And an X conductive path connected between the other side of the data driver board and the X pad area provided at the lower side of the upper plate. The method of claim 16, And wherein the conductive path is any one of a flexible flat cable and a flexible printed cable. A driving method of a plasma display device which is driven divided into a reset period, an address period and a sustain period, The first scan electrode line group positioned in the upper region of the panel and the first sustain electrode line group positioned in the lower region of the panel and the panel among the scan electrode lines and the sustain electrode lines formed in the panel during the sustain period; And alternately supplying sustain pulses to a second scan electrode line group located in a lower region of the second scan electrode line group and a second sustain electrode line group located in an upper region of the panel. . The method of claim 18, And the sustain pulse is supplied to the first scan electrode line group and the first sustain electrode line group and then to the second scan electrode line group and the second sustain electrode line group. The method of claim 18, And the sustain pulses are supplied to the second scan electrode line group and the second sustain electrode line group, and then supplied to the first scan electrode line group and the first sustain electrode line group.

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