KR100680708B1 - Plasma display device and method of driving the same - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof that can improve reliability and reduce power consumption and cost.

In the plasma display device according to the present invention, scan electrode lines and sustain electrode lines are formed, and first common electrode lines commonly connected to the sustain electrode lines are formed on one side thereof, and the other scan electrode lines are formed on the other side thereof. A plasma display panel including an upper plate having a Y pad connected thereto and a lower plate having address electrode lines formed thereon; A Y-Z integrated board generating reset pulses and scan pulses and supplying them to the scan electrode lines, and generating sustain pulses in common to alternately supply the sustain pulses to the scan electrode lines and the sustain electrode lines; A data driver board supplying data to the address electrode lines; And a control board controlling the Y-Z integrated mode and the data driver board.

Description

Plasma display and driving method {PLASMA DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 3 is a diagram illustrating a general driving waveform for driving the plasma display panel shown in FIG. 2.

4 is a diagram illustrating a conventional plasma display device.

FIG. 5 is an equivalent view of a plasma display panel, a Y driving board, and a Z sustainer board in the plasma display device shown in FIG. 4.

6 is a diagram illustrating a plasma display device according to a first embodiment of the present invention.

FIG. 7 is a diagram illustrating the plasma display panel shown in FIG. 6.

FIG. 8 is a partial circuit diagram of the plasma display shown in FIG. 6.

FIG. 9 is a diagram illustrating a first embodiment of on / off timing of the switch illustrated in FIG. 8.

FIG. 10 is a diagram illustrating a second embodiment of on / off timing of the switch illustrated in FIG. 8.

11 is a diagram illustrating a plasma display device according to a second embodiment of the present invention.

FIG. 12 is a diagram illustrating the plasma display panel shown in FIG. 11.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: Metal electrode 14: Upper dielectric layer

16: protective film 18: lower substrate

22: lower dielectric layer 24: partition wall

26 phosphor layer 30 discharge cell

32, 132, 232: top plate 34, 134, 234: bottom plate

36, 136, 236: PDP 38, 138, 238: heat sink

40: Y drive board 42, 142, 242: scan driver board

44: Y Sustainer Board 46: Z Sustainer Board

48, 148, 248: data driver board 50, 150, 250: control board

52, 54, 56, 58, 60, 62, 152, 156, 158, 162, 174, 176, 252, 256, 258, 262, 274, 276

64: Y pad area 66: Z pad area

70, 100, 102: scan driver 72: Y sustain circuit

74: Z sustain circuit 104: Y-Z integrated sustain circuit

106: switch circuit 140, 240: Y-Z integrated board

144, 244: Y-Z integrated sustainer board 146, 246: switch board

164 and 264: second region 166 and 266: first region

180, 280: Z pad 184, 284: Y pad

182a, 182b, 182c, 282a, 282b, 282c: common electrode line

294a, 294b: connection cable

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device and a method of driving the same, which can reduce costs and improve reliability.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. Displays an image containing graphics. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell of a typical three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP has a scan electrode Y, a sustain electrode Z, an upper dielectric layer 14, and a protective layer 16 sequentially formed on the upper substrate 10. And a lower plate having an address electrode X, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed on the upper and lower substrates 18.

 Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one edge of the transparent electrodes 12Y and 12Z. (13Y, 13Z). Indium tin oxide (ITO) is generally used for the transparent electrodes 12Y and 12Z. The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) on the transparent electrodes 12Y and 12Z to reduce the voltage drop by the transparent electrodes 12Y and 12Z having high resistance.

 Wall charges generated during discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during plasma discharge and increases emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 can lower the discharge voltage applied from the outside. At this time, magnesium oxide (MgO) is normally used as the protective film 16.

 The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays generated by the gas discharge from leaking to the adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green, or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas mixed with these, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 of the PDP having such a structure is selected as counter discharge by the address electrode Y and the scan electrode Y, and then sustains the discharge by surface discharge by the scan electrode Y and the sustain electrode Z. do. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

2 is a view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 2, the discharge cells 30 are formed at the intersections of the scan electrode lines Y1 to Yn, the sustain electrode lines Z, and the address electrode lines X1 to Xm.

The scan electrode lines Y1 to Yn supply scan pulses to scan the discharge cells 30 line by line, and supply sustain pulses to maintain the sustain discharges generated in the discharge cells 30. The sustain electrode lines Z commonly supply a sustain pulse to maintain the sustain discharge generated in the discharge cells 30 together with the scan electrode lines Y1 to Yn. The address electrode lines X1 to Xm supply data pulses synchronized with scan pulses in line units to select discharge cells 30 in which discharges are to be maintained according to logic values of the data pulses.

Such a driving method of the PDP is an ADS (Address and Display Separation) driving method which is driven separately by an address period and a display period, that is, a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. In this case, while the reset period and the address period of each subfield are the same for each subfield, the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Increase to give different weights. Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

 FIG. 3 is a diagram illustrating a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 among a plurality of subfields.

Referring to FIG. 3, each of the subfields SF includes a reset period RP for initializing the discharge cell 30 of the full screen, an address period AP for selecting the discharge cell 30, and a selected discharge cell ( 30 is divided into the sustain period SP for maintaining the discharge.

In the reset period RP, during the setup period SU, the rising ramp waveform PR rising from the sustain voltage Vs to the peak voltage Vs + Vsetup at a predetermined slope in all the scan electrode lines Y is applied. It is applied at the same time. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. In the set-down period SD, a falling ramp waveform (falling from the positive sustain voltage Vs lower than the peak voltage Vs + Vsetup of the rising ramp waveform PR to the negative scan voltage (-Vy)) NR) is applied to all scan electrode lines Y at the same time. This falling ramp waveform (NR) causes weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly retaining wall charges required for the address discharges in the full screen cells. Let's go.

In the address period AP, a negative scan pulse SCNP is sequentially applied to the scan electrode lines Y, and a positive data pulse DP is applied to the address electrodes X. Is approved. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

Meanwhile, a positive sustain voltage Vs is applied to the sustain electrode lines Z during the set down period SD and the address period AP.

In the sustain period SP, sustain pulses SUSP and SUSP are applied to the scan electrode lines Y and the sustain electrode lines Z alternately. Then, in the cell selected by the address discharge, the wall voltage and the sustain pulses SUSP and SUSP are added between the scan electrode Y and the sustain electrode Z every time the sustain pulses SUSP and SUSP are applied. Sustain discharge occurs in the form of surface discharge. Here, the sustain pulses SUSP and SUSP have the same voltage value as the sustain voltage Vs.

4 is a diagram illustrating a conventional plasma display device.

Referring to FIG. 4, the conventional plasma display device includes a PDP 36 for displaying an image, a heat sink 38 provided on the back of the PDP 36, a Y drive board 40 provided on the back of the heat sink 38, Z sustainer board 46, data driver board 48 and control board 50.

The PDP 36 has a structure in which the upper plate 32 and the lower plate 34 are joined while providing a gas discharge space. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z are formed in parallel on the upper plate 32, and address electrode lines X1 to Xm are formed on the lower plate 34. do. In addition, a Y pad region 64 is formed at one side of the upper plate 32 to form Y pads (not shown) connected to the scan electrode lines Y1 to Yn, and a Z pad region 66 is formed at the other side. ) Are formed to form Z pads (not shown) connected to the sustain electrode lines Z. In addition, an X pad region (not shown) is formed at one side of the lower plate 34 to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 32 and the lower plate 34 are bonded to expose the Y pad region 64, the Z pad region 66, and the X pad region (not shown).

The heat sink 38 is installed so as to overlap with the rear surface of the PDP 36 as a whole to serve to release heat generated from the PDP 36.

The Y driving board 40 includes a scan driver board 42 for generating reset pulses PR and NR and a scan pulse SCNP as shown in FIG. 3, and a Y for generating sustain voltage Vs and sustain pulses SSUS. It is composed of a sustainer board 44. The scan driver board 42 supplies the reset pulses PR and NR and the scan pulse SCNP to the scan electrode lines Y1 to Yn of the PDP 36 via the Y conductive path 52. The Y sustainer board 44 maintains the sustain voltage Vs and the sustain pulse SSUS at the scan electrode lines Y1 to Yn of the PDP 36 via the scan driver board 42 and the Y conductive path 52. To supply. To this end, the scan driver board 42 includes a scan driver for generating reset pulses PR and NR and a scan pulse SCNP, and the Y sustain board 44 includes a sustain voltage Vs and a Y sustain pulse. Y sustain circuit for generating SUSP).

The Z sustainer board 46 generates the sustain voltage Vs and the sustain pulses SUSP shown in FIG. 3, and PDP the sustain voltage Vs and the sustain pulses SUSP via the Z conductive path 54. The common sustain electrode lines Z of 36 are supplied. To this end, the Z sustain board 46 includes a Z sustain circuit for generating a sustain voltage Vs and a sustain pulse SSUS.

The data driver board 48 generates the data pulse DP shown in FIG. 3, and supplies the data pulse DP to the address electrodes X1 to Xm via the X conductive path 56.

The control board 50 generates X, Y, and Z timing control signals, respectively. The control board 50 supplies the Y timing control signal to the Y driving board 40 via the first conductive path 58, and transmits the Z timing control signal to the Z sus via the second conductive path 60. It supplies to the retainer board 46, and supplies an X timing control signal to the data driver board 48 via the 3rd conductive path 62. As shown in FIG. That is, the control board 50 controls the data driver board 48, the Y drive board 40, and the Z sustainer board 46 by using X, Y, and Z timing control signals, respectively.

Here, each of the conductive paths 52, 54, 56, 58, 60, and 62 is one of a flexible flat cable or a flexible printed cable.

FIG. 5 is an equivalent view of a PDP, a Y driving board, and a Z sustainer board in the plasma display shown in FIG. 4.

Referring to FIG. 5, a conventional plasma display device includes a panel capacitor Cp, a scan driver 70, a Y sustain circuit 72, and a Z sustain circuit 74.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP 36. The panel capacitor Cp generates sustain discharge by sustain pulses SUSP and SUSP having opposite polarities.

The scan driver 70 simultaneously supplies the reset pulses PR and NR to all the scan electrode lines Y1 to Yn during the reset period RP, and also scan electrode lines Y1 to Yn during the address period AP. Scan pulses (SCNP) are supplied sequentially.

The Y sustain circuit 72 supplies the sustain voltage Vs to the scan electrode lines Y1 to Yn in the reset period RP, and sustain pulses in the scan electrode lines Y1 to Yn during the sustain period SP. Supply (SUSP).

The Z sustain circuit 74 supplies the sustain voltage Vs to the sustain electrode lines Z during the set down period SD and the address period AP, and also sustains the sustain electrode lines Z during the sustain period SP. Sustain pulses (SUSP) are alternately supplied to the sustain pulses (SUSP).

However, such a conventional plasma display device has a Y sustain circuit 72 and a Z sustain circuit (S) for supplying sustain pulses (SUSP) having the same size to the scan electrode lines (Y) and the sustain electrode lines (Z), respectively. Since 74) is separately configured, there is a problem in that the cost of the entire circuit increases and the configuration increases. In addition, when the plasma display device is driven, a lot of electromagnetic interference (hereinafter referred to as “EMI”) is generated due to the interference caused by the phase difference between the electrodes Y and Z, thereby reducing reliability.

Accordingly, an object of the present invention is to provide a plasma display device and a method of driving the same, which can reduce costs and improve reliability.

In order to achieve the above object, in the plasma display device according to the present invention, scan electrode lines and sustain electrode lines are formed, and first common electrode lines commonly connected to the sustain electrode lines are formed at one side thereof, and A plasma display panel including a top plate on which a Y pad is connected to the scan electrode lines and a bottom plate on which address electrode lines are formed; A Y-Z integrated board generating reset pulses and scan pulses and supplying them to the scan electrode lines, and generating sustain pulses in common to alternately supply the sustain pulses to the scan electrode lines and the sustain electrode lines; A data driver board supplying data to the address electrode lines; And a control board controlling the Y-Z integrated mode and the data driver board.

The Y-Z integrated board includes a scan driver board including a scan driver for generating the reset pulse and the scan pulse; A Y-Z integrated sustainer board having a Y-Z integrated sustain circuit for generating the sustain pulses; And a switch board having a switch circuit for alternately supplying the sustain pulses to the scan electrode lines and the sustain electrode lines.

The switch circuit includes a first switch connected between the Y-Z integrated sustain circuit and the scan driver; And a second switch connected between the Y-Z integrated sustain circuit and the sustain electrode lines.

The first switch is turned on when an odd number of sustain pulses are supplied, and the second switch is turned on when an even number of sustain pulses is supplied.

The first switch and the second switch is characterized in that the sustain pulse is turned on for 1/2 cycle to maintain the sustain voltage level.

The first switch and the second switch are characterized in that the sustain pulse is turned on for one period to maintain the sustain voltage level and the base voltage level.

A second common electrode line is formed at an upper side of the upper plate to be connected to one side of the first common electrode line, and a third common electrode line is connected to the other side of the first common electrode line at a lower side of the upper plate. And a Z pad connected to the second common electrode line and the third common electrode line on the other side of the upper plate.

The first to third common electrode lines may be formed in the non-display area of the upper plate.

A second common electrode line is formed on one side of the first common electrode line at an upper side of the lower plate, and a sustain pulse is formed on the other side of the first common electrode line at a lower side of the lower plate. A third common electrode line for supplying is formed, and a Z pad connected to each of the second common electrode line and the third common electrode line is formed at one side of the lower plate.

The second common electrode line is connected to one side of the first common electrode line by a first connecting cable, and the third common electrode line is connected to the other side of the first common electrode line by a second connecting cable. It is characterized by.

The first connection cable and the second connection cable is any one of a flexible flat cable and a flexible printed cable.

According to the present invention, a plasma display device includes: a Y conductive path connected between the Y pad and the scan driver board; A Z conductive path connected between the Z pad and the switch board; A first conductive path connected between the Y-Z integrated sustainer board and one side of the control board; A second conductive path connected between one side of the data driver board and a lower side of the control board; A third conductive path connected between one side of the switch board and an upper side of the control board; And an X conductive path connected between the other side of the data driver board and the X pad region provided in the lower side of the upper plate.

The conductive path may be any one of a flexible flat cable and a flexible printed cable.

A driving method of a plasma display device according to the present invention includes a driving method divided into a reset period, an address period, and a sustain period, the method comprising: generating a plurality of sustain pulses during the sustain period; Supplying odd-numbered sustain pulses of the plurality of sustain pulses to scan electrode lines of a plasma display panel; And supplying an even number of the sustain pulses to the sustain electrode lines of the plasma display panel.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 12.

6 is a diagram illustrating a plasma display device according to a first embodiment of the present invention, and FIG. 7 is a diagram illustrating a PDP shown in FIG. 6.

6 and 7, the plasma display device according to the first embodiment of the present invention is a plasma display panel (PDP) 136 for displaying an image, and a PDP 136. It includes a heat sink 138 installed on the back of the, YZ integrated board 140, a data driver board 148 and the control board 150 installed on the back of the heat sink 138.

As illustrated in FIG. 7, the PDP 136 has a structure in which the upper plate 132 and the lower plate 134 are bonded while providing a gas discharge space. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z are formed in parallel on the upper plate 132, and address electrode lines X1 to Xm are formed on the lower plate 134. In this case, a first region 166 is formed in the non-display area of one side of the upper plate 132 to form a first common electrode line 182a commonly connected to the sustain electrode lines Z, and the upper side of the upper plate 132. The second common electrode line 182b connected to one side of the first common electrode line 132 is formed in the negative non-display area, and the second common electrode line 182b is formed in the non-display area under the upper plate 132 of the first common electrode line 132. The third common electrode line 182c is formed to be connected to the other side. In addition, a second region 164 is provided in the non-display area of the other side of the upper plate 132 so that the Y pads 184 and the second common electrode line 182b connected to the scan electrode lines Y1 to Yn, and Z pads 180 connected to the third common electrode line 182c are formed. In addition, an X pad region (not shown) is provided at one side of the lower plate 134 to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 132 and the lower plate 134 are bonded to expose the first region 166, the second region 164, and the X pad region (not shown).

The heat sink 138 is installed to overlap with the rear surface of the PDP 136 as a whole to discharge heat generated from the PDP 136 to the outside.

The YZ integrated board 140 generates the reset pulses PR and NR and scan pulses Supp shown in FIG. 3, supplies them to the scan electrode lines Y, and generates sustain pulses Supp. The electrode lines SUP are selectively supplied to the scan electrode lines Y and the sustain electrode lines Z. The YZ integrated board 140 may include a scan driver board 142 generating reset pulses PR and NR and scan pulses SCNP, a sustain pulse having a sustain voltage level Vs and a ground voltage level GND. And a switch board 146 for connecting the YZ integrated sustainer board 144 and the scan driver board 142 and the YZ integrated sustainer board 144 generating SUSP.

The scan driver board 142 generates reset pulses PR and NR to be supplied to the scan electrode lines Y1 to Yn in the reset period RP in response to the Y timing control signal supplied from the control board 150. In addition, the scan pulse SCNP is generated to be supplied to the scan electrode lines Y1 to Yn during the address period AP. In addition, the scan driver board 142 may reset pulses PR and NR and scan pulses to the scan electrode lines Y1 to Yn of the PDP 136 via the Y conductive path 152 and the Y pads 184. (SCNP) is supplied. The first scan driver board 142 includes a scan driver (not shown) that generates reset pulses PR and NR and scan pulses SCNP.

The YZ integrated sustainer board 144 may scan the scan electrode lines Y1 to Yn and the sustain electrode line in the sustain period SP as shown in FIG. 3 in response to the Y and YZ integrated timing control signals supplied from the control board 150. Sustain pulse SUSP is generated to be supplied to field Z. The YZ integrated sustainer board 144 is connected to the scan electrode lines Y1 to Yn via the switch board 146, the scan driver board 142, the Y conductive path 152, and the Y pads 184. Supply Sustain Pulse (SUSP). In addition, the YZ integrated sustainer board 144 may include a switch board 146, a Z conductive path 174, Z pads 180, a second common electrode line 182b, a third common electrode line 182c, and a first common electrode line 182c. 1 The sustain pulse SUSP is supplied to the sustain electrode lines Z through the common electrode line 182a. This, Y-Z integrated sustainer board 144 includes a Y-Z integrated sustain circuit (not shown) for generating a common sustain pulse (SUSP).

The switch board 146 scans the sustain pulse SUSP supplied from the YZ integrated sustainer board 144 in response to the switch control signal supplied from the control board 150 to scan electrode lines Y1 to Yn and the sustain electrode line. It is selectively supplied to field Z. That is, the switch board 146 may scan the scan electrode lines Y1 via the scan driver board 142, the Y conductive path 152, and the Y pad 184 in response to the switch control signal supplied from the control board 150. To Yn). In addition, the switch board 142 may include a Z conductive path 174, a Z pad 180, a second common electrode line 182b, and a third common electrode line in response to a switch control signal supplied from the control board 150. The sustain pulse SSUS is supplied to the sustain electrode lines Z through 182c and the first common electrode line 182a. At this time, the switch board 146 supplies odd-numbered sustain pulses to the scan electrode lines Y1 to Yn among the plurality of sustain pulses SUSP supplied from the YZ integrated sustainer board 144, and supplies even-numbered sustain pulses. Supply to the sustain electrode lines (Z). Accordingly, the sustain pulse SSUS is alternately supplied to the scan electrode lines Y1 to Yn and the sustain electrode lines Z. FIG. The switch board 146 includes a switch circuit (not shown) for alternately supplying the sustain pulse SUSP to the scan electrode lines Y1 to Yn and the sustain electrode lines Z.

In response to the X timing control signal supplied from the control board 150, the data driver board 148 generates a data pulse DP to be supplied to the address electrode lines X1 to Xm in the address period AP as shown in FIG. 3. Is generated and supplied to the address electrode lines X1 to Xm of the PDP 136 via the X conductive path 156. Here, the X conductive path 156 is connected to an X pad region (not shown) provided under the data driver board 148 and the upper plate 132.

The control board 150 controls the Y timing control signal and the YZ integrated timing control signal for controlling the YZ integrated sustainer board 144, the X timing control signal and the switch board 144 for controlling the data driver board 148. Generates a switch control signal for controlling. The control board 150 supplies the Y timing control signal and the YZ integrated timing control signal to the YZ integrated sustainer board 144 via the first conductive path 158 and passes through the second conductive path 162. The X timing control signal is supplied to the data driver board 148, and the switch control signal is supplied to the switch board 144 via the third conductive path 176.

In this case, each of the conductive paths 152, 156, 158, 162, 174, and 176 may use one of a flexible flat cable and a flexible printed cable.

FIG. 8 is a partial circuit diagram of the plasma display shown in FIG. 6.

Referring to FIG. 8, a plasma display device according to an exemplary embodiment of the present invention applies reset pulses PR and NR and scan pulses SCNP to a panel capacitor Cp and a scan electrode line Y of the panel capacitor Cp. YZ integrated sustain circuit 104 and YZ integrated sustain circuit for supplying sustain pulse (SUSP) to scan driver 100 for supplying, scan electrode line Y of panel capacitor Cp and sustain electrode line Z And a switch circuit 106 for alternately supplying the sustain pulse SSUS supplied from the 104 to the scan electrode line Y and the sustain electrode line Z. Here, the scan driver 100 is installed on the scan driver board 142, the YZ integrated sustain circuit 104 is installed on the YZ integrated sustainer board 144, and the switch circuit 106 is mounted on the switch board 146. Is installed.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode line Y and the sustain electrode line Z formed in the PDP 136. The panel capacitor Cp is connected to the scan electrode line Y and the sustain from the YZ integrated sustain circuit 104 according to the switching operation of the first switch SW1 and the second switch SW2 included in the switch circuit 106. The sustain discharge is generated by the sustain pulse SUSP alternately supplied to the electrode line Z.

The scan driver 100 is connected to the scan electrode line Y of the panel capacitor Cp, and the scan electrode line during the reset period RP as shown in FIG. 3 in response to the Y timing control signal supplied from the control board 150. The reset pulses PR and NR are supplied to (Y), and the scan pulses SCNP are sequentially supplied to the scan electrode line Y during the address period AP.

The YZ integrated sustain circuit 104 includes a plurality of sustain pulses having a sustain voltage level Vs and a ground voltage level GND during the sustain period SP in response to the YZ integrated timing control signal supplied from the control board 150. SUSP).

The switch circuit 106 is connected between the YZ integrated sustain circuit 104 and the scan driver 100 and the sustain electrode line Z, and in accordance with a switch control signal supplied from the control board 150, the YZ integrated sustain circuit 104. Sustain pulses SupP generated from the &lt; RTI ID = 0.0 &gt;) are selectively supplied to the scan electrode line Y and the sustain electrode line Z. To this end, the switch circuit 106 is connected between the first switch SW1 connected between the YZ integrated sustain circuit 104 and the scan driver 100 and between the YZ integrated sustain circuit 104 and the sustain electrode line Z. 2nd switch SW2.

The first switch SW1 is connected between the YZ integrated sustain circuit 104 and the scan driver 100 and is supplied with the sustain voltage level supplied from the YZ integrated sustain circuit 104 in accordance with a switch control signal supplied from the control board 150. A sustain pulse SSUS having Vs and a ground voltage level GND is supplied to the scan electrode line Y. The first switch SW1 supplies the odd-numbered sustain pulses SUSP to the scan electrode line Y among the plurality of sustain pulses SUSP generated from the Y-Z integrated sustain circuit 104. That is, the first switch SW1 is turned on when the odd-numbered sustain pulse SSUS is supplied from the Y-Z integrated sustain circuit 104. Detailed description thereof will be described later.

The second switch SW2 is connected between the YZ integrated sustain circuit 104 and the sustain electrode line Z, and the sustain voltage supplied from the YZ integrated sustain circuit 104 according to the switch control signal supplied from the control board 150. A sustain pulse SSUS having a level Vs and a ground voltage level GND is supplied to the sustain electrode line Z. The second switch SW2 supplies the even-numbered sustain pulse SSUS to the sustain electrode line Z among the plurality of sustain pulses SSP generated from the Y-Z integrated sustain circuit 104. That is, the second switch SW2 is turned on when the even-numbered sustain pulse SUSP is supplied from the Y-Z integrated sustain circuit 104. Detailed description thereof will be described later.

FIG. 9 is a diagram illustrating a first embodiment of on / off timing of the switch illustrated in FIG. 8.

Referring to FIG. 9, the YZ integrated sustain circuit 104 has a sustain voltage level Vs and a ground voltage level GND during the sustain period SP according to the YZ integrated timing control signal supplied from the control board 150. Generates a number of sustain pulses (SUSP). In this case, the first switch SW1 is turned on when the odd-numbered sustain pulse SSUS_odd is supplied among the plurality of sustain pulses SSUS, and the second switch SW2 is supplied with the even-numbered sustain pulse SUSP_even. When it is turned on. The first switch SW1 and the second switch SW2 are turned on only while the sustain pulse SSUS maintains the sustain voltage level Vs, that is, during the 1/2 cycle of the sustain pulse SSUS. . Accordingly, odd-numbered sustain pulses SUSP_odd are supplied to the scan electrode line Y, and even-numbered sustain pulses SUSP_even are supplied to the sustain electrode line Z.

FIG. 10 is a diagram illustrating a second embodiment of on / off timing of the switch illustrated in FIG. 8.

Referring to FIG. 10, the YZ integrated sustain circuit 104 has a sustain voltage level Vs and a ground voltage level GND during the sustain period SP according to the YZ integrated timing control signal supplied from the control board 150. Generates a number of sustain pulses (SUSP). At this time, the first switch SW1 is turned on when the odd-numbered sustain pulses SUSP_odd of the plurality of sustain pulses SSUS are supplied, and the second switch SW2 is supplied with the even-numbered sustain pulses SUSP_even. When it is turned on. The first switch SW1 and the second switch SW2 are turned on for one period in which the sustain pulse SSUS maintains the sustain voltage level Vs and the ground voltage level GND. Accordingly, odd-numbered sustain pulses SUSP_odd are supplied to the scan electrode line Y, and even-numbered sustain pulses SUSP_even are supplied to the sustain electrode line Z.

FIG. 11 is a diagram illustrating a plasma display device according to a second exemplary embodiment of the present invention, and FIG. 12 is a diagram illustrating a PDP shown in FIG. 11.

11 and 12, a plasma display device according to a second exemplary embodiment of the present invention includes a PDP 236 for displaying an image, a heat sink 238 installed on a rear surface of the PDP 236, and a heat sink 238. And a YZ integrated board 240, a data driver board 248, and a control board 250 installed on the rear surface.

As illustrated in FIG. 12, the PDP 236 has a structure in which the upper plate 232 and the lower plate 234 are bonded while providing a gas discharge space. Here, scan electrode lines Y1 to Yn and sustain electrode lines Z are formed in parallel on the upper plate 232, and address electrode lines X1 to Xm are formed on the lower plate 234. In this case, a first region 266 is formed in the non-display area of one side of the upper plate 232 to form a first common electrode line 282a connected to the sustain electrode lines Z in common. In the non-display area of the side portion, Y pads 284 having second regions 264 connected to the scan electrode lines Y1 to Yn are formed in the non-display area of the upper and lower portions of the lower plate 234. The second common electrode line 282b and the third common electrode line 282c for supplying the sustain voltage Vs and the sustain pulse SSUS to the common electrode line 282a are formed, and one of the lower plates 234 is formed. Z pads 280 connected to the second common electrode line 282b and the third common electrode line 282c are formed on the side portion, where the second common electrode line 282b is formed of the first connection cable 294a. Is connected to one side of the first common electrode line 282a, and the third common electrode line 282c is called the first common electrode by the second connection cable 294b. It is connected to the other side of the phosphor 282a, where the first connecting cable 294a and the second connecting cable 294b are any one of a flexible flat cable and a flexible printed cable. One side of the lower plate 234 is provided with an X pad region (not shown) to form X pads (not shown) connected to the address electrode lines X1 to Xm. The upper plate 232 and the lower plate 234 are bonded to expose the first region 266, the second region 264, and the X pad region (not shown).

The heat sink 238 is installed to overlap with the rear surface of the PDP 236 as a whole to radiate heat generated from the PDP 236 to the outside.

The YZ integrated board 240 generates the reset pulses PR and NR and scan pulses Supp shown in FIG. 3, supplies them to the scan electrode lines Y, and generates sustain pulses Supp. The electrode lines SUP are selectively supplied to the scan electrode lines Y and the sustain electrode lines Z. The YZ integrated board 240 includes a scan driver board 242 for generating reset pulses PR and NR and a scan pulse SCNP, a sustain pulse having a sustain voltage level Vs and a ground voltage level GND. And a switch board 246 for connecting the YZ integrated sustainer board 244 and the scan driver board 242 and the YZ integrated sustainer board 244 that generate the SUSP.

The scan driver board 242 generates reset pulses PR and NR to be supplied to the scan electrode lines Y1 to Yn in the reset period RP in response to the Y timing control signal supplied from the control board 250. In addition, the scan pulse SCNP is generated to be supplied to the scan electrode lines Y1 to Yn during the address period AP. In addition, the scan driver board 142 may reset pulses PR and NR and scan pulses to the scan electrode lines Y1 to Yn of the PDP 236 via the Y conductive path 252 and the Y pads 284. (SCNP) is supplied. The first scan driver board 242 includes a scan driver (not shown) for generating reset pulses PR and NR and scan pulses SCNP.

The YZ integrated sustainer board 244 has the scan electrode lines Y1 to Yn and the sustain electrode lines in the sustain period SP as shown in FIG. 3 in response to the YZ integrated timing control signal supplied from the control board 250. It generates a sustain pulse (SUSP) to be supplied to Z). The YZ integrated sustainer board 244 is connected to the scan electrode lines Y1 to Yn via the switch board 246, the scan driver board 242, the Y conductive path 252, and the Y pads 284. Supply Sustain Pulse (SUSP). In addition, the YZ integrated sustainer board 244 is formed through the switch board 246, the Z conductive path 274, the Z pads 280, the second common electrode line 282b, and the first connection cable 292a. 1 supplies a sustain pulse (SUSP) to one side of the common electrode line 282a, the switch board 246, the Z conductive path 274, the Z pads 280, the third common electrode line 282c and The sustain pulse SSUS is supplied to the other side of the first common electrode line 282a through the two connection cables 292b. Accordingly, the sustain pulse SSUS supplied to the first common electrode line 282a commonly connected to the sustain electrode lines Z is supplied to the sustain electrode lines Z. This, Y-Z integrated sustainer board 244 includes a Y-Z integrated sustain circuit (not shown) for generating a common sustain pulse (SUSP).

The switch board 246 scans the sustain pulse SUSP supplied from the YZ integrated sustainer board 244 in response to the switch control signal supplied from the control board 250 to scan electrode lines Y1 to Yn and the sustain electrode line. It is selectively supplied to field Z. That is, the switch board 246 may scan the scan electrode lines Y1 via the scan driver board 242, the Y conductive path 252, and the Y pad 284 in response to a switch control signal supplied from the control board 250. To Yn). The switch board 242 also includes a Z conductive path 274, a Z pad 280, a second common electrode line 282b, and a first connection cable 292a in response to a switch control signal supplied from the control board 150. Supplies a sustain pulse (SUSP) to one side of the first common electrode line 282a, and switches the switch board 246, the Z conductive path 274, the Z pads 280, and the third common electrode line The sustain pulse SSUS is supplied to the other side of the first common electrode line 282a through the 282c and the second connection cable 292b. Accordingly, the sustain pulse SSUS supplied to the first common electrode line 282a commonly connected to the sustain electrode lines Z is supplied to the sustain electrode lines Z. At this time, the switch board 246 supplies odd-numbered sustain pulses to the scan electrode lines Y1 to Yn among the plurality of sustain pulses SUSP supplied from the YZ integrated sustainer board 244, and supplies even-numbered sustain pulses. Supply to the sustain electrode lines (Z). Accordingly, sustain pulses SUSP are alternately supplied to the scan electrode lines Y1 to Yn and the sustain electrode lines Z. The switch board 246 includes a switch circuit (not shown) for alternately supplying the sustain pulse SSUS to the scan electrode lines Y1 to Yn and the sustain electrode lines Z.

The data driver board 248 supplies the data pulse DP to be supplied to the address electrode lines X1 to Xm in the address period AP as shown in FIG. 3 in response to the X timing control signal supplied from the control board 250. Is generated and supplied to the address electrode lines X1 to Xm of the PDP 236 via the X conductive path 256. Here, the X conductive path 256 is connected to an X pad region (not shown) provided under the data driver board 248 and the upper plate 232.

The control board 250 includes a Y timing control signal and a YZ integrated timing control signal for controlling the YZ integrated sustainer board 244, an X timing control signal and a switch board 244 for controlling the data driver board 248. Generates a switch control signal for controlling. The control board 250 supplies the Y timing control signal and the YZ integrated timing control signal to the YZ integrated sustainer board 244 via the first conductive path 258, and passes through the second conductive path 262. The X timing control signal is supplied to the data driver board 248, and the switch control signal is supplied to the switch board 244 via the third conductive path 276.

In this case, each of the conductive paths 252, 256, 258, 262, 274, and 276 may use any one of a flexible flat cable and a flexible printed cable.

The plasma display device according to the second embodiment of the present invention has the same equivalent circuit as that of the plasma display device according to the first embodiment of the present invention. Accordingly, the driving method of the plasma display device according to the second embodiment of the present invention is also the same as the driving method of the plasma display device according to the first embodiment of the present invention. Therefore, a detailed description of the plasma display device according to the second embodiment of the present invention will be replaced with the details described with reference to FIGS. 8 to 10.

As described above, the plasma display device and the driving method thereof according to the present invention can reduce the number of logic and driving switches of the circuit by integrating a sustain circuit for supplying sustain pulses to the scan electrodes and the sustain electrodes during the sustain period. Not only can the cost of the device be reduced, but the sustain circuit is composed of a single board, thereby improving the space utilization of the plasma display device. In addition, since the integrated sustain circuit drives the scan electrode lines and the sustain electrode lines, the interference and the EMI caused by the phase difference between the two electrodes can be reduced, and the reliability can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

The top plate having scan electrode lines and sustain electrode lines formed thereon and first common electrode lines commonly connected to the sustain electrode lines on one side thereof, and a Y pad connected to the scan electrode lines on the other side thereof. And a plasma display panel including a lower plate on which address electrode lines are formed; A Y-Z integrated board generating reset pulses and scan pulses and supplying them to the scan electrode lines, and generating sustain pulses in common to alternately supply the sustain pulses to the scan electrode lines and the sustain electrode lines; A data driver board supplying data to the address electrode lines; And And a control board for controlling the Y-Z integrated mode and the data driver board. The method of claim 1, The Y-Z integrated board, A scan driver board including a scan driver for generating the reset pulse and the scan pulse; A Y-Z integrated sustainer board having a Y-Z integrated sustain circuit for generating the sustain pulses; And And a switch board having a switch circuit for alternately supplying the sustain pulses to the scan electrode lines and the sustain electrode lines. The method of claim 2, The switch circuit, A first switch connected between the Y-Z integrated sustain circuit and the scan driver; And And a second switch connected between the Y-Z integrated sustain circuit and the sustain electrode lines. The method of claim 3, wherein Wherein the first switch is turned on when an odd number of sustain pulses is supplied, and the second switch is turned on when an even number of sustain pulses is supplied. . The method of claim 4, wherein And the first switch and the second switch are turned on for a period of 1/2 during which the sustain pulse maintains a sustain voltage level. The method of claim 4, wherein And the first switch and the second switch are turned on for one period in which the sustain pulse maintains the sustain voltage level and the ground voltage level. The method of claim 2, A second common electrode line is formed at an upper side of the upper plate and connected to one side of the first common electrode line, and a third common electrode line is connected to the other side of the first common electrode line at a lower side of the upper plate. And a Z pad connected to the second common electrode line and the third common electrode line on the other side of the upper plate. The method of claim 7, wherein And the first to third common electrode lines are formed in a non-display area of the upper plate. The method of claim 2, A second common electrode line is formed on one side of the first common electrode line at an upper side of the lower plate, and a sustain pulse is formed on the other side of the first common electrode line at a lower side of the lower plate. And a third common electrode line for supplying, and a Z pad connected to the second common electrode line and the third common electrode line on one side of the lower plate. The method of claim 9, The second common electrode line is connected to one side of the first common electrode line by a first connecting cable, and the third common electrode line is connected to the other side of the first common electrode line by a second connecting cable. Plasma display device characterized in that. The method of claim 10, And the first connection cable and the second connection cable are any one of a flexible flat cable and a flexible printed cable. The method according to claim 8 or 11, A Y conductive path connected between the Y pad and the scan driver board; A Z conductive path connected between the Z pad and the switch board; A first conductive path connected between the Y-Z integrated sustainer board and one side of the control board; A second conductive path connected between one side of the data driver board and a lower side of the control board; A third conductive path connected between one side of the switch board and an upper side of the control board; And And an X conductive path connected between the other side of the data driver board and the X pad area provided at the lower side of the upper plate. The method of claim 12, And wherein the conductive path is any one of a flexible flat cable and a flexible printed cable. A driving method of a plasma display device which is driven divided into a reset period, an address period and a sustain period, Generating a plurality of sustain pulses during the sustain period; Supplying odd-numbered sustain pulses of the plurality of sustain pulses to scan electrode lines of a plasma display panel; And supplying even-numbered sustain pulses from the plurality of sustain pulses to sustain electrode lines of the plasma display panel.

Images