KR100607512B1 - Plasma Display Panel And Module thereof - Google Patents

Abstract

The present invention relates to a plasma display panel module for integrating a sustainer board and reducing electromagnetic interference.

A plasma display panel module according to an embodiment of the present invention includes scan electrode lines, sustain electrode lines, and data electrode lines, and includes a first pad connected to the scan electrode lines and a second electrode connected to the sustain electrode lines. A plasma display panel having pads formed at one side thereof; An integrated driving board for driving the scan electrode lines and the sustain electrode lines; A conductive path connected between one side of the integrated driving board and the first and second pads, the integrated driving board comprising: a scan driver board generating a scan pulse to be supplied to the scan electrode lines; And an integrated sustain board for generating a first sustain pulse to be supplied to the scan electrode lines and a second sustain pulse to be supplied to the sustain electrode lines.

Description

Plasma display panel and module thereof             

1 is a perspective view showing a discharge cell of a conventional three-electrode alternating current plasma display panel.

2 is an overall electrode layout of a typical plasma display panel.

FIG. 3 is a driving waveform diagram of the plasma display panel shown in FIG. 2.

4 is a diagram illustrating a rear structure of a conventional plasma display panel module.

5 is a cross-sectional view of the plasma display panel module in FIG.

6 illustrates a rear structure of a plasma display panel module according to a first embodiment of the present invention.

FIG. 7 is a sectional view of the plasma display panel module shown in FIG. 6; FIG.

FIG. 8 is a cross-sectional view illustrating in detail the output signal path of the Y-Z integrated board shown in FIG.

9 illustrates a rear structure of the plasma display panel module according to the second embodiment of the present invention.

10 is a cross-sectional view of the plasma display panel module shown in FIG.

FIG. 11 is a view showing an electrode structure formed on the plasma display panel of the plasma display panel module shown in FIG. 9; FIG.

12 is a view showing a cable used in the electrode structure of the plasma display panel shown in FIG.

FIG. 13 is a view showing another electrode structure formed on the plasma display panel of the plasma display panel module shown in FIG. 9; FIG.

14 is a view showing a cable used in the electrode structure of the plasma display panel shown in FIG.

FIG. 15 is a view showing a problem in the electrode structure of the plasma display panel shown in FIG. 13; FIG.

FIG. 16 is a view showing another type of electrode structure in which the electrode structure of the plasma display panel shown in FIG. 13 is improved.

<Brief description of symbols for the main parts of the drawings>

10: upper substrate 18: lower substrate

12A: Scanning electrode 12B: Sustaining electrode

14 upper dielectric layer 16 protective film

20: data electrode 22: lower dielectric layer

24: partition 26: phosphor

30: discharge cell 40, 70, 170: PDP

42, 72, 172: control board 44, 73, 173: scan driver board

45: Y drive board 46: Y sustainer board

48: Z sustainer board 50, 80, 180: data driver board

51, 52, 54, 56, 58, 60, 76, 78, 82, 84, 88, 176, 178, 182, 188: FPC

61, 90, 190: upper plate 62, 92, 192: lower plate

64, 86, 186: heat sink 74, 174: Y-Z sustainer board

75, 175: connector 100, 200: Y-Z integrated board

94, 96: Y and Z pad area 194: Y / Z pad area

194a: Y pad 194b: Z pad

195: black matrix

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel and a module thereof, and more particularly, to a plasma display panel and a module thereof, which integrate an sustainer board and reduce electromagnetic interference.

Recently, plasma display panels (hereinafter referred to as PDPs), which are easy to manufacture large panels, have attracted attention as flat panel display devices. The PDP typically displays an image by adjusting the gas discharge period of each of the pixels in accordance with digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is an enlarged view of one discharge cell constituting a conventional AC PDP.

The discharge cell 30 shown in FIG. 1 includes an upper plate having sustain electrode pairs 12A and 12B, an upper dielectric layer 14 and a protective film 16 sequentially formed on the upper substrate 10, and a lower substrate 18. A lower plate having a data electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed thereon is provided.

Each of the sustain electrode pairs 12A and 12B is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 12A and 12B are separated into the scan electrode 12A and the sustain electrode 12B. The scan electrode 12A mainly supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12B mainly supplies a sustain signal. The data electrode 20 is formed to cross the sustain electrode pairs 12A and 12B. This data electrode 20 supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside.

The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the data electrode 20 to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 having such a structure is selected as the counter discharge by the data electrode 20 and the scan electrode 12A, and then maintains the discharge by surface discharge by the sustain electrode pairs 12A and 12B. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

FIG. 2 illustrates the overall electrode arrangement structure of the PDP including the discharge cells 30 shown in FIG. 1. In FIG. 2, it can be seen that the discharge cells 30 are configured at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the data electrode lines X1 to Xn.

The scan electrode lines Y1 to Ym supply the scan pulses and the sustain pulses so that the discharge cells 30 are scanned in units of lines, and the discharges are maintained in the discharge cells 30. The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to maintain the discharge in the discharge cells 30 together with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn supply data pulses synchronized with the scan pulse in line units so that the discharge cells 30 in which discharge is to be maintained are selected according to the logic value of the data pulses.

The PDP driving method is typically an ADS (Address and Display Separation) driving method which is driven separately into an address period and a display period, that is, a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. Each of these subfields has the same reset period (RPD) and address period (APD) and gives different weights to the sustain period (SPD). Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

FIG. 3 illustrates a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 among a plurality of subfields.

As shown in FIG. 3, the PDP initializes all of the discharge cells 30 to an off state in which wall charge remains by erasing wall charges after the front writing discharge is generated using the reset pulse RP in the reset period RPD. Let's do it. To this end, the scan electrode lines Y1 to Ym have a reset pulse RP, which gradually decreases to a rising ramp pulse and a base voltage 0V that gradually increase to the peak voltage Vr based on the step voltage Vs. A falling ramp pulse is supplied. The first dark discharge occurs in all the discharge cells 30 by the rising ramp pulse. Next, secondary dark discharge occurs in all the discharge cells 30 by the falling ramp pulse and the bias pulse BP supplied to the sustain electrode lines Z1 through Zm. Subsequently, the wall charges formed in the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm decrease according to the falling ramp pulse, and thus all the discharge cells 30 are initialized to the off state where the wall charges remain. do. In this reset period RPD, the voltages of the data electrode lines X1 to Xn are fixed to the base voltage 0V.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and a data pulse is applied to each of the data electrode lines X1 to Xn in synchronization with the scan pulse SP. (DP) is optionally supplied. As a result, address discharge is generated in the discharge cells supplied with the data pulse DP together with the scan pulse SP, so that the wall charge for the next sustain discharge is sufficiently formed. On the other hand, in the discharge cells to which the data pulse DP is not supplied together with the scan pulse SP, the address discharge does not occur, thereby maintaining the off state.

In the sustain period SPD, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the address period APD. The state of the discharge cell is maintained. Specifically, the discharge cells in the on state in which the wall charges are sufficiently formed in the address period APD remain in the on state by the discharge by the Y and Z sustain pulses SUSPy and SUSPz, and the discharge cells in the off state are in the off state without discharge. Keep it.

The wall charges present in all the discharge cells 30 are erased by supplying the erase pulse EP to the sustain electrode lines Z1 to Zm in the erase period EPD following the sustain period SPD. To be.

In order to supply these driving waveforms to the PDP shown in FIG. 2, the driving device is provided on the rear surface of the heat sink 64 located on the back side of the PDP 40 as shown in FIGS. 4 and 5.

The driving apparatus of the PDP shown in FIGS. 4 and 5 drives the Y driving board 45 for driving the scan electrode lines Y1 to Ym of the PDP 40 and the sustain electrode lines Z1 to Zm. A Z sustainer board 48 for driving, a data driver board 50 for driving the data electrode lines X1 to Xm, the Y driving board 45, a Z sustainer board 48, and a data driver A control board 42 for controlling the board 50 and a power board (not shown) for supplying power to each of the boards 42, 45, 48, and 50 are provided.

The Y drive board 45 includes a scan driver board 44 for generating the reset pulse RP and the scan pulse SP shown in FIG. 3 of the PDP 40, and a Y suspend for generating the Y sustain pulse SUSPy. A retainer board 46 is provided. The scan driver board 44 transmits a scan pulse SP to the scan electrode lines Y1 to Ym of the PDP 40 via a Y Flexible Printed Circuit (FPC) 51. Supply. The Y sustainer board 46 supplies the Y sustain pulse SUSPy to the scan electrode lines Y1 to Ym via the scan driver board 44 and the Y FPC 51.

The Z sustainer board 48 generates the bias pulses BP and the Z sustain pulses SUSz shown in FIG. 3 and the sustain electrode lines Z1 to Zm of the PDP 40 via the Z FPC 52. To feed.

The data driver board 50 generates the data pulse DP shown in FIG. 3 and supplies it to the data electrode lines X1 to Xn of the PDP 40 via the X FPC 54.

The control board 42 generates each of the X, Y, and Z timing control signals. The control board 42 transmits the Y timing control signal to the Y driving board 45 via the first FPC 56 and the Z timing control signal via the second FPC 58 to the Z sustainer board 48. ), The X timing control signal is supplied to the data driver board 50 via the third FPC 60.

When driving the PDP module having such a configuration, the current path in the sustain period SPD is as follows. First, when the Y sustain pulse SUSPy is supplied to the scan electrode lines Y1 to Ym from the Y drive board 45, the first current path is Y drive board 45-> scan electrode lines Y1 to Ym. -> Panel capacitor-> sustain electrode line (Z1 to Zm)-> Z sustainer board 48-> heat sink 64-> Y drive board 45. When the Z sustain pulse SUSPz is supplied to the sustain electrode lines Z1 to Zm in the Z sustainer board 48, the second current path is Z sustainer board 48-> sustain electrode line Z1 to Zm. Zm)-> panel capacitor-> scan electrode line (Y1 to Ym)-> Y drive board 45-> heat sink 64-> Z sustain board 48.

Since the heat sink 64 is operated at the ground level by the current path in the PDP module, there is a problem in that the front surface of the PDP 40 is affected by electromagnetic interference (EMI). In addition, the conventional PDP module has a disadvantage in that the configuration is complicated and the manufacturing cost is high as it includes a plurality of circuit boards.

Accordingly, it is an object of the present invention to provide a plasma display panel and a module thereof that integrate an sustainer board and reduce electromagnetic interference.

In order to achieve the above object, a plasma display panel module according to an embodiment of the present invention includes scan electrode lines, sustain electrode lines, and data electrode lines, and includes a first pad and the sustain electrode connected to the scan electrode lines. A plasma display panel having a second pad connected to the lines formed at one side thereof; An integrated driving board for driving the scan electrode lines and the sustain electrode lines; And a conductive path connected between one side of the integrated drive board and the first and second pads.

In the plasma display panel module according to the embodiment of the present invention, the plasma display panel is characterized in that the two sustain electrode lines are formed between the adjacent two scan electrode lines.

In the plasma display panel module according to an exemplary embodiment of the present invention, the second pad may be connected in common with one side of two adjacent sustain electrode lines.

In the plasma display panel module according to an embodiment of the present invention, the plasma display panel further includes a black matrix formed between two adjacent sustain electrode lines and commonly connected to the adjacent two sustain electrode lines. do.

In the plasma display panel module according to an exemplary embodiment of the present invention, the second pad may be connected to the black matrix.

In the plasma display panel module according to an exemplary embodiment of the present invention, the signal supplied to the second pad is supplied to two adjacent sustain electrode lines via the black matrix.

The conductive path in the plasma display panel module according to the embodiment of the present invention is characterized in that the flexible printed film.

In the plasma display panel module according to an exemplary embodiment of the present invention, the conductive path may be connected to any one of a front surface and a rear surface of one side of the integrated driving board.

In the plasma display panel module according to an embodiment of the present invention, the integrated driving board includes: a scan driver board generating a scan pulse to be supplied to the scan electrode lines; And an integrated sustainer board for generating a first sustain pulse to be supplied to the scan electrode lines and a second sustain pulse to be supplied to the sustain electrode lines.

According to an embodiment of the present invention, a plasma display panel module includes: a metal plate bonded to the plasma display panel to release heat from the plasma display panel; A data driver and a board for generating a data pulse to be supplied to the data electrode lines; A flexible printing film connected between a data driver board and the data electrode lines; A control board for supplying a corresponding control signal to each of the scan driver board and the integrated board and the data driver board; It further includes a power board for supplying power to each of the boards.

According to an embodiment of the present invention, a plasma display panel includes: a first pad connected to scan electrode lines; A black matrix formed between two adjacent sustain electrode lines and connected to the adjacent two sustain electrode lines; A second pad connected to the black matrix; The first and second pads may be formed at one side of the plasma display panel.

In the plasma display panel according to an exemplary embodiment of the present invention, a signal supplied to the second pad is supplied to two adjacent sustain electrode lines via the black matrix.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 16.

FIG. 6 illustrates a PDP module according to a first embodiment of the present invention, FIG. 7 illustrates a cross-sectional structure of the PDP module illustrated in FIG. 6, and FIG. 8 illustrates an output signal path of the YZ integrated board illustrated in FIG. 7. will be.

The PDP module shown in FIGS. 6 and 7 includes a PDP 70, a heat sink 86 provided on the rear surface of the PDP 70, a YZ integrated board 75 and a data driver board provided on the back surface of the heat sink 86. 80 and a control board 72 and a power board (not shown) for supplying power to each of the boards 75, 80, and 72.

The PDP 70 has a structure in which the upper plate 90 and the lower plate 92 are joined while providing a gas discharge space. Here, scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm are formed in parallel on the upper plate 90, and data electrode lines X1 to Xn on the lower plate 92. Is formed. In addition, a Y pad region 94 is provided at one side of the upper plate 90 to provide Y pads (not shown) connected to the scan electrode lines, and a Z pad region 96 is provided at the other side of the upper plate 90 to sustain electrode lines ( Z pads (not shown) connected to the not shown are formed. In addition, an X pad area (not shown) is formed at one side of the lower plate 92 to form X pads (not shown) connected to data lines. The upper plate 90 and the lower plate 92 are bonded to expose the Y pad region 94, the Z pad region 96, and the X pad region (not shown).

The heat sink 86 allows heat generated in the PDP 70 to be easily released to the outside. To this end, the heat sink 86 is installed so as to entirely overlap the rear surface of the PDP (70).

The control board 72 generates each of the X, Y, and Z timing control signals. The control board 72 transmits the Y and Z timing control signals to the YZ integrated board 100 via the first FPC 76 and the X timing control signals via the second FPC 78. 80).

The data driver board 80 generates a data pulse DP using the X timing control signal from the control board 72 as shown in FIG. 3 and the data electrode lines of the PDP 70 via the X FPC 88. To feed. Here, the X FPC 88 is connected to an X pad region (not shown) provided in the data driver board 80 and the PDP 70.

The Y-Z integrated board 100 is composed of a scan driver board 73 and a Y-Z sustainer board 74 and a connector 75 for connecting the two boards 73 and 74.

The scan driver board 73 uses the Y timing control signal from the control board 72 to reset the pulse RP to be supplied to the scan electrode lines in the reset period APD as shown in FIG. 3, and the address period APD. Generates a scan pulse SP to be supplied at. The scan driver board 73 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 70 via the Y FPC 82.

Here, the Y FPC 82 is connected to the scan driver board 73 and the Y pad region 94 of the PDP 70 as shown in FIG. 7.

The YZ sustainer board 74 uses the Y and Z timing control signals from the control board 72 to generate the Y sustain pulse SUSPy to be supplied to the scan electrode lines in the sustain period SPD as shown in FIG. Alternating with the Y sustain pulse SUSPy, a Z sustain pulse SUSPz to be supplied to the sustain electrode lines is generated. The Y-Z sustainer board 74 generates a bias pulse BP to be supplied to the sustain electrode lines in the reset period RPD and the address period APD as shown in FIG. 3. To this end, the YZ sustainer board 100 includes a Y sustain circuit (not shown) for generating a Y sustain pulse (SUSPy), and a Z sustain circuit (not shown) for generating a bias pulse (BP) and a Z sustain pulse (SUSPz). ). The YZ sustainer board 74 is connected to the Y sustain pulse (SUSPy) as shown in FIG. 8 via the connector 75-> scan driver board 73-> Y FPC 82 and the scan electrode of the PDP 70. To the lines. The Y-Z sustainer board 74 supplies the bias pulse BP and the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 70 via the Z FPC 84 as shown in FIG. 8.

Here, the Z FPC 84 is electrically connected to the YZ sustainer board 74 as shown in FIG. 7, and the Z pad region 96 provided in the PDP 70 via the PDP 70 and the heat sink 86. Connected with. A portion of the Z FPC 84 passing between the PDP 70 and the heat sink 86 may be formed of a conductive metal member.

Thus, the Y FPC 82 is connected to the scan driver board 73, and the Z FPC 84 is the YZ sustainer board 74 having a height difference from the scan driver board 73 through the connector 104. Is connected to. Here, the Y FPC 82 is connected to the front side (reference to the PDP 70) or the back side of the scan driver board 73, and the Z FPC 82 is connected to the front side or the back side of the Y-Z sustainer board 74.

For example, the Y FPC 82 is connected to the rear surface of the scan driver board 73 as shown in FIGS. 7 and 8, and the Z FPC 84 is connected to the front surface of the Y-Z sustainer board 74. Accordingly, even if the Y FPC 82 and the Z FPC 84 are connected to one side of the YZ integrated board 100, they are contacted with each other by being separated by a height difference between the scan driver board 73 and the YZ sustainer board 74. Can be prevented to bring about driving stabilization. In addition, since the Z FPC 84 is connected to the Z pad region 96 via the PDP 70 and the heat sink 86, the heat sink 86 does not act as a current path. Interference (EMI) can be minimized.

However, in the plasma display panel module according to the first embodiment of the present invention, the PDP 70 and the heat sink 86 are connected to the YZ sustainer board 74 in the Z pad region 96 provided in the PDP 70. Z FPC 84 via) is required. The Z FPC 84 has a problem in that it is difficult to work for mass production because the length to be connected is long. In order to solve this problem, a PDP module as shown in FIG. 9 is proposed.

FIG. 9 illustrates a PDP module according to a second embodiment of the present invention, and FIG. 10 illustrates a cross-sectional structure of the PDP module illustrated in FIG. 9.

The PDP module illustrated in FIGS. 9 and 10 includes a PDP 170, a heat sink 186 provided on the rear surface of the PDP 170, a YZ integrated board 175 and a data driver board installed on the rear surface of the heat sink 186. 180 and a control board 172 and a power board (not shown) for supplying power to each of the boards (175, 180, 172).

The PDP 170 has a structure in which the upper plate 190 and the lower plate 192 are bonded while providing a gas discharge space. Here, scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm are formed in parallel on the upper plate 190, and data electrode lines X1 to Xn on the lower plate 192. Is formed. In addition, Y and Z pad regions 194 may be provided at one side of the upper plate 190 to provide Y pads (not shown) connected to scan electrode lines and Z pads connected to sustain electrode lines (not shown). (Not shown) is formed. In addition, an X pad area (not shown) is formed at one side of the lower plate 192 to form X pads (not shown) connected to data lines. The upper plate 190 and the lower plate 192 are bonded to expose the Y and Z pad regions 194 and the X pad regions (not shown).

The heat sink 186 allows heat generated from the PDP 170 to be easily released to the outside. To this end, the heat sink 186 is installed so as to overlap the entire back surface of the PDP 170.

The control board 172 generates each of the X, Y, and Z timing control signals. The control board 172 transfers the Y and Z timing control signals to the YZ integrated board 200 via the first FPC 176 and the X timing control signals through the second FPC 178. 180).

The data driver board 180 generates a data pulse DP using the X timing control signal from the control board 172 and the data electrode lines of the PDP 170 via the X FPC 188 as shown in FIG. 3. To feed. Here, the X FPC 188 is connected to an X pad region (not shown) provided in the data driver board 180 and the PDP 170.

The Y-Z integration board 200 is composed of a scan driver board 173 and a Y-Z sustainer board 174, and a connector 175 for connecting the two boards 173 and 174.

The scan driver board 173 receives the reset pulse RP to be supplied to the scan electrode lines in the reset period APD as shown in FIG. 3 using the Y timing control signal from the control board 172, and the address period APD. Generates a scan pulse SP to be supplied at. The scan driver board 173 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 170 via the Y / Z FPC 182.

The YZ sustainer board 174 uses the Y and Z timing control signals from the control board 172 to generate the Y sustain pulse SUSPy to be supplied to the scan electrode lines in the sustain period SPD as shown in FIG. 3. Alternating with the Y sustain pulse SUSPy, a Z sustain pulse SUSPz to be supplied to the sustain electrode lines is generated. The Y-Z sustainer board 174 generates a bias pulse BP to be supplied to the sustain electrode lines in the reset period RPD and the address period APD as shown in FIG. 3. To this end, the YZ sustainer board 200 includes a Y sustain circuit (not shown) for generating a Y sustain pulse (SUSPy), and a Z sustain circuit (not shown) for generating a bias pulse (BP) and a Z sustain pulse (SUSPz). ). The YZ sustainer board 174 connects the Y sustain pulse SUSPy to the scan electrode lines of the PDP 170 via the connector 175-> scan driver board 173-> Y / Z FPC 182. Supply. In addition, the YZ sustainer board 174 connects the bias pulse BP and the Z sustain pulse SUSPz to the PDP 170 via the connector 175-> scan driver board 173-> Y / Z FPC 182. To the sustain electrode lines.

Here, the Y / Z FPC 182 is electrically connected to the Y-Z integrated board 200 as shown in FIG. 10 and is connected to the Y / Z pad region 194 provided at one side of the PDP 170. That is, as shown in FIG. 11, the Y pad 194a connected to the scan electrode lines and the Z pad 194b connected to the sustain electrode lines are formed together on one side of the PDP 170 to form a YZ integrated board ( By connecting to the 200, one Y / Z FPC connector 82 can be easily connected to the YZ integrated board 200. Accordingly, the work for mass production can be made more convenient. At this time, since the Y and Z pads 194a and 194b are formed together at one side of the PDP 170, the number of connecting pins of the Y / Z FPC 182 is connected to the conventional Y pad area as shown in FIG. It is about twice as much as Y FPC. However, in the case of the YY-ZZ electrode structure as shown in FIG. 13, since the sustain electrode lines are common electrodes and are connected to the Z pad 194b by tying up two lines, the increased number of connecting pins is shown in FIG. 14. Half of the lines are needed.

Meanwhile, since the voltage is supplied to the scan electrode and the sustain electrode lines only on one side of the PDP 170 as shown in FIG. 15, a voltage drop is generated by the electrode resistance toward the opposite side. A difference in luminance may occur at both sides. That is, since the voltage supplied to the scan electrode and the sustain electrode lines is large at the point A where the voltage is supplied to the scan electrode and the sustain electrode lines, the discharge between the two electrodes is actively generated and the luminance is increased. However, since the voltage supplied to the scan electrode and the sustain electrode lines decreases toward the point B, the luminance is lowered. Afterwards, the voltage supplied to the scan electrode and the sustain electrode lines is significantly lowered to point C, thereby weakening the discharge between the two electrodes. As a result, the luminance is significantly lowered at the C point. Therefore, a luminance difference occurs on both sides of the PDP 170, resulting in a drop in contrast performance. In order to improve this problem, an electrode structure as shown in FIG. 16 is proposed.

Referring to FIG. 16, a black matrix 195 is formed between two adjacent sustain electrode lines which are bundled to improve the contrast performance of the PDP 170. In this case, since the black matrix 195 may use a conductive material, the Y and Z pads 194a and 194b may be used to supply current (voltage) to two adjacent sustain electrode lines as shown in FIG. 13. ) And two sustain electrode lines adjacent to the black matrix 195 are connected to each other at the opposite position where the () is formed. Accordingly, currents (voltages) supplied to adjacent sustain electrode lines are respectively supplied by turning to the adjacent sustain electrode lines through the black matrix 195 by forming a current path in a dotted arrow direction as shown in FIG. 16. . Accordingly, even when a voltage is supplied to the scan electrode and the sustain electrode lines only on one side of the PDP 170, the PDP 170 may obtain uniform luminance because a constant voltage difference may be maintained between the scan electrode and the sustain electrode lines. .

In addition, as illustrated in FIG. 16, a current path is formed in the electrode structure of FIG. 16 by the black matrix 195 in the dotted arrow direction to supply current (voltage) to the sustain electrode lines. Accordingly, since the directions of the current (voltage) supplied to the scan electrode lines and the current (voltage) supplied to the sustain electrode lines are opposite to each other and the amount of current are the same, the magnetic fields are canceled to minimize the electromagnetic interference (EMI). It becomes possible.

As described above, the plasma display panel and the module thereof according to the embodiment of the present invention can simplify the configuration of the circuit board by integrating the scan driver board and the Y-Z integrated sustainer board and mounting them on one board.

In particular, the plasma display panel and its module according to an embodiment of the present invention is a YZ sustainer board incorporating Y and Z sustain circuits, and a plasma display panel having scan electrode pads and sustain electrode pads formed at one side thereof as one FPC. Workability can be improved by connecting. In addition, a black matrix may be formed between two sustain electrode lines to obtain an electromagnetic interference (EMI) improvement effect.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A plasma display panel having scan electrode lines, sustain electrode lines, and data electrode lines, wherein a first pad connected to the scan electrode lines and a second pad connected to the sustain electrode lines are formed at one side thereof; A scan driver board for generating scan pulses to be supplied to the scan electrode lines is mounted, and an integrated sustain source for generating a first sustain pulse to be supplied to the scan electrode lines and a second sustain pulse to be supplied to the sustain electrode lines. An integrated drive board to which a retainer board is mounted; A conductive path connected between one side of the integrated driving board and the first and second pads, And the plasma display panel includes a black matrix formed between two adjacent sustain electrode lines and commonly connected to the adjacent two sustain electrode lines. The method of claim 1, And the adjacent two sustain electrode lines formed on the plasma display panel are formed between the adjacent two scan electrode lines. The method of claim 2, And the second pad is connected in common with one side of two adjacent sustain electrode lines. delete The method of claim 3, wherein And the second pad is connected to the black matrix. The method of claim 5, And the signal supplied to the second pad is supplied to two adjacent sustain electrode lines via the black matrix. The method of claim 1, The conductive path is a plasma display panel module, characterized in that the flexible printing film. The method of claim 1, And the conductive path is connected to any one of a front surface and a rear surface of one side of the integrated driving board. delete The method of claim 1, A metal plate bonded to the plasma display panel for dissipating heat from the plasma display panel; A data driver and a board for generating a data pulse to be supplied to the data electrode lines; A flexible printing film connected between the data driver board and the data electrode lines; A control board for supplying a corresponding control signal to each of the scan driver board, the integrated board, and the data driver board; And a power board for supplying power to each of the boards. In the plasma display panel in which two adjacent sustain electrode lines are formed between two adjacent scan electrode lines, A first pad connected to the scan electrode lines; A black matrix formed between the two adjacent sustain electrode lines and connected to the adjacent two sustain electrode lines; A second pad connected to said black matrix; The first and second pads are formed on one side of the plasma display panel. The method of claim 11, And the signal supplied to the second pad is supplied to two adjacent sustain electrode lines via the black matrix.

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