JP5130672B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A plasma display device using a typical plasma display panel (hereinafter simply abbreviated as “panel”) as an image display panel has a wide viewing angle, is easy to enlarge, is self-luminous, and has an image display quality. Is becoming the mainstream of large-screen image display devices.

  In the panel, a large number of discharge cells are formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. In the back plate, a plurality of parallel data electrodes are formed on a back glass substrate, and barrier ribs and phosphor layers are further formed. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  The plasma display device displays images by applying sustain pulses alternately to the display electrode pairs to discharge and emit light from these discharge cells.

In order to stably generate a sustain discharge in each discharge cell, it is necessary to apply a sustain pulse having a steep shape with an amplitude of typically several hundreds of volts and a rise time of 1 μsec or less to the display electrode pair. At this time, for example, if the display screen size is a 40-inch panel, a large current exceeding several tens of amperes flows instantaneously. For this reason, the layout and wiring of the drive circuit, etc., should be reduced so that the impedance of the current path from the drive circuit to each of the display electrode pairs is reduced so that no ringing or the like is superimposed on the sustain pulse and no voltage drop due to a large current occurs. It is very important to devise the method to generate a stable discharge. For example, Patent Document 1 discloses a plasma display device in which the arrangement of the drive circuit and its wiring are devised to reduce parasitic inductance and to reduce ringing of the voltage waveform of the panel.
JP 2004-347622 A

  However, as the screen of the panel further increases, the displacement current for charging and discharging the panel capacity and the discharge current accompanying the discharge increase in proportion to the square of the display screen size, and the slight impedance of the current path is also imaged. It has become a factor that degrades display quality. As the screen of the panel increases, the difference in the impedance of the current path from the drive circuit to each display electrode pair also increases, but the difference in image display quality due to the difference in the current path also becomes so large that it cannot be ignored. It is coming.

  In fact, when the display screen size of the panel is increased to about 100 inches, the length of the short side of the panel is 1 m or more and the length of the long side is 2 m or more. Not only is it high, the length of the current path from the drive circuit to each of the display electrode pairs is not the same, and the display electrode pair in the center of the display screen can be wired relatively short, The upper and lower display electrode pairs on the display screen become longer. For this reason, it is extremely difficult to supply the same drive voltage waveform to each of the display electrode pairs. If a large ringing is superimposed on the drive voltage waveform or a large variation occurs in the drive voltage waveform applied to each of the display electrode pairs, brightness unevenness, color unevenness, etc. occur, and the image display quality is greatly reduced.

  The present invention has been made in view of these problems, and provides a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of a pair of display electrodes even in a large-screen panel. The purpose is to provide.

  The present invention has a panel in which discharge cells are formed at intersections between a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and an image is generated by applying a drive voltage to the scan electrode and the sustain electrode of the plasma display panel. A plurality of voltage supply printed boards for supplying a drive voltage to at least one of the scan electrodes and the sustain electrodes, and the scan electrodes and the sustain electrodes via the voltage supply printed boards. A sustain pulse generating printed circuit board for generating a sustain pulse to be supplied to at least one, and a conductive plate for supplying the sustain pulse from the sustain pulse generating printed circuit board to the voltage supplying printed circuit board are provided. With this configuration, it is possible to provide a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of the display electrode pairs even in a large-screen panel.

  Further, the voltage supply printed circuit board of the plasma display device of the present invention may generate a scanning pulse.

  According to the present invention, it is possible to provide a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of the display electrode pairs even in a large-screen panel.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
The panel in the present embodiment has a display screen size of 103 inches, and the panel has a long side length of about 2.3 m and a short side length of about 1.3 m.

  FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. On the front substrate 21 made of glass, a plurality of display electrode pairs 28 made up of the scan electrodes 22 and the sustain electrodes 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 cross each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 28 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (maintenance in FIG. 1) that are long in the row direction (n = 1080 in the present embodiment). Electrode 23) is arranged, and m data electrodes D1 to Dm (data electrode 32 in FIG. 1) that are long in the column direction (m = 5760 in the present embodiment) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  FIG. 3 is a circuit block diagram of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each circuit block. Scan electrode driving circuit 53 generates sustain pulse generator 100 for generating a sustain pulse in the sustain period, initialization waveform generator 300 for generating a ramp waveform voltage in the initialization period, and generates a scan pulse in the write period. A scan pulse generator 400 is provided, and each of the scan electrodes SC1 to SCn is driven based on the timing signal. Sustain electrode drive circuit 54 has sustain pulse generator 200 for generating a sustain pulse in the sustain period, and drives sustain electrodes SU1 to SUn based on the timing signal.

  FIG. 4 is a circuit diagram showing details of scan electrode drive circuit 53 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Sustain pulse generation unit 100 includes power recovery unit 110 and clamp unit 120. The power recovery unit 110 includes a power recovery capacitor C100, switching elements Q111 and Q112, backflow prevention diodes D101 and D102, and a resonance inductor L100. The power recovery capacitor C100 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half of the voltage value Vs described later, so as to serve as a power source for the power recovery unit 110. Yes. The clamp part 120 has switching elements Q121 and Q122. Further, a smoothing capacitor C150 for reducing the impedance of the voltage source Vs is provided. The initialization waveform generation unit 300 includes a Miller integrating circuit having a switching element Q311, a capacitor C310, and a resistor R310, a Miller integrating circuit having a switching element Q322, a capacitor C320, and a resistor R320, a separation circuit using the switching element Q312, and switching. A separation circuit using the element Q321 is provided. Scan pulse generation unit 400 includes switch units OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, and switching element Q401 for clamping the low voltage side of switch units OUT1 to OUTn to voltage Va. I have. Each of the switch units OUT1 to OUTn includes switching elements QH1 to QHn for outputting the voltage Vc and switching elements QL1 to QLn for outputting the voltage Va.

  Here, since a very large current flows through the switching elements Q121, Q122, Q312 and Q321, a plurality of FETs, IGBTs and the like are connected in parallel to these switching elements to reduce the impedance.

  FIG. 5 is a circuit diagram showing details of sustain electrode drive circuit 54 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Sustain pulse generation unit 200 has the same configuration as sustain pulse generation unit 100. That is, a power recovery unit C200 having a power recovery capacitor C200, switching elements Q211 and Q212, backflow prevention diodes D201 and D202, and a resonance inductor L200, and a clamp unit having switching elements Q221 and Q222 and a smoothing capacitor C250 220, and is connected to sustain electrodes SU1 to SUn of panel 10. Further, FIG. 5 shows switching elements Q231 and Q232 for applying voltage Ve1 to sustain electrodes SU1 to SUn, a backflow prevention diode D231, and voltage Ve2 obtained by stacking voltage Ve1 on voltage Ve1 and sustain electrodes SU1 to SUn. Also shown are switching elements Q241 and Q242 and a capacitor C241 for applying to the capacitor.

  Again, since a very large current flows through the switching elements Q221 and Q222, a plurality of FETs, IGBTs and the like are connected in parallel to these switching elements to reduce the impedance.

  Next, a driving voltage waveform for driving the panel and its operation will be described. The subfield method is used as a method for driving the panel. In this method, one field period is divided into a plurality of subfields, and gradation display is performed by controlling light emission / non-light emission of each discharge cell in each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent address operation are formed. In the address period, a scan pulse is sequentially applied to the scan electrodes and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes to perform address discharge, thereby selectively forming wall charges. In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the display luminance to be emitted is applied between the scan electrode and the sustain electrode, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged and emitted. .

  Below, the detail of the drive voltage waveform for driving the panel 10 and its operation | movement are demonstrated. FIG. 6 is a drive voltage waveform diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 6 shows drive voltage waveforms in the first subfield and the second subfield.

  In the first half of the initializing period of the first subfield, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, and the scan electrodes SC1 to SCn are applied to the sustain electrodes SU1 to SUn. A ramp waveform voltage that gently rises from a voltage Vi1 equal to or lower than the discharge start voltage toward a voltage Vi2 that exceeds the discharge start voltage is applied. This ramp waveform voltage is generated by turning on a Miller integrating circuit comprising switching element Q311, capacitor C310 and resistor R310 in FIG. Then, it is applied to scan electrode SC1 via switching elements Q321 and QL1, applied to scan electrode SC2 via switching elements Q321 and QL2, and similarly applied to scan electrode SCn via switching elements Q321 and QLn. . While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn via switching elements Q231 and Q232. At this time, the switching element Q242 is turned on, and charging is performed so that the voltage of the capacitor C241 becomes the voltage Ve1. A scan waveform SC1 to SCn is applied with a ramp waveform voltage that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage with respect to sustain electrodes SU1 to SUn. This ramp waveform voltage is generated by turning on the Miller integrating circuit composed of the switching element Q322, the capacitor C320, and the resistor R320 in FIG. Then, it is applied to scan electrodes SC1 to SCn via switching element Q321 and switching elements QL1 to QLn. During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The

  Thus, the initialization operation ends. Note that, as shown in the initialization period of the second subfield in FIG. 6, only the voltage waveform in the latter half of the initialization period may be applied as the drive voltage waveform in the initialization period. Initializing discharge is selectively generated in the discharge cells that have undergone sustain discharge in the sustain period of the immediately preceding subfield.

  In the subsequent address period, switching element Q401 is turned on and switching elements QH1 to QHn are turned on to apply voltage Vc to scan electrodes SC1 to SCn. Then, switching element Q242 is turned off, switching elements Q231, Q232, and Q241 are turned on, and voltage Ve1 + ΔVe, that is, voltage Ve2, is applied to sustain electrodes SU1 to SUn. Next, the switching element QH1 is turned off and the switching element QL1 is turned on, so that the negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row. Then, a positive address pulse voltage Vd is applied to the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the difference between the externally applied voltages (Vd−Va). The discharge start voltage is exceeded. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until reaching the discharge cell in the nth row, and the address period ends.

  In the sustain period, switching element Q212 is turned on. Then, the charges on the sustain electrodes SU1 to SUn side start to flow to the capacitor C200 through the inductor L200, the diode D202, and the switching element Q212, and the voltage of the sustain electrodes SU1 to SUn starts to decrease. Then, switching element Q222 is turned on when the voltage of sustain electrodes SU1 to SUn drops to near 0 (V). Then, sustain electrodes SU1 to SUn are clamped to 0 (V) through switching element Q222.

  Further, the switching element Q111 is turned on. Then, current begins to flow from switching capacitor Q111, diode D101, inductor L100, switching elements Q312, Q321, and switching elements QL1 to QLn from power recovery capacitor C100, and the voltages of scan electrodes SC1 to SCn begin to rise. Then, when the voltage of scan electrodes SC1 to SCn rises to near Vs, switching element Q121 is turned on. Then, scan electrodes SC1 to SCn are clamped to voltage Vs of smoothing capacitor C150 through switching element Q121, switching elements Q312 and Q321 and switching elements QL1 to QLn.

  In this manner, 0 (V) is applied to sustain electrodes SU1 to SUn, and positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time.

  As a result of this discharge, negative wall voltage is accumulated on scan electrode SCi, and positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, although not described in detail, 0 (V) is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a potential difference is applied between the electrodes of the display electrode pair, so that the address discharge is performed in the address period. The sustain discharge is continuously performed in the discharge cell that has caused the failure.

  At the end of the sustain period, a so-called narrow pulse-like potential difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on the electrode SCi and the sustain electrode SUi is erased. Thus, the maintenance operation in the maintenance period is completed.

  Along with the sustain discharge described above, a discharge current corresponding to the number of discharge cells that have caused discharge flows. For example, assuming that discharge occurs in all the discharge cells, a very large current exceeding 100 A instantaneously flows. However, in the present embodiment, although details will be described later, since the arrangement of the drive circuit is devised so that the impedance of the current path from the smoothing capacitor C150 to each scan electrode SCi is very small, a large voltage drop is caused. A desired sustain pulse can be applied to the display electrode pair without being generated.

  The operation of the subsequent subfield is substantially the same as the operation of the first subfield, and thus description thereof is omitted.

  In this embodiment, the voltage value applied to each electrode is, for example, voltage Vi1 = voltage Vi3 = voltage Vs = 200 (V), voltage Vi2 = 440 (V), voltage Vi4 = −80 (V), voltage Va = −85 (V), voltage Ve1 = 150 (V), and voltage Ve2 = 155 (V). However, these voltage values are merely an example, and it is desirable to set them appropriately to optimum values according to the panel characteristics, the specifications of the plasma display device, and the like.

  FIG. 7 is an exploded perspective view showing the structure of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, a chassis 80 that holds the panel 10, a heat conductive sheet 82 that transfers heat generated in the panel 10 to the chassis 80, and bonds the panel 10 and the chassis 80 to each other. A circuit block 84 for driving the panel 10, such as a power supply circuit, a scan electrode drive circuit, a sustain electrode drive circuit, a timing generation circuit, and the like, and a front frame 86 and a back cover 88 for housing them are provided.

  As described above, the 103-inch panel has a short side length of approximately 1.3 m. However, since the size of a printed board that can be normally used is about 50 cm at most, a plurality of printed boards can be used. The scanning electrode drive circuit 53 and the sustain electrode drive circuit 54 are configured by using them.

  7 includes four printed circuit boards 531 to 534 on which the scan electrode driving circuit 53 is mounted in the circuit block 84, a conductive plate 900 that electrically connects the four printed circuit boards 531 to 534, and a conductive structure. Insulating sheets 910 and 912 for insulating the plate 900 are shown.

  FIG. 8 is a diagram showing the arrangement of the printed circuit board on which each electrode driving circuit is mounted according to Embodiment 1 of the present invention, and each electrode driving circuit is mounted with the back cover 88 of the plasma display device 1 removed. It is a figure which shows a printed circuit board and its arrangement | positioning typically. In FIG. 8, the chassis 80, 12 printed boards 521 on which the data electrode driving circuit 52 is mounted, 32 flexible boards (hereinafter abbreviated as “FPC”) 529, and 4 on which the scanning electrode driving circuit 53 are mounted. The printed circuit boards 531 to 534 and the three printed circuit boards 541 to 543 on which the sustain electrode driving circuit 54 is mounted are shown. Further, FPC 539 for applying the output voltage of scan electrode driving circuit 53 to each of scan electrodes SC1 to SCn, and FPC 549 for applying the output voltage of sustain electrode driving circuit 54 to sustain electrodes SU1 to SUn are also shown. Here, the four printed circuit boards on which the scan electrode driving circuit 53 is mounted include three voltage supply printed circuit boards 532 to 534 for supplying a drive voltage to the scan electrodes, and the voltage supply printed circuit boards 532 to 534. This is a sustain pulse generating printed circuit board 531 that generates sustain pulses to be supplied to each.

  Further, a conductive plate 900 covered with insulating sheets 910 and 912 is provided between the sustain pulse generating printed circuit board 531 and the voltage supplying printed circuit boards 532 to 534 and the chassis 80. FIG. Only 912 is shown.

  FIG. 9 is a circuit diagram of scan electrode driving circuits mounted on sustain pulse generating printed circuit board 531 and voltage supply printed circuit boards 532 to 534 according to the first embodiment of the present invention, and FIG. 10 shows the implementation of the present invention. 6 is an exploded perspective view showing an arrangement of sustain pulse generating printed circuit board 531, voltage supplying printed circuit boards 532 to 534, and conductive plate 900 in Embodiment 1. FIG.

  Sustain pulse generating printed circuit board 531 has sustain pulse generating unit 100 and initialization waveform generating unit 300 mounted thereon. Portions corresponding to scan electrodes SC1 to SC360 of scan pulse generator 400 are mounted on voltage supply printed board 532, and portions corresponding to scan electrodes SC361 to SC720 of scan pulse generator 400 are mounted on voltage supply printed board 533. And a portion corresponding to scan electrodes SC721 to SC1080 of scan pulse generator 400 is mounted on voltage supply printed circuit board 534.

  In this embodiment, conductive plate 900 is formed of an aluminum plate having a thickness of 1 mm and has a shape having a surface facing each of sustain pulse generating printed circuit board 531 and voltage supplying printed circuit boards 532 to 534. Formed and disposed between the chassis 80 and the four printed circuit boards 531 to 534. Further, an insulating sheet 910 having substantially the same shape as that of the conductive plate 900 is disposed between the chassis 80 and the conductive plate 900, and an insulating sheet 912 is also disposed between the conductive plate 900 and the printed boards 531 to 534. Yes. The insulating sheets 910 and 912 can be used as long as they can withstand a withstand voltage and have a certain level of heat resistance. Examples of such materials include modified PPE (polyphenylene ether), PC (polycarbonate), PET (polyethylene terephthalate), ABS resin, and polyimide. In the present embodiment, modified PPE sheets having a thickness of 0.3 to 0.5 mm are used as the insulating sheets 910 and 912.

  Each of sustain pulse generating printed circuit board 531 and voltage supplying printed circuit boards 532 to 534 is fixed to conductive plate 900 with screws, with insulating sheet 912 interposed therebetween. Here, sustain pulse generating printed circuit board 531 uses metal screw 631 in the wiring portion of the output of printed circuit board 531 so that the voltage of conductive plate 900 becomes equal to the voltage at point P1 which is the output of printed circuit board 531. Are fixed to the conductive plate 900. The voltage supply printed circuit board 532 generates a scan pulse using the output voltage of the sustain pulse generation printed circuit board 531 as a reference voltage, and a metal screw 632 is used in the wiring portion of the voltage at point P2, which is the reference voltage. Are fixed to the conductive plate 900. Similarly, with respect to the voltage supply printed boards 533 and 534, the metal screws 633 and 634 are used at the wiring portions of the voltage at the points P3 and P4 which are the reference voltages of the voltage supply printed boards 533 and 534, respectively. It is fixed to the conductive plate 900. A through hole is provided at a position corresponding to the screw fixing of the insulating sheet 912 so as not to prevent conduction.

  Thus, the conductive plate 900 not only serves as an auxiliary chassis for fixing the sustain pulse generating printed circuit board 531 and the voltage supplying printed circuit boards 532 to 534, but also from the sustain pulse generating printed circuit board to the voltage supplying printed circuit board. It also serves as a supply path for supplying the sustain pulse. By supplying the sustain pulse using the conductive plate 900 having a low impedance, the three voltage supply printed boards 532 do not cause a large ringing or voltage drop to the three voltage supply print boards 532 to 534. A drive voltage waveform can be supplied without large variations between .about.534. As a result, it is possible to realize an image display device with less luminance unevenness and color unevenness even when a panel having a large display screen size is used and the scan electrode driving circuit is divided and mounted on a plurality of printed circuit boards. .

  Although scan electrode driving circuit 53 in the present embodiment has been described as being configured using sustain pulse generating printed circuit board 531 and voltage supplying printed circuit boards 532 to 534, sustain pulse generating printed circuit board 531 and voltage supply are described. The printed circuit board 533 may be connected to form a single printed circuit board.

  Further, in the present embodiment, the configuration in which the sustain pulse is supplied from the sustain pulse generating printed board to the voltage supplying printed board only through the conductive plate has been described. However, a sustain pulse may be supplied through a coupler or the like in addition to the supply path of the conductive plate using a coupler or the like that electrically connects the sustain pulse generating printed board and the voltage supply printed board.

(Embodiment 2)
FIG. 11 is a diagram showing an arrangement of a printed circuit board on which each electrode drive circuit according to the second embodiment of the present invention is mounted. FIG. 12 shows a sustain pulse generating printed circuit board 741 and voltage supply according to the second embodiment of the present invention. 7 is an exploded perspective view showing the arrangement of the printed circuit boards 742 to 744 and the conductive plate 950. FIG.

  The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The present embodiment is different from the first embodiment in that the sustain electrode driving circuit 54 is divided into a sustain pulse generating printed circuit board 741 and voltage supplying printed circuit boards 742 to 744, and the four printed circuit boards 741 to 744 A conductive plate 950 covered with insulating sheets 960 and 962 is provided between the chassis 80 and the printed circuit boards 741 to 744 so as to face each other.

  Sustain pulse generating unit 200 is mounted on printed circuit board 741 for sustain pulse generation. Active components are not particularly mounted on the voltage supply printed boards 742 to 744, but an FPC 549 connected to the sustain electrodes is provided.

  The conductive plate 950 is formed of an aluminum plate having a thickness of 1 mm, as in the first embodiment, and has a shape having surfaces facing the sustain pulse generating printed circuit board 741 and the voltage supplying printed circuit boards 742 to 744, respectively. , Between the chassis 80 and the four printed circuit boards 741 to 744. Further, an insulating sheet 960 having substantially the same shape as the conductive plate 950 is disposed between the chassis 80 and the conductive plate 950, and an insulating sheet 962 is also disposed between the conductive plate 950 and the printed circuit boards 741 to 744. Yes.

  Each of the sustain pulse generating printed circuit board 741 and the voltage supplying printed circuit boards 742 to 744 is fixed to the conductive plate 950 with screws while sandwiching the insulating sheet 962. Of course, a through hole is provided at a position corresponding to the screw fixing of the insulating sheet 962 so as not to prevent conduction. Sustain pulse generation printed circuit board 741 is fixed to conductive plate 950 using metal screw 841 at the output wiring portion so that the voltage of conductive plate 950 becomes equal to the output voltage of sustain pulse generation printed circuit board 741. ing. Further, the voltage supply printed board 742 is fixed to the conductive plate 950 using a metal screw 842 at a wiring portion to which the FPC 549 is connected. Similarly, the voltage supply printed boards 743 and 744 are fixed to the conductive plate 950 using metal screws 843 and 844 at wiring portions to which the FPC 549 is connected, respectively.

  Thus, the conductive plate 900 not only serves as an auxiliary chassis for fixing the sustain pulse generating printed circuit board 741 and the voltage supplying printed circuit boards 742 to 744, but also from the sustain pulse generating printed circuit board to the voltage supplying printed circuit board. It also serves as a supply path for supplying the sustain pulse. By supplying the sustain pulse using the conductive plate 950 having a low impedance, there is no large ringing or voltage drop, and there is no large variation between the three voltage supply printed boards 742 to 744. A drive voltage waveform can be supplied to one printed circuit board 742 to 744 for voltage supply. As a result, it is possible to realize an image display device with less luminance unevenness and color unevenness even when a panel having a large display screen size is used and the scan electrode driving circuit is divided and mounted on a plurality of printed circuit boards. .

  Although the sustain electrode driving circuit 54 in the present embodiment has been described as being configured using four printed circuit boards 741 to 744, the sustain pulse generating printed circuit board 741 and the voltage supplying printed circuit board 743 are connected. Alternatively, it may be composed of a single printed circuit board.

  Further, in the present embodiment, the configuration in which the sustain pulse is supplied from the sustain pulse generating printed board to the voltage supplying printed board only through the conductive plate has been described. However, a sustain pulse may be supplied through a coupler or the like in addition to the supply path of the conductive plate using a coupler or the like that electrically connects the sustain pulse generating printed board and the voltage supply printed board.

  The present invention is useful as an image display apparatus using a panel because a desired drive voltage waveform can be supplied to each display electrode pair to display a high-quality image even in a large-screen panel.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention Circuit diagram showing details of scan electrode drive circuit of same plasma display device Circuit diagram showing details of sustain electrode drive circuit of same plasma display device Driving voltage waveform diagram of the plasma display device An exploded perspective view showing the structure of the plasma display device The figure which shows arrangement | positioning of the printed circuit board carrying each electrode drive circuit of the plasma display apparatus Circuit diagram of scan electrode driving circuit mounted on printed circuit board of plasma display device Exploded perspective view showing arrangement of printed circuit board and conductive plate of same plasma display device The figure which shows arrangement | positioning of the printed circuit board carrying each electrode drive circuit of the plasma display apparatus in Embodiment 2 of this invention. Exploded perspective view showing arrangement of printed circuit board and conductive plate of same plasma display device

Explanation of symbols

1 Plasma display device 10 Panel (Plasma display panel)
DESCRIPTION OF SYMBOLS 21 Front substrate 22 Scan electrode 23 Sustain electrode 28 Display electrode pair 31 Back substrate 32 Data electrode 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 80 Chassis 521,541,542 , 543 Printed circuit board 529,539,549 FPC
531,741 (for sustain pulse generation) Printed circuit board 532,533,534,742,743,744 (For voltage supply) Printed circuit board 631,632,633,634,841,842,843,844 Screw 900,950 Conductive plate 910, 912, 960, 962 Insulating sheet SC1 to SCn Scan electrode SU1 to SUn Sustain electrode D1 to Dm Data electrode

Claims (2)

A plasma display panel having a discharge cell formed at the intersection of a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and applying a drive voltage to the scan electrode and the sustain electrode of the plasma display panel A plasma display device for displaying, a plurality of voltage supply printed circuit boards for supplying a drive voltage to at least one of the scan electrode and the sustain electrode;
A sustain pulse generating PCB for supplying a driving voltage to the voltage supply printed circuit board for generating a sustain pulse to at least one of the scan electrodes and the sustain electrode through the voltage supply printed circuit board,
A conductive plate for supplying sustain pulses from the sustain pulse generating PCB to the voltage supply PCB,
A plasma display device comprising: The plasma display apparatus as claimed in claim 1, wherein the voltage supply printed circuit board supplies a drive voltage to the scan electrode to generate a scan pulse.

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