JP2011145427A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply a desired driving voltage waveform to each of a pair of display electrodes even in the case of a large-screen plasma display panel. <P>SOLUTION: The plasma display device has a panel forming a discharge cell at the intersection between a display electrode pair including a scanning electrode and a sustaining electrode and a data electrode, and displays an image by applying a sustaining pulse to the scanning electrode and the sustaining electrode during a sustaining period. The plasma display device includes a sustaining pulse generation circuit board 51 having a sustaining pulse generation circuit 41 mounted to generate a sustaining pulse supplied to the scanning electrode, sustaining pulse supplying circuit boards 52 and 53 for supplying the sustaining pulses to the respective scanning electrodes, and clamping circuits 44 and 45 for executing clamping to prevent a potential of a wire for supplying the sustaining pulses of the sustaining pulse supplying circuit boards 52 and 53 from exceeding a voltage Vs of a high-voltage side of the sustaining pulse during the sustaining period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a plasma display device using an AC surface discharge type plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate which are arranged to face each other. In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. In the rear substrate, a plurality of parallel data electrodes are formed on a rear glass substrate, and barrier ribs and phosphor layers are further formed. Then, the front substrate and the rear substrate are disposed opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  The plasma display device displays images by applying sustain pulses alternately to the display electrode pairs to discharge and emit light from these discharge cells.

  In order to stably generate a sustain discharge in each discharge cell, it is necessary to apply a sustain pulse having a steep shape with an amplitude of typically several hundreds of volts and a rise time of 1 μsec or less to the display electrode pair. At this time, for example, if the display screen size is a panel corresponding to 40 inches, a large current exceeding several tens of amperes flows instantaneously. Therefore, to reduce the impedance of the current path from the drive circuit to each power supply and each electrode so that ringing or the like is not superimposed on the sustain pulse, and to reduce the ground impedance to prevent malfunction. It is important to devise the arrangement, wiring, etc. For example, Patent Document 1 discloses a plasma display device in which the arrangement of driving circuits and wiring thereof are devised to reduce parasitic inductance and to reduce ringing of the voltage waveform of the panel.

JP 2008-40408 A

  However, as the screen of the panel further increases, the displacement current for charging and discharging the panel capacity and the discharge current accompanying the discharge increase in proportion to the square of the display screen size, and the slight impedance of the current path is also imaged. It has become a factor that degrades display quality. As the screen of the panel increases, the difference in the impedance of the current path from the drive circuit to each display electrode pair also increases, but the difference in image display quality due to the difference in the current path also becomes so large that it cannot be ignored. It is coming.

  In fact, when the display screen size of the panel is increased to about 100 inches, the length of the short side of the panel is 1 m or more and the length of the long side is 2 m or more. In addition to the increase, the length of the current path from the drive circuit to each of the display electrode pairs is not the same. Specifically, wiring can be made relatively short up to the display electrode pair at the center of the panel, but the display electrode pair at the top and bottom of the panel is long. For this reason, there has been a problem that large ringing is superimposed on the drive voltage waveforms of the display electrode pairs located at the upper and lower parts of the panel, resulting in luminance unevenness, color unevenness, and the like, and image display quality is deteriorated.

  The present invention has been made in view of these problems, and provides a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of a pair of display electrodes even in a large-screen panel. The purpose is to provide.

  To achieve the above object, the present invention has a panel in which discharge cells are formed at intersections between a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and sustain pulses are applied to the scan electrode and the sustain electrode in the sustain period. Display apparatus for displaying an image by applying a sustain pulse generating circuit board having a sustain pulse generating circuit for generating a sustain pulse to be supplied to a scan electrode, and supplying a sustain pulse to each of the scan electrodes And a circuit for clamping the voltage of the wiring for supplying the sustain pulse of the sustain pulse supply circuit board so that it does not exceed the voltage on the high voltage side of the sustain pulse during the sustain period. It is characterized by that. With this configuration, it is possible to provide a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of the display electrode pairs even in a large-screen panel.

  Further, the sustain pulse supply circuit board of the plasma display device of the present invention may be equipped with a scan pulse generating circuit for generating a scan pulse.

  The plasma display device of the present invention may further include a clamp circuit that clamps the potential of the wiring that supplies the sustain pulse of the sustain pulse supply circuit board so that it does not become less than the voltage on the low voltage side of the sustain pulse during the sustain period. Good.

  According to the present invention, it is possible to provide a plasma display device that can display a high-quality image by supplying a desired drive voltage waveform to each of the display electrode pairs even in a large-screen panel.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a figure which shows the drive voltage waveform applied to each electrode of the panel of the same plasma display apparatus. It is a circuit block diagram of the plasma display device. It is a figure which shows the circuit block of the scanning electrode drive circuit mounted in the some circuit board of the plasma display apparatus. It is a disassembled perspective view which shows the structure of the plasma display apparatus. It is a figure which shows arrangement | positioning of the circuit board of the plasma display apparatus in Embodiment 2 of this invention. It is a figure which shows the circuit block of the scanning electrode drive circuit of the plasma display apparatus in Embodiment 3 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. In panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) that are long in the row direction are arranged and long in the column direction. m data electrodes D1 to Dm (data electrode 22 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a method for driving the panel 10 will be described. In the present embodiment, a so-called subfield method is used as a method of displaying a gradation corresponding to an image signal. In the subfield method, one field period is divided into a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by controlling light emission / non-light emission of each discharge cell for each subfield. It is.

  FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows drive voltage waveforms for the three subfields SF1 to SF3, but the drive voltage waveforms in the other subfields are substantially the same.

  In the initializing period of subfield SF1, voltage 0 (V) is applied to data electrodes D1 to Dm and sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn are ramped up gradually from voltage Vi1 to voltage Vi2. Apply voltage. Thereafter, voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs in each discharge cell, and wall charges necessary for the subsequent address operation are formed on each electrode.

  Note that as the operation in the initialization period, as shown in the initialization period of the subfields SF2 and SF3, it is only necessary to apply a ramp voltage that gradually decreases to the scan electrodes SC1 to SCn.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, voltage Vc is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to data electrodes D1 to Dm.

  Then, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge is generated in the discharge cells in the first row to which the scan pulse and the address pulse are simultaneously applied, and an address operation for accumulating wall charges on the scan electrode SC1 and the sustain electrode SU1 of the discharge cell is performed.

  The above addressing operation is repeated in all rows of discharge cells, and address discharge is selectively generated in the discharge cells to emit light to form wall charges.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrodes SU1 to SUn. Then, a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred and emits light. Next, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the sustain discharge occurs again to emit light. Thereafter, sustain pulses corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn to cause the discharge cells to emit light. At the end of the sustain period, a ramp voltage that gradually rises toward voltage Vr is applied to scan electrodes SC1 to SCn, and the positive wall voltage on data electrode Dk is left and maintained on scan electrode SCi. The wall voltage on the electrode SUi is weakened. Thus, the maintenance operation in the maintenance period is completed.

  Along with the sustain discharge described above, a discharge current corresponding to the number of discharge cells that have caused discharge flows. For example, if discharge occurs in all the discharge cells, a very large current exceeding several tens of amperes instantaneously flows. Furthermore, when the display screen size is about 100 inches, a very large current reaches several hundred amperes. In order to flow such a large current, it is necessary to reduce the impedance of the current path from each electrode drive circuit to each power source and each electrode. In particular, the current path to the upper and lower display electrode pairs on the display screen tends to be long and the impedance tends to be high.

  Although details will be described later, in the present embodiment, a circuit is provided for reducing ringing by lowering the impedance of the current path with respect to the scan electrodes located at the upper and lower portions of the display screen.

  The operation of the subsequent subfield is substantially the same as the operation of the first subfield, and thus description thereof is omitted.

  FIG. 4 is a circuit block diagram of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10 and a drive circuit. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and each circuit block. Is provided with a power supply circuit 36 for supplying necessary power.

  The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 32 converts the image data for each subfield into address pulses applied to the data electrodes D1 to Dm. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks.

  Scan electrode driving circuit 33 generates sustain pulse generation circuit 41 for generating a sustain pulse in the sustain period, initialization waveform generation circuit 42 for generating a ramp waveform voltage in the initialization period, and generates a scan pulse in the write period. A scan pulse generation circuit 43 is provided to drive each of the scan electrodes SC1 to SCn based on the timing signal. Sustain electrode drive circuit 54 has a sustain pulse generation circuit for generating a sustain pulse in the sustain period, and drives sustain electrodes SU1 to SUn based on a timing signal. These drive circuits are mounted on a plurality of circuit boards.

  Although these drive circuits are mounted on a circuit board, the size of a printed circuit board that can be normally used is about 50 cm on a side at most, and therefore, the data electrode drive circuit 32, the scan electrode drive circuit 33, and the sustain electrode drive circuit 34. Are mounted on a plurality of printed circuit boards.

  FIG. 5 is a diagram showing a circuit block of scan electrode driving circuit 33 mounted on a plurality of circuit boards of plasma display device 30 in accordance with the first exemplary embodiment of the present invention. Scan electrode driving circuit 33 has sustain pulse generating circuit board 51 (hereinafter simply referred to as “circuit board 51”) mounted with sustain pulse generating circuit 41 for generating sustain pulses to be supplied to the scan electrodes and initialization waveform generating circuit. And a sustain pulse supply circuit board 52 (hereinafter simply abbreviated as “circuit board 52”) and a sustain pulse for mounting the scan pulse generation circuit 43 and supplying the sustain pulse to each of the scan electrodes. A supply circuit board 53 (hereinafter simply referred to as “circuit board 53”) is provided.

  A sustain pulse generation circuit 41 and an initialization waveform generation circuit 42 are mounted on the circuit board 51. On circuit board 52, scan pulse generating circuit 43 corresponding to scan electrodes SC1 to SCn / 2 is mounted. On circuit board 53, scan pulse generating circuit 43 corresponding to scan electrodes SCn / 2 + 1 to SCn is mounted.

  The sustain pulse generated by the sustain pulse generation circuit 41 is transmitted from the output terminal P1 of the circuit board 51 to the input terminal P2 of the circuit board 52, and is mounted on the wiring for supplying the sustain pulse of the circuit board 52 and the circuit board 52. The voltage is applied to each of scan electrodes SC1 to SCn / 2 via scan pulse generation circuit 43.

  Here, the input terminal P2 is provided above the wiring for supplying the sustain pulse of the circuit board 52 and in the vicinity of the scan electrode SCn / 2 located in the center of the panel 10, and the scan electrode SCn / 2 and A sustain pulse can be applied to a scan electrode in the vicinity thereof through a short current path. Therefore, a sustain pulse with little ringing can be applied. However, the current path of the wiring for supplying the sustain pulse becomes longer as it goes to the upper part of the panel 10, and ringing having a non-negligible magnitude is superimposed on the sustain pulse applied to scan electrode SC1 and the nearby scan electrode.

  Therefore, in order to suppress this ringing, the first clamping circuit clamps the potential of the wiring for supplying the sustain pulse of the sustain pulse supplying circuit board 52 so as not to exceed the voltage Vs on the high voltage side of the sustain pulse in the sustain period. 44 is provided. That is, the first clamp circuit 44 is provided on the circuit board 54 and is located above the wiring for supplying the sustain pulse of the circuit board 52 and is connected to the point P4 having the same potential as the input terminal P2.

  In the present embodiment, the first clamp circuit 44 includes a diode D62 and a switching element Q62. Then, by turning on switching element Q62 during the sustain period, the voltage applied to scan electrode SC1 and the scan electrode in the vicinity thereof is clamped so as not to exceed voltage Vs. A sustain pulse with little ringing can be applied.

  Similarly, the sustain pulse generated by the sustain pulse generation circuit 41 is transmitted from the output terminal P1 of the circuit board 51 to the input terminal P3 of the circuit board 53, and is scanned through the scan pulse generation circuit 43 mounted on the circuit board 53. Applied to each of the electrodes SCn / 2 + 1 to SCn.

  Here, input terminal P3 is provided in the vicinity of scan electrode SCn / 2 + 1 located at the center of panel 10, and sustain pulse is applied to scan electrode SCn / 2 + 1 and the scan electrode in the vicinity thereof through a short current path. be able to. Therefore, a sustain pulse with little ringing can be applied. However, the current path becomes longer as it goes to the lower part of the panel 10, and ringing having a non-negligible magnitude is superimposed on the sustain pulse applied to the scan electrode SCn and the nearby scan electrode.

  Therefore, in order to suppress this ringing, the second clamp circuit clamps the potential of the wiring for supplying the sustain pulse of the sustain pulse supply circuit board 53 so as not to exceed the voltage Vs on the high voltage side of the sustain pulse in the sustain period. 45 is provided. That is, the second clamp circuit 45 for clamping with the voltage Vs which is the high voltage side voltage of the sustain pulse is provided on the circuit board 55, and is positioned below the wiring for supplying the sustain pulse of the circuit board 53, and the input terminal P3. Are connected to a point P5 having the same potential as

  In the present embodiment, the second clamp circuit 45 includes a diode D63 and a switching element Q63. Then, by turning on switching element Q63 during the sustain period, a sustain pulse with less ringing can be applied to the scan electrode located at the bottom of panel 10 as well.

  FIG. 6 is an exploded perspective view showing the structure of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, a chassis 61 that holds the panel 10, a heat conduction sheet 62 that adheres the panel 10 and the chassis 61, and transmits heat generated in the panel 10 to the chassis 61. A circuit board group 63 for driving the panel 10, such as a power supply circuit, a scan electrode drive circuit, a sustain electrode drive circuit, and a timing generation circuit, and a front frame 65 and a back cover 66 for housing them are provided. In FIG. 6, among the circuit board group 63, the circuit boards 51 to 55 on which the scan electrode driving circuit 33 is mounted are indicated with reference numerals.

  In this way, the circuit board 54 on which the first clamp circuit 44 is mounted is attached in the vicinity of the point P4 of the circuit board 52 on which the scan pulse generating circuit 43 is mounted, and the circuit board 55 on which the second clamp circuit 45 is mounted is attached. By attaching to the vicinity of the point P5 of the circuit board 53 on which the scan pulse generating circuit 43 is mounted, a sustain pulse with little ringing can be applied to the scan electrodes located at the upper and lower portions of the panel 10.

  In the present embodiment, circuit boards 54 and 55 on which a clamp circuit is mounted are provided on each of the circuit boards 52 and 53 on which the scan pulse generation circuit 43 is mounted. However, the clamp circuit 44 may be mounted on the circuit board 52 and the clamp circuit 45 may be mounted on the circuit board 53. In addition, a clamp circuit for each of the circuit boards 52 and 53 may be mounted on one circuit board.

  In the present embodiment, a voltage exceeding the voltage Vs (for example, the voltage Vi2) is applied to the scan electrode 22. However, when a voltage exceeding the voltage Vs is not applied to the scan electrode 22, the switching element Q62 of the clamp circuit 44 and the switching element Q63 of the clamp circuit 45 are not necessary. Therefore, the on-resistance at the time of clamping is only the on-resistance of the diode D62 or the on-resistance of the diode D63, so that the sustain pulse ringing can be further suppressed.

(Embodiment 2)
FIG. 7 is a diagram showing the arrangement of the circuit boards of the plasma display device 30 according to the second exemplary embodiment of the present invention, and schematically shows the arrangement of each circuit board viewed from the back cover 66 side with the back cover 66 removed. FIG. Mounted on the circuit board 56 are both the first clamp circuit 44 composed of the diode D62 and the switching element Q62 and the second clamp circuit 45 composed of the diode D63 and the switching element Q63. Has been.

  The point P4 of the circuit board 52 and the clamp circuit 44 are connected by a wiring 56a, and the point P5 of the circuit board 53 and the clamp circuit 45 are connected by a wiring 56b. As described above, even when the two clamp circuits 44 and 45 are mounted on the single circuit board 56, the ringing of the sustain pulse applied to the scan electrodes located at the upper and lower portions of the panel 10 can be suppressed. At this time, it is more desirable that the circuit board 56 on which the two clamp circuits are mounted be disposed near the power supply board 59 that generates the voltage Vs.

(Embodiment 3)
FIG. 8 is a diagram showing a circuit block of scan electrode drive circuit 33 of plasma display device 30 in the third exemplary embodiment of the present invention.

  In the present embodiment, the first clamp circuit 46 includes a diode D62 and a switching element for clamping the potential of the wiring for supplying the sustain pulse of the circuit board 52 so as not to exceed the voltage Vs on the high voltage side of the sustain pulse. In addition to the clamp circuit configured by Q62, a clamp circuit configured by a diode D72 and a switching element Q72 for clamping the sustain pulse so as not to be less than the voltage 0 (V) on the low voltage side of the sustain pulse is provided. .

  Similarly, the second clamp circuit 47 includes a diode D63 and a switching element Q63 for clamping the potential of the wiring for supplying the sustain pulse of the circuit board 53 so as not to exceed the voltage Vs on the high voltage side of the sustain pulse. In addition to the clamp circuit, a clamp circuit including a diode D73 and a switching element Q73 for clamping the sustain pulse so as not to be less than the voltage 0 (V) which is a voltage on the low voltage side of the sustain pulse is provided.

  Thereby, in addition to the ringing that occurs at the rising edge of the sustain pulse applied to the scan electrodes located at the upper and lower portions of the panel 10, the ringing that occurs at the falling edge can also be suppressed.

  Note that the first clamp circuit 46 may be mounted on the circuit board 52 and the second clamp circuit 47 may be mounted on the circuit board 53. Alternatively, the first clamp circuit 46 and the second clamp circuit 47 are mounted on separate circuit boards, the circuit board on which the first clamp circuit 46 is mounted is attached in the vicinity of the point P4 of the circuit board 52, and the first The circuit board 55 on which the two clamp circuits 47 are mounted may be attached in the vicinity of the point P5 of the circuit board 53. Further, both the clamp circuits of the first clamp circuit 46 and the second clamp circuit 47 are mounted on a single circuit board, the point P4 of the circuit board 52 and the clamp circuit 46 are connected by wiring, and the circuit board The point P5 of 53 and the clamp circuit 47 may be connected by wiring.

  In the first to third embodiments, it goes without saying that the ringing suppression effect is further improved by providing a decoupling capacitor for the voltage Vs near the clamp circuit.

  In addition, the specific numerical values used in the first to third embodiments are merely examples, and may be appropriately set to optimal values according to the panel characteristics, the specifications of the plasma display device, and the like. desirable.

  The present invention is useful as a plasma display device because even a large-screen panel can supply a desired drive voltage waveform to each display electrode pair to display a high-quality image.

DESCRIPTION OF SYMBOLS 10 (Plasma display) panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 21 Back substrate 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 36 Power supply circuit 41 Sustain pulse generation circuit 42 Initialization waveform generation circuit 43 Scan pulse generation circuit 44, 46 First clamp circuit 45, 47 Second clamp circuit 41 Sustain pulse generation circuit 41 Sustain pulse generation circuit 51 (for sustain pulse generation) ) Circuit board 52, 53 (for sustain pulse supply) Circuit board 54, 55, 56 Circuit board

Claims (3)

It has a plasma display panel in which discharge cells are formed at the intersection of the display electrode pair consisting of the scan electrode and the sustain electrode and the data electrode, and displays an image by applying a sustain pulse to the scan electrode and the sustain electrode in the sustain period A plasma display device,
A sustain pulse generating circuit board equipped with a sustain pulse generating circuit for generating a sustain pulse to be supplied to the scan electrode, and a sustain pulse supplying circuit board for supplying the sustain pulse to each of the scan electrodes;
2. A plasma display, comprising: a clamp circuit that clamps a potential of a wiring for supplying the sustain pulse of the sustain pulse supply circuit board so as not to exceed a voltage on a high voltage side of the sustain pulse in the sustain period. apparatus. The plasma display apparatus according to claim 1, wherein the sustain pulse supply circuit board includes a scan pulse generation circuit for generating a scan pulse. The clamp circuit for clamping the potential of the wiring for supplying the sustain pulse of the sustain pulse supply circuit board so as not to become less than the voltage on the low voltage side of the sustain pulse in the sustain period. 2. The plasma display device according to 1.

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