JP2007266151A - Compound semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly efficient compound semiconductor device with less energy loss. <P>SOLUTION: An n-type low carrier concentration layer 2 with a carrier concentration as ≥10<SP>11</SP>/cm<SP>3</SP>and ≤10<SP>16</SP>/cm<SP>3</SP>, a p-type layer 3 with the carrier concentration as ≥10<SP>11</SP>/cm<SP>3</SP>and ≤10<SP>21</SP>/cm<SP>3</SP>, and an n-type high carrier concentration layer 4 with the carrier concentration ≥10<SP>16</SP>/cm<SP>3</SP>and ≤10<SP>21</SP>/cm<SP>3</SP>, are sequentially laminated on a low resistance substrate 1. The respective layers 2-4 are made to be 3C-SiC single crystal with the fault density of not more than 10<SP>4</SP>/cm<SP>2</SP>concerning a micropipe, a double-positioning domain, an anti-phase domain, a stacking fault, and a twin band. The compound semiconductor device also includes: a gate insulating film 5 which contacts at least the p-type layer 3, a control electrode 6 which contacts the gate insulating film 5 and is electrically separated from the respective layers 2-4, an upper electrode 7 which contacts at least the p-type layer 3 and the n-type high carrier concentration layer 4, and a lower electrode 8 which contacts the low resistance substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a low-loss compound semiconductor device made of cubic silicon carbide (3C—SiC) single crystal.

SiC has excellent characteristics such as a wide band gap, high electron mobility, and high heat resistance, is rich in the amount of constituent elements, and has little concern about environmental pollution. It is a material expected to be applied as a compound semiconductor in next-generation electronic devices, electronic devices capable of high-speed and high-temperature operation, solar power generation devices, and the like.
For this reason, the compound semiconductor using SiC is promising as it surpasses the physical property limit of the semiconductor silicon which is currently mainstream.

Conventionally known MOSFETs using hexagonal SiC typified by 4H—SiC and 6H—SiC are known as compound semiconductor devices using SiC as described above (see, for example, Patent Document 1).
JP-A-8-8429

The MOSFET induces carriers in the vicinity of the contact portion between the insulating film and the compound semiconductor by an electrostatic force, and electrical conduction occurs by the induced carriers, that is, by movement of carriers in the channel.
However, the compound semiconductor device using the conventional hexagonal SiC as described in Patent Document 1 has a problem that the resistance in the channel is high. When the channel resistance is high, the energy loss during device operation increases.
For this reason, various attempts have been made to change the crystal orientation of hexagonal SiC in order to reduce the resistance of the channel, but a practical level has not yet been obtained.

  The present invention has been made to solve the above descriptive problem, and an object of the present invention is to provide a highly efficient compound semiconductor device with little energy loss.

Compound semiconductor device according to the present invention, the low-resistance substrate, the carrier concentration of 10 ¹¹ / cm ³ or more and 10 ¹⁶ / cm ³ or less of the n-type low carrier concentration layer, the carrier concentration of 10 ¹¹ / cm ³ or more 10 ²¹ / cm ³ or less p-type layer and an n-type high carrier concentration layer having a carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less are sequentially laminated, and the n-type low carrier concentration layer, the p-type layer and the n-type high carrier layer are stacked. Each of the carrier concentration layers is made of 3C—SiC single crystal having a defect density of 10 ⁴ / cm ² or less of micropipe, double positioning domain, antiphase domain, stacking fault, and twin band, and at least the p-type. A gate insulating film in contact with the layer, and any of the n-type low carrier concentration layer, the p-type layer, and the n-type high carrier concentration layer in contact with the gate insulating film A control electrode provided in a gas separation, an upper electrode in contact with at least the p-type layer and the n-type high carrier concentration layer, and a lower electrode in contact with the low-resistance substrate; To do.
In the 3C-SiC single crystal layer, which is isotropic compared to hexagonal SiC, by suppressing defects that hinder carrier movement in the channel, carrier mobility can be increased and channel resistance can be reduced. .

In the compound semiconductor device, the low resistance substrate is preferably an n-type or p-type high carrier concentration SiC single crystal substrate having a carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less.
In particular, the SiC single crystal substrate is preferably a 3C-SiC single crystal substrate.
By using the low resistance substrate as described above, the lattice matching with the upper layer made of the 3C—SiC single crystal layer is improved, so that the occurrence of defects due to lattice mismatch or the like can be suppressed.

The n-type low carrier concentration layer has a thickness of 10 μm to 100 μm, the p-type layer has a thickness of 0.01 μm to 2 μm, and the n-type high carrier concentration layer has a thickness of 0.01 μm to 2 μm. It is preferable that
When the thickness of each of the layers is thin, a desired breakdown voltage cannot be secured, while when it is too thick, an increase in resistance is promoted.

Furthermore, it is preferable that the gate insulating film is in contact with the n-type low carrier concentration layer, the p-type layer, and the n-type high carrier concentration layer.
Thereby, when a voltage is applied to the control electrode, it is possible to effectively form a channel and reduce the resistance.

Further, from the viewpoint of lowering connection resistance, the connection portion between the p-type layer and the upper electrode preferably has a high carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less.

  As described above, the compound semiconductor device according to the present invention is composed of a high-quality 3C-SiC single crystal layer with excellent crystallinity and few defects, and has high carrier mobility and low loss. It can be suitably used as a high-power electronic device or the like.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
FIG. 1 shows one embodiment of a compound semiconductor device according to the present invention. Compound semiconductor device shown in FIG. 1, on the low-resistance substrate 1, a carrier concentration of 10 ¹¹ / cm ³ or more 10 ¹⁶ / cm ³ or less of the n-type low carrier concentration layer 2, the carrier concentration of 10 ¹¹ / cm ³ or more 10 ²¹ / cm ^{3 or} less p-type layer 3, made of the configuration and the carrier concentration of 10 ¹⁶ / cm ³ or more 10 ²¹ / cm ³ or less of the n-type high carrier concentration layer 4 are sequentially laminated.
Each of the n-type low carrier concentration layer 2, the p-type layer 3, and the n-type high carrier concentration layer 4 has micropipe, double positioning domain, antiphase domain, stacking fault, and twin band defect densities. It consists of 3C-SiC single crystal of 10 ⁴ / cm ² or less.
Furthermore, at least the gate insulating film 5 in contact with the p-type layer 3, the n-type low carrier concentration layer 2, the p-type layer 3, and the n-type high carrier concentration layer 4 in contact with the gate insulating film 5. A control electrode 6 provided electrically separated, an upper electrode 7 in contact with at least the p-type layer 3 and the n-type high carrier concentration layer 4, and a lower electrode 8 in contact with the low-resistance substrate 1 are provided. It is characterized by that.
In FIG. 1, the gate insulating film 5 is in contact with the n-type low carrier concentration layer 2, the p-type layer 3 and the n-type high carrier concentration layer 4.

The crystal structure of 3C-SiC is isotropic compared to hexagonal SiC, and the carrier mobility in the channel is potentially high, and the micropipe, double positioning domain, antiphase domain, stacking fault The twin band is a defect that suppresses carrier movement in the 3C-SiC channel.
For this reason, according to the compound semiconductor device of the above structure, resistance can be reduced to 1/10 of the conventional.

In the compound semiconductor device, the low-resistance substrate 1 is an n-type or p-type high carrier concentration SiC single crystal substrate having a carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less, particularly a 3C-SiC single crystal substrate. Preferably there is.

  When the low-resistance substrate 1 is an n-type high carrier concentration SiC single crystal substrate, the lattice matching with the upper layers 2 to 4 made of the 3C-SiC single crystal layer becomes good. The occurrence of defects can be suppressed, and the resistance can be reduced to 1/50 compared to conventional compound semiconductor devices.

  Further, even when the low-resistance substrate 1 is a p-type high carrier concentration SiC single crystal substrate, the lattice matching with the upper layers 2 to 4 made of the 3C-SiC single crystal layer is improved, resulting in lattice mismatch and the like. It is possible to suppress the occurrence of the resulting defect. Furthermore, in this case, since the conductivity can be modulated by injecting holes from the low-resistance substrate 1 during device operation, the energy loss of the compound semiconductor device can be reduced. As compared with the above, the resistance can be reduced to 1/100.

2A to 2G show an example of a manufacturing process of a compound semiconductor device according to another embodiment of the present invention. Hereinafter, the method for manufacturing a compound semiconductor device according to the present invention will be described with reference to FIGS. In addition, the manufacturing method of the compound semiconductor device which concerns on this invention is not limited to this.
The compound semiconductor device shown in FIG. 2G has a trench structure.
First, as a low-resistance substrate 1, a 3C—SiC single crystal substrate having a crystal plane orientation {111}, a carrier concentration of 10 ¹⁷ / cm ³ , a conductivity type n-type, and a thickness of 400 μm is heat-treated at 1000 ° C. in a hydrogen atmosphere. Clean the surface.
Note that the method for manufacturing the 3C—SiC single crystal substrate is not particularly limited, and can be obtained by a vapor deposition method, a sublimation method, or the like.

On the low-resistance substrate 1, by vapor phase growth method, SiH ₄ gas and C ₃ H ₈ gas are used as source gases at 1000 ° C., thickness 20 μm, carrier concentration 10 ¹⁵ / cm ³ , conductive n-type an n-type low carrier concentration layer 2, a thickness of 1 [mu] m, and p-type layer 3 of the carrier concentration of 10 ¹⁷ / cm ^3, a thickness of 1 [mu] m, and an n-type high carrier concentration layer 4 having a carrier concentration 10 ¹⁷ / cm ³ sequential Laminate (see FIG. 2A).

  The defect density of micropipe, double positioning domain, antiphase domain, stacking fault and twin band in these n-type low carrier concentration layer 2, p-type layer 3 and n-type high carrier concentration layer 4 is It can be controlled by adjusting the growth conditions of each layer such as the temperature in the vapor phase growth, the supply amount of hydrogen and source gas, and the like.

Further, the carrier concentration and conductivity type of each layer are controlled by adjusting and adding the kind and amount of dopant during vapor phase growth. Examples of the n-type dopant include N ₂ and PH ₃ , and examples of the p-type dopant include B ₂ H ₆ and trimethylammonium (TMA).
Alternatively, it can be controlled by implanting impurity ions by an implantation method after vapor phase growth.
In the implantation method, the concentration of impurity ions to be partially implanted can be adjusted by performing masking in advance. Therefore, by using this, a compound semiconductor device in which the conductivity type and the carrier concentration are partially adjusted can be used. It is also possible to configure.

Next, after a resist mask 10 is formed at a desired position on the n-type high carrier concentration layer 4 by lithography, a groove having a depth of 20 μm is dug by reactive ion etching to form side and bottom surfaces. (See FIG. 2 (b)).
As a method for forming the desired side and bottom surfaces, a method of forming a groove by an etching method, a deposition method by a selective epi method, or the like can be used.

After removing the resist mask 10, a SiO ₂ film (gate insulating film) 5 having a thickness of 100 nm was formed in the formed groove by thermal oxidation in an oxygen atmosphere at 1000 ° C. The gate insulating film 5 is in contact with the n-type low carrier concentration layer 2, the p-type layer 3, and the n-type high carrier concentration layer 4 (see FIG. 2C).
The gate insulating film 5 may be formed by SiO ₂ , SiN _x or the like by a CVD method or a PVD method.

Next, a control electrode 6 that is in contact with the gate insulating film 5 and is electrically isolated from any of the n-type low carrier concentration layer 2, the p-type layer 3, and the n-type high carrier concentration layer 4 is formed by CVD. By using this method, polysilicon is used (see FIG. 2D).
A resist mask 11 is formed on the control electrode 6 by lithography, and unnecessary polysilicon and SiO ₂ films are removed by etching (see FIG. 2E).

Then, after removing the resist mask 11, a resist mask 12 is again formed at a predetermined position by lithography, and an upper electrode 7 made of Ni in contact with the n-type high carrier concentration layer 4 is formed by electron beam method. (See FIG. 2 (f)).
Further, the lower electrode 8 in contact with the low resistance substrate 1 is formed by an electron beam method (see FIG. 2G).
In addition, electrode formation can also be performed by a vacuum evaporation method, PVD method, etc.

It is sectional drawing which showed typically an example of the compound semiconductor device which concerns on this invention. It is sectional drawing typically shown in order to demonstrate an example of the manufacturing process of the compound semiconductor device which concerns on this invention.

Explanation of symbols

1 Low resistance substrate 2 n-type low carrier concentration layer 3 p-type layer 4 n-type high carrier concentration layer 5 Gate insulating film (SiO ₂ film)
6 Control electrode 7 Upper electrode 8 Lower electrode 10, 11, 12 Resist mask

Claims (6)

The low-resistance substrate, and the carrier concentration of 10 ¹¹ / cm ³ or more 10 ¹⁶ / cm ³ or less of the n-type low carrier concentration layer, and the carrier concentration of 10 ¹¹ / cm ³ or more 10 ²¹ / cm ³ or less of p-type layer, the carrier An n-type high carrier concentration layer having a concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less is sequentially laminated;
The n-type low carrier concentration layer, the p-type layer, and the n-type high carrier concentration layer all have a defect density of 10 ⁴ / cm in micropipes, double positioning domains, antiphase domains, stacking faults, and twin bands. ² or less 3C-SiC single crystal,
A gate insulating film in contact with at least the p-type layer, and in contact with the gate insulating film, and electrically separated from any of the n-type low carrier concentration layer, the p-type layer, and the n-type high carrier concentration layer A compound semiconductor device comprising: a control electrode provided; an upper electrode in contact with at least the p-type layer and the n-type high carrier concentration layer; and a lower electrode in contact with the low-resistance substrate. 2. The compound semiconductor device according to claim 1, wherein the low-resistance substrate is an n-type or p-type high carrier concentration SiC single crystal substrate having a carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less.   The compound semiconductor device according to claim 2, wherein the SiC single crystal substrate is a 3C—SiC single crystal substrate.   The n-type low carrier concentration layer has a thickness of 10 μm to 100 μm, the p-type layer has a thickness of 0.01 μm to 2 μm, and the n-type high carrier concentration layer has a thickness of 0.01 μm to 2 μm. The compound semiconductor device according to any one of claims 1 to 3, wherein   5. The compound semiconductor according to claim 1, wherein the gate insulating film is in contact with the n-type low carrier concentration layer, the p-type layer, and the n-type high carrier concentration layer. device. 6. The connection part between the p-type layer and the upper electrode has a high carrier concentration of 10 ¹⁶ / cm ³ or more and 10 ²¹ / cm ³ or less. The compound semiconductor device described.

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