JP2007243444A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor which can access a register without being influenced by a state of other image processing blocks, and without forming a space more than necessary between pages. <P>SOLUTION: In the image processor, when accessing the register inside each image processing block in an image processing chip, a bus to be used for transferring a command packet sent from the CPU within the image processing chip and within each image processing block can be automatically switched between a command bus 2109 and a data bus 2107. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a configuration of an image processing LSI that inputs digital image data and performs image processing.

  In the conventional image processing LSI, when register setting is performed for each internal image processing module, the processing is waited for to be completed. For example, the register setting for the next page is performed after the processing of a certain page is completed, and the processing of the next page is started after all the register settings are completed. This is because if the register setting is changed before the corresponding image processing module completes the processing, for example, the image quality before and after the register setting is different within the same page.

As another conventional example, Patent Document 1 can be cited.
Japanese Patent Laid-Open No. 2004-253906

  In the conventional technique, when the number of times of register setting is large, the time required for register setting becomes long, and as a result, the interval / time between pages becomes empty. As a result, the performance of the device using the image processing LSI is degraded.

  In order to solve this problem, an image processing apparatus having a configuration capable of transferring a command packet onto a data bus has been proposed in Patent Document 1. In this document, all commands for register access are proposed. Since this is a system that inserts and transfers packets between data packets, when multiple image processing modules are connected in series to form an image processing sequence, it takes time to process in one image processing unit. If this is the case, there is a problem that register access to other image processing units is delayed.

  In addition, in this document, there is still a problem that read access to the register is impossible.

  In the present invention, in order to solve the above problems, the following configuration is prepared.

A data bus for mainly transferring image data, a command bus for transferring command data, and at least one image for performing respective image processing on the data bus and the image data connected to the command bus and transferred. An image having a processing module, a distribution module for distributing command data and image data to the command bus or the data bus and transferring them upstream of the image processing block, and an input / output I / F unit for inputting / outputting data to / from the outside In the processing device,
The image data is transferred as a data packet divided into rectangles of a predetermined size, and the child F-degree data is transferred as a command packet divided into data lengths of a predetermined size.
Processing is performed on a packet basis,
Based on the predetermined information in the packet header information included in the packet, the distribution module distributes the packet to either the data bus or the command bus and transfers the data in each image processing module. An image processing apparatus having means for transferring data / command packets transferred via a bus to an image processing unit / register, respectively.

  As described above, according to the present invention, the command packet can be transferred via the image bus when it is desired to synchronize with the image data, and can be transferred via the command bus when the command packet is desired to be transmitted independently. It is possible to change the register settings without having to do so, but there is an image processing module with heavy processing on the image bus, and even if it is desired to perform register access to the downstream module, it can be accessed at any timing. .

  Next, details of the present invention will be described in accordance with the description of the embodiments.

[Whole system]
A configuration diagram of the entire network system of the present invention is shown in FIG.

  An image 1001 includes a scanner and a printer. An image read from the scanner can be sent to a local area network (1010) (hereinafter referred to as LAN), and an image received from the LAN can be printed out by a printer. Further, an image read from the scanner can be transmitted to PSTN or ISDN (1030) by a FAX transmission means (not shown), and an image received from PSTN or ISDN can be printed out by a printer. Reference numeral 1002 denotes a database server that manages binary images and multi-valued images read by the apparatus (1001) of the present invention as a database.

  Reference numeral 1003 denotes a database client of the database server (1002), which can browse / search image data stored in the database (1002).

  An e-mail server 1004 can receive an image read by the apparatus (1001) of the present invention as an e-mail attachment. Reference numeral 1005 denotes an e-mail client that can receive and browse e-mails received by the e-mail server (1004) and send e-mails.

  Reference numeral 1006 denotes a WWW server that provides an HTML document to the LAN, and an HTML document provided by the WWW server can be printed out by the apparatus (1001) of the present invention.

  Reference numeral 1007 denotes a router that connects the LAN (1010) to the Internet / intranet (1012). The database server (1002), the WWW server (1006), the e-mail server (1004), and the device similar to the device (1001) of the present invention are connected to the Internet / intranet as 1020, 1021, 1022, and 1023, respectively. ing. On the other hand, the apparatus (1001) of the present invention can transmit and receive with the FAX apparatus (1031) via the PSTN or ISDN (1030).

  Also, a printer (1040) is connected to the LAN, and is configured to print out an image read by the apparatus (1001) of the present invention.

[Description of controller]
FIG. 2 is a block diagram of an image processing apparatus that best represents the present invention.

  The image ring (2008) is composed of a combination of a pair of unidirectional connection paths (image ring 1 and image ring 2). The image ring (2008) includes a tile expansion unit (2103), a packet distribution unit (2104), a status via the image ring interface 3 (2101) and the tile image interface 4 (2102) in the tile image processing unit (2149). The processing unit (2105) is connected to the tile compression unit (2106).

  The tile expansion unit (2103) is connected to the packet distribution unit (2104) and the data bus (2107) in addition to the connection to the image ring interface, and expands the compressed image data input from the image ring, Transfer to (2107). In the present embodiment, an example is shown in which JPEG is used as multi-value data and Pacbits are used as decompression algorithms for binary data.

  In addition to connecting to the image ring interface, the tile compression unit (2106) is connected to the data bus (2107), compresses the uncompressed image data input from the data bus, and transfers it to the image ring (2008). It is a bridge. In the present embodiment, an example is shown in which JPEG is used as multi-value data and Pacbits are used as compression algorithms for binary data.

  The packet distribution unit (2104) is connected to the command bus (2109) and the tile expansion unit (2103) in addition to the connection to the image ring interface, and the image data input through the image ring is input to the data bus (2107). Forward. The register setting request (command) issued by the CPU (2001) is transferred to the command bus (2109) or the data bus (2107). Also, based on the read issued by the CPU (2001), information is read from the corresponding register through the command bus. Transfer to Image Ring Interface 4 (2102).

  In addition to the above blocks, the following functional blocks are connected to the data bus (2107).

  Rendering unit interface (2110), image input interface (2112), image output interface (2113), multi-value conversion unit (2119), binarization unit (2118), color space conversion unit (2117), image rotation unit (2030) ), A resolution converter (2116).

  The rendering unit interface (2110) is an interface for inputting a bitmap image generated by a rendering unit described later. The rendering unit and the rendering unit interface are connected by a general video signal (2111). The rendering unit interface has a connection to the memory bus (2108) and the command bus (2109) in addition to the data bus (2107), and a predetermined method in which the input raster image is set via the command bus. Thus, the structure is converted into a tile image and at the same time the clock is synchronized and output to the data bus (2107).

  The image input interface (2112) receives raster image data subjected to correction image processing by a scanner image processing unit (2114), which will be described later, and inputs a structure into a tile image by a predetermined method set via a command bus. Conversion and clock synchronization are performed and output to the data bus (2107).

  The image output interface receives tile image data from the data bus, converts the structure into a raster image and changes the clock rate, and outputs the raster image to the printer image processing unit (2115).

  An image rotation unit (2030) rotates image data.

  A resolution converter (2116) changes the resolution of the image.

  A color space conversion unit (2117) converts the color space of the color and gray scale image.

  A binarization unit (2118) binarizes a multi-value (color, gray scale) image.

  A multi-value conversion unit (2119) converts a binary image into multi-value data.

  The external bus interface unit (2120) sends write and read requests issued by the CPU (2001) to the external bus 3 (2121) via the image ring interface 1, 2, 3, 4, command processing unit and command bus. This is a bus bridge that converts and outputs. In this embodiment, the external bus 3 (2121) is connected to the printer image processing unit (2115) and the scanner image processing unit (2114).

  The memory control unit (2122) is connected to the memory bus (2108), and in accordance with the request of each image processing unit, the image data is transferred to the image memory 1 and the image memory 2 (2123) by preset address division. Operations such as writing, reading, and refreshing are performed as necessary. In this embodiment, an example in which SDRAM is used as the image memory is shown.

  The scanner image processing unit (2114) performs correction image processing on the image data scanned by the scanner (2070) which is an image input device.

  The printer image processing unit performs corrected image processing for printer output, and outputs the result to the Printer (2095).

  The rendering unit (2060) expands the PDL code or the intermediate display list into a bitmap image.

[Tile image (packet) format]
In the SystemControllerUnit (2000), image data, commands from the CPU (2001), and interrupt information issued from each block are transferred in a packetized form.

  In this embodiment, two different types of packets are used: a data packet shown in FIG. 3 and a command packet shown in FIG.

Data packet (Figure 3)
Fig. 3 shows an example in which image data is divided into 32 pixel x 32 pixel Tile unit image data (3002).

  Necessary header information (3001) and image additional information (3003) are added to the image in units of Tile to form a data packet.

  Information included in the header information (3001) will be described below.

  Packet Type is distinguished by PacketType (3004) in header information (3001). PacketType (3004) includes a repeat flag. When the Data Packet image Data is the same as the previous Data Packet image Data transmitted, the Repeat Flag is set.

  ChipID (3005) indicates the ID of a target chip that transmits a packet.

  DataType (3006) indicates the data type.

  PageID (3007) indicates a page, and JobID stores Job ID (3008) for software management.

  The Tile number is a combination of the Tile coordinate (3009) in the Y direction and the Tile coordinate (3010) in the X direction, and is represented by YnXn.

  Data packets may be compressed or uncompressed. In this embodiment, as the compression algorithm, an example is shown in which JPEG is used for multi-valued colors (including multi-value gray scales) and Pacbits are used for binary values.

  The distinction between the case of being compressed and the case of non-compression is indicated by CompressFlag (3017).

  Process Instruction (3011) is left-justified and set in the processing order, and each processing unit shifts the process instruction 8 bits to the left after processing. Process Instruction (3011) stores eight sets of UnitID (3019) and Mode (3020). UnitID (3019) designates each processing unit, and Mode (3020) designates the operation mode in each processing unit. As a result, one packet can be continuously processed by eight Units.

  PacketByteLength (3012) indicates the total number of bytes of the packet.

  ImageDataByteLengh (3015) represents the number of bytes of image data, ZDataByteLength (3016) represents the number of bytes of image additional information, and ImageDataOffset (3013) and ZDataOffset (3014) represent Offset from the beginning of the data packet.

  BusSel (3021) indicates whether the data bus or the command bus is transferred in the image processing unit.

Packet Table (Figure 6)
Each packet is managed by a packet table (6001).

  The components of the Packet Table (6001) are as follows. When 5 bits are added to the value of the Table, the packet begins with Address (6002) and Packet Byte Length (6005).

Packet Address Pointer (27bit) + 5b00000 = Packet top address
Packet Length (11bit) + 5b00000 = Packet Byte Length
Packet Table (6001) and Chain Table (6010) are not divided.

The Packet Table (6001) is always arranged in the scanning direction and arranged in the order of Yn / Xn = 000/000, 000 / 001,000 / 002,. An Entry in the Packet Table (6001) uniquely indicates one Tile. In addition, the following Entry of Yn / Xmax becomes Yn + 1 / X _0.

  When the packet is exactly the same data as the previous packet, the packet is not written on the memory, and the same packet address pointer and packet length as the first entry are stored in the entry of the packet table. It becomes the form that two Table Entry points to one Packet Data. In this case, the repeat flag (6003) of the second table entry is set.

  When the packet is divided into a plurality by Chain DMA, Divide Flag (6004) is set, and the Chain Table number (6006) of the Chain Block containing the head part of the packet is set.

  An entry of the Chain Table (6010) is composed of a Chain Block Address (6011) and a Chain Block Length (6012), and 0 is stored in both the Address and Length in the last Entry of the Table.

Command Packet Format (Figure 4)
This Packet Format is for accessing the command bus (2109). By using this packet, it is possible to access the image memory (2123) from the COU (2001).

  ChipID (4004) stores an ID representing the image processing unit (2149) that is the transmission destination of the command packet.

  PageID (4007) and JobID (4008) store Page ID and Job ID for software management.

  Packet ID (4009) is represented in one dimension. Use only Data Packet X-coordinate.

  The packet byte length (4010) is fixed at 128 bytes.

  The packet data portion (4002) can store a maximum of 12 commands, with a set of address (4011) and data (4012) as one command. The command type for writing or reading is indicated by CmdType (4005), and the number of commands is indicated by Cmdnum (4006).

Tile composition (Figure 5)
In FIG. 5, it is assumed that tile coordinates and image coordinates are determined from the upper left, and that the tile coordinates and image coordinates are (0, 0) in the upper left. In FIG. 5, Tile (0, 0) or the like indicates one tile, and the numbers in parentheses indicate tile coordinates (X, Y). It is determined that the X coordinate of the tile coordinate increases from the left to the right, and the Y coordinate of the tile coordinate increases from the top to the bottom. When the paper size is A4 (horizontal), the resolution is 600 dpi, and the size of one tile is 32 × 32 pixels, one page has 220 (horizontal) × 156 (vertical) tiles.

  Packets are displayed in the order of the first data packet, command packet (register write), second data packet, command packet (register read (synchronous)), third data packet, command packet (register read (asynchronous)) The operation when input to the processing unit 2149 will be described. For the sake of explanation, these five packets are all directed to the same resolution conversion unit 2116. Hereinafter, it demonstrates in order.

  First, the first data packet is input to the image processing unit 2149 through the path of the image ring interface 1 (2147) → the image ring interface 3 (2101) using the packet DMA. The input first data packet is transferred from the image ring interface 3 (2101) to the packet distribution unit (2104).

  Next, in the packet distribution unit (2104), in the first data packet, Packet Type ID (3004), UnitID (3019) in Process Instruction (3011) in the packet header (3001), and BusSel (3021) And confirm. In this case, Packet Type ID (3004) is the data packet, UnitID (3019) is the unit ID of the tile expansion unit (2103), and BusSel (3021) is the data bus information, so this first data packet Is first sent to the tile stretcher (2103).

  During the expansion operation in the tile expansion unit (2103), a command packet (register write) is input to the packet distribution unit (2104). The packet header information in this command packet is a data packet Therefore, Packet Type ID (3004) is set to the command packet, UnitID (3019) is set to the unit ID of the tile expansion unit (2103), and BusSel (3021) is set to the data bus. For this reason, the packet distribution unit (2104) tries to transfer this command packet to the tile expansion unit (2103). However, since the tile expansion unit (2103) is processing as described above, it receives the next data. It cannot stay in the packet distribution unit.

  When the processing in the tile decompression unit (2103) is completed, the first data packet that has been decompressed is transferred to the data bus, and the command packet is transferred from the packet distribution unit (2104) to the tile decompression unit (2103) for the first time. . The transferred command is similarly transferred to the data bus. In this embodiment, since it is assumed that the command packet is not compressed, the tile expansion unit (2103) does not perform any processing.

  The first data packet and command packet (register write) transferred to the data bus are sequentially transferred to the target resolution conversion unit 2116.

  Subsequently, when the second data packet is input to the image processing unit (2149), the tile decompression unit 2103 causes the command packet (register The second data packet is transferred to the tile expansion unit (2103) unless the write) cannot be output to the data bus (2107).

  The second data packet input to the tile expansion unit (2103) is similarly expanded and output to the data bus (2107). When output to the data bus (2107), the previous command packet (register write) must have already been registered in the resolution converter 2116, so the function change to the resolution converter 2116 has been completed without fail. After that, the second data packet is automatically input to the resolution converter 2116.

  As a result, the first data packet and the second data packet are processed by the resolution conversion unit 2116 in different operation modes / settings.

  In this way, the order of the first data packet, the command packet (register write), and the second data packet is guaranteed, and the register access of the command packet is synchronized with the first data packet and the second data packet. Will be set.

  Further, the means for synchronizing the three packets uses the pipeline structure in the image processing unit 249, so that no special means are used and the interval between the packets is not increased more than necessary. Is called.

  Next, a command packet (register read (synchronization)) is input to the image processing unit 2149.

  Since the packet header information in this command packet should operate in synchronization with the data packet, Packet Type ID (3004) is the command packet, UnitID (3019) is the unit ID of the tile expansion unit (2103) BusSel (3021) is set as the data bus. Since this command packet is also transferred on the data bus, the command packet is input to the image processing unit 2149 in synchronization with the immediately preceding second data packet and immediately following third data packet. Synchronously with the register access.

  Similarly to the first and second data packets, the third data packet is also carefully processed by the tile expansion unit (2103), and then sent to the resolution conversion unit (2116) for processing.

  When a command packet (register read (asynchronous)) is input to the image processing unit 2149 after or during the third data packet, the packet type ID (3004) in the packet header of this command packet is the command packet, UnitID ( 3019) is the unit ID of the resolution conversion unit (2116), and BusSel (3021) is set to the command bus information, so this command packet is not sent to the tile expansion unit (2103), but directly transferred to the command bus. Is done. The command transferred to the command bus is transmitted directly to the resolution conversion unit (2116) based on the address information in the packet.

  Commands accessed via the command bus can access the registers regardless of the status of the resolution converter (2116), because they can access the registers regardless of the status of the data bus and data image processing. Do it.

  In this case, since the command is a read command, it can be used, for example, for polling the status register during processing in the resolution conversion unit (2116).

  The read value read from the register returns to the command bus and is transferred to the packet distribution unit (2104), where a return command packet is created, and finally the CPU 2001 via the image ring interface 4 (2102). Forwarded to

  According to this embodiment, the bus to be uniquely transferred is determined by the BusSel (3021) information in the packet header.

  In the above embodiment, the read command performs a synchronous / asynchronous operation and the write command describes only the synchronous operation. However, an asynchronous write command can be performed depending on the setting in the packet header.

  However, when register write is performed asynchronously with the image data, the operation mode of the image processing unit whose register value has been changed is changed before and after the register write command. It is conceivable that the image quality changes significantly. For example, as shown in FIG. 7, when register write is performed at the timing of 7003 in one page, the image quality of the first half image (7001) and the second half image (7002) is different.

  For this reason, it is necessary to control with the software which controls the register setting so that it does not become above.

  Or, if an asynchronous write command is set, that is, if Packet Type ID (3004) in the packet header of the command packet is a command packet, BusSel (3021) is a command bus, and CmdType (4005) is a write, The distribution unit may determine that an error has occurred and notify the CPU (2001) with an interrupt signal.

  In the first embodiment, the case where the data bus for transferring image data is a so-called bus connection (a bus capable of transferring an image from any image processing unit to any other image processing unit) has been described. In this embodiment, a case where the data bus is an interface that connects all the image processing blocks in a single direction by connecting them in a daisy chain will be described.

  FIG. 8 shows a block diagram of the image processing unit (equivalent to 2149) in this embodiment. Blocks and the like that are not necessary for the description in this embodiment are omitted.

  Parts not specifically described are the same as in the first embodiment.

  Reference numeral 8001 denotes a data bus, which is a packet distribution unit (2104) → tile expansion unit (2103) → multi-value conversion unit (2119) → binarization unit (2119) → color space conversion unit (2117) → image rotation unit (2030) ) → resolution conversion unit (2116) → tile compression unit in this order, and the image data is transferred while performing image processing.

  There may be a block in the series of data buses where processing is not performed. For example, when multi-value data is input to the image processing unit (2149), the multi-value conversion unit (2119) does not particularly process. In this case, the input data packet is once input to the multi-value quantization unit (2119), but is transferred to the binarization unit (2118) which is the next block without being internally processed.

  The function of transferring to the next block without performing any processing as described above is built in all image processing blocks, and whether or not to perform processing in the image processing block is determined in ProcessInstruction ( 3011) is performed by determining whether or not the UnitID corresponds to an ID given in advance to the image processing block.

  FIG. 9 shows an internal block diagram of the image processing unit in the second embodiment.

  FIG. 9 schematically shows one of the image processing units in FIG. Depending on the processing contents, a memory or the like may be connected outside the image processing unit, but a simplified diagram is shown to simplify the description.

  An image processing unit 9010 includes a command I / F (9021), a packet Input I / F (9022), a register (9023), an image processing block (9024), and a packet Output I / F (9025). The command I / F (9021) is connected to the command bus (9001) and the register access bus (9002). The packet Input I / F (9022) is connected to an input data bus (9003), a command packet bus (9004), a packet forward bus (9005), and a data packet bus (9006). The image processing block (9024) is connected to the data packet bus (9006) and the processed data packet bus (9007). The packet Output I / F (9025) is connected to the packet forward bus (9005), the processed data packet bus (9007), and the output data bus (9008).

As described in the first embodiment, only commands are transferred via the command bus 9001. The command I / F accesses a designated register based on the address offset value described in the command. (With read / write)
In addition, as described in the first embodiment, the data transferred via the data bus 9003 is either a data packet or a command packet. The packet Input I / F (9022) determines whether it is a data packet or a command packet based on the PacketType described in the header part of the received image data.

  When it is determined that the transferred packet is a command packet, the packet Input I / F (9022) further confirms the Process Instruction in the header, and confirms whether or not this is a command to the image processing unit 9010. If it is determined that the packet is for the image processing unit, the command packet accesses the designated address in the register (9023) based on the internal address information. When it is determined that the packet is not sent to the image processing unit, the packet Input I / F (9022) transfers this packet to the packet forward bus (9005).

  When it is determined that the transferred packet is a data packet, the packet Input I / F (9022) further confirms the Process Instruction in the header and confirms whether the command is for the image processing unit 9010. If it is determined that the packet is to be sent to the image processing unit, the data packet is transferred to the image processing block (9024), and image processing is performed in accordance with the operation mode set in the register (9023) until that point. . The processed data packet is transferred to the processed data packet bus (9007). When it is determined that the packet is not sent to the image processing unit, the packet Input I / F (9022) transfers this packet to the packet forward bus (9005).

  Each data / command packet that has reached the packet Output I / F (9025) as described above is transferred to the next image processing unit.

  The command packet transferred via the data bus must be transferred in synchronization with other data packets. For example, when the data packet is input to a certain image processing unit in the order of data packet → command packet. Consider a case where the data packet is processed by the image processing unit, and the command packet is not a register access to the image processing unit.

  Since the first transferred data packet is subjected to image processing by the image processing unit, it is sent to the image processing block (9024) to start processing. If this processing itself takes time, before the data packet completes the image processing and arrives at the packet Output I / F (9025), the next command packet is subsequently input to the image processing unit and the packet forward bus ( 9005) to arrive at the packet Output I / F. For this reason, the order of the packets is changed in the image processing block.

  In the packet Output I / F, when the arriving packets are output to the output data bus (9008) in the order of arrival, in the next image processing unit, the packet order is in the order of command packet → data packet, and the above data packet is desired. The image processing operation mode is not processed.

  In order to avoid this, when the image processing block (9024) receives the data packet and starts the image processing, it outputs a signal indicating that the image processing is in progress to the packet Output I / F. This signal continues to be output until the processing is completed. When a command packet is received via the packet forward bus while receiving this image processing signal, the packet Output I / F (9025) is used until the image processing of the image data is completed and output to the output data bus is completed. The command packet is temporarily stored in the internal buffer so as not to be output to the outside.

  Thereby, it is possible to guarantee the output image quality without changing the order of the packets in each image processing.

  If a packet is input in the order of data packet (processed by the image processing unit) → data packet (not processed by the image processing unit), the latter data packet (not processed by the image processing unit) is There is no need to wait for completion of the former data packet (processed by the image processing unit).

  FIG. 10 shows an operation flowchart of the packet OutPutI / F.

  In this embodiment, only one register (9023) is prepared and can be accessed from either the command bus or the data bus, but two registers are prepared, one of which is from the command packet. You may comprise so that it may be exclusive for access and the other may be exclusive for access from a data packet.

The figure explaining the whole system demonstrated in a present Example Block diagram of the entire controller described in the first embodiment The figure explaining the data packet demonstrated in a present Example The figure explaining the command packet demonstrated in a present Example The figure explaining the tile position in the page explained in this embodiment and the coordinates of the image The figure explaining the packet table demonstrated in a present Example Diagram explaining the image after processing when asynchronous write command is executed Block diagram of the image processing unit described in the second embodiment Block diagram of each image processing unit described in the second embodiment Flowchart diagram for guaranteeing the packet order described in the health embodiment 2

Claims (11)

In an image processing apparatus that performs image processing, a data bus that transfers image data and is connected to an image processing unit, a command bus that is connected to a register unit that performs operation settings for the image processing unit, and Data I / F section for inputting / outputting data from outside,
A data distribution unit connected to the data I / F unit for selectively transferring all input data to either the data bus or the command bus;
And at least one image processing unit connected to the image bus and the command bus,
An image processing apparatus, wherein the image data is automatically transferred to either the data bus or the command bus according to information in the image data.   2. The image processing apparatus according to claim 1, wherein the image data is processed in a grid pattern.   2. The image processing apparatus according to claim 1, wherein the image data is classified into a data packet subjected to image processing by the image processing unit and a command packet used for setting operation of the image processing unit. An image processing apparatus.   2. The image processing apparatus according to claim 1, wherein the information in the image data is a packet header included in the packet data.   5. The image processing apparatus according to claim 4, wherein the packet header includes information specifying which image processing unit to perform processing among at least a plurality of image processing units, and whether the packet is a data packet or a command packet. An image processing apparatus comprising: information indicating: information specifying whether the packet is transferred on a command bus or a data bus.   2. The image processing apparatus according to claim 1, wherein the image processing unit can distribute a command packet received via a data bus to an internal register unit.   2. The image processing apparatus according to claim 1, wherein the image processing unit outputs the packet as it is when receiving a packet unrelated to the image processing unit via a data bus.   2. The image processing apparatus according to claim 1, wherein the image processing unit transfers to the internal image processing block when a data packet related to the image processing unit is received via the data bus. Processing equipment.   The image processing apparatus according to claim 1, wherein the image processing unit can distribute command data received via a command packet to an internal register unit.   2. The image processing apparatus according to claim 1, wherein the register unit in the image processing unit includes a first register unit accessed using the command data received via the data bus and a command received via the command bus. An image processing apparatus that is divided into a second register unit that is accessed using data.   2. The image processing apparatus according to claim 1, wherein the command data received during the image data processing is waited for completion of the image data processing transfer so that the order of the command data and the image data is not switched in the image processing unit. An image processing apparatus.

Images