JP2003304381A - Information processor and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor and a data transfer method which can efficiently transmit and receive packets between blocks even when different packets are simultaneously processed. <P>SOLUTION: When the packets are transferred from a resolution conversion part (1057) with a slow data transfer speed to an image rotation part (1056), the packets are temporarily transferred from the resolution conversion part (1057) to a temporary storage part (1056), and the packets which are transferred to the temporary storage part (1056) are temporarily stored in the temporary storage part (1056), and the packets which are temporarily stored in the temporary storage part (1056) are transferred to the image rotation part (1056) according to header information to minimize the effect of the resolution conversion part (1057) with the slow data transfer speed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a data transfer method for processing a packet composed of data and a header containing information about the data.

[0002]

2. Description of the Related Art In recent years, the speed of CPUs and the capacity of IC memories and hard disks have increased, and the amount of data handled by information processing devices has increased. Along with this, the amount of data transmitted between blocks inside the information processing apparatus is also increasing.

As a typical device that processes a large amount of data, a conventional technique will be described by taking an information processing device that handles image data as an example. In an image processing apparatus, generally, a CPU, an IC memory, and a hard disk portion for storing and processing image data and a hardware portion for realizing image processing that cannot be processed in a time required by the CPU. Be divided. Since the former part has the same configuration as a general computer, the same architecture as the computer is used, and the latter part is added to it. Also,
In the image processing, it is general that one image data is subjected to a plurality of processes. For example, it is conceivable that color space processing, resolution conversion (magnification change) processing, rotation processing, and binarization processing are successively performed on multivalued image data.

FIG. 15 is a block diagram simply showing an image processing hardware section in an information processing apparatus proposed by the present applicant. A CPU (1501) and a memory 1502 connected to the 1501 are units that control this information processing apparatus, like a computer.
The image processing units (1503) to (1507) use the CPU (1
501) via a bus (1508),
A multi-value conversion processing block (1503), a binarization processing block (1504), a color space conversion processing block (1505),
It is composed of a rotation processing block (1506) and a resolution conversion processing block (1507). Image data is CPU
(1501) is packetized and transmitted, and each image processing is performed by the received image processing.

Although the block diagram shown in FIG. 15 is simplified for the sake of explanation, an actual image processing apparatus is provided with a larger number of blocks to perform more detailed image processing.

[0006]

The image processing apparatus proposed by the present applicant is characterized by processing image data in units of packet data. Next, the packet data handled by the image processing units (1503) to (1507) will be described. FIG. 3 shows the structure of packet data. The image data handled by this device has a very large data amount for one image. Therefore, each image processing block (1503) to (1507) is divided into a predetermined size, for example, 32 pixels × 32 pixels (this 32 × 32 unit data is called a tile) so that it can be easily processed. The processing of each image processing block is performed in tile units, but the data transmitted and received between the CPU and the image processing unit has information necessary for performing image processing added as header information. A set of data and data is a unit of actual data transmission / reception (this data is called a packet).

By adding to the header portion of this packet the transmission path information indicating which block is to be processed and in what order for each content of image processing, the CP
When the packet is sent from the U (1501) to the packet bus (1508), the packets pass through the image processing blocks in the order specified in the header section, and the desired processing is performed on the image data. At this time, it is conceivable that the same image processing block is designated in the mutual transmission route information. in this case,
Processing is performed in the order in which the packets arrive at the block.

By handling data in packets,
It is possible to easily process a plurality of packets having different transmission route information, that is, packets having different image processing modes at the same time in the image processing unit. In particular, an MFP having a scan function, a print function, a copy function, a communication function, etc.
(Multi Function Periphera
In systems such as l), a state called simultaneous operation frequently occurs, which requires image processing of different image data at the same time. Therefore, data processing using such a packet is an effective method for handling data inside the MFP.

However, particularly in an MFP or the like, it is easily assumed that the same processing is simultaneously performed on a plurality of image data. At this time, in the MFP to which the image processing apparatus is applied, if a desired image processing block is used for data processing of another system, it is necessary to wait until the processing is completed. Even if there are a plurality of image processing blocks that can perform the same processing, since the transmission path is set in advance by the CPU, data is transferred to an empty block even if a block other than the set block is empty. There is a problem that processing cannot be performed, which leads to a decrease in overall performance.

The present invention is for solving the above-mentioned problems. When the unique information of the transmission block satisfies a predetermined condition, the packet is transferred from the transmission block to a predetermined storage block and the transferred packet is stored. By temporarily storing the packet in a block and transferring the packet once stored in the storage block to the reception block based on the header information, for example, the influence of the transmission block having a slow data transfer rate can be minimized. Therefore, it is an object of the present invention to provide an information processing apparatus and a data transfer method capable of efficiently transmitting / receiving packets between blocks even when different packets are simultaneously processed.

When the processing block of the transmission destination cannot accept the packet from the processing block of the transmission source, the alternative transmission destination is determined based on the unique information of the processing block,
By sending the packet to the determined alternative destination,
An object of the present invention is to provide an information processing device and a data transfer method capable of efficiently performing data processing even when different packets are simultaneously processed because data can be transferred to an empty block for processing. To do.

When the transmission rate of the first transmission block is slower than the transmission rate of the second transmission block, the first transmission block
Data of packets transmitted from the transmission block is sequentially stored in the storage block, and data of packets transmitted from the second transmission block is transferred to the reception block, and the storage block is transmitted from the first transmission block. Transfer of the data to the receiving block is temporarily stopped after the transfer of the data to the receiving block, and the data from the first transmitting block stored in the storage block is transferred to the storage block. By transferring to the receiving block, it is possible to minimize the influence of the sending block, which has a relatively low data transfer rate. Therefore, even when different packets are processed at the same time, it is possible to efficiently send and receive packets between blocks. An object is to provide an information processing apparatus and a data transfer method that can be performed.

[0013]

In order to achieve the above object, an information processing apparatus of the present invention is an information processing apparatus that processes a packet composed of data and a header containing information about the data. And transmitting means for transmitting the packet to a predetermined destination based on the information in the header, receiving means for receiving the packet sent from the transmitting means, and storage means for temporarily storing the packet. And control means for controlling transfer of the packet via the bus between the transmitting means, the receiving means, and the storing means, and the unique information of the transmitting means satisfies a predetermined condition. The control means transfers the packet from the transmission means to the storage means, and transfers the packet once stored in the storage means to the reception means.

The information processing apparatus of the present invention is an information processing apparatus for processing a packet composed of data and a header containing information about the data, and is sent from a predetermined transmission source. A plurality of processing means for receiving a packet, performing a predetermined processing, and transmitting the processed packet to a predetermined destination based on the header information, and transferring the packet via a bus between the plurality of processing means When the processing means of the transmission destination cannot accept the packet from the processing means of the transmission source, the control means determines an alternative transmission destination based on the unique information of the processing means. And transmitting the packet to the determined alternative transmission destination.

Further, the data transfer method of the present invention is such that a packet composed of data and a header containing information about the data is transferred from a transmission block to a reception block via a bus based on the information of the header. A data transfer method for transferring, wherein when the unique information of the transmission block satisfies a predetermined condition, the packet is transferred from the transmission block to a predetermined storage block, and the transferred packet is temporarily stored in the storage block. The packet that is temporarily stored in the storage block is transferred to the reception block based on the header information.

Further, the data transfer method of the present invention transfers a packet via a bus between a plurality of processing blocks for processing a packet composed of data and a header containing information about the data. A data transfer method for transmitting a packet from a processing block of a transmission source, the alternative transmission destination is determined based on unique information of the processing block, and the determined alternative transmission destination is determined. And transmitting the packet.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) [Outline of Image Processing Apparatus] FIG. 1 shows an overall configuration of an image processing apparatus to which the present invention is applicable.

The controller unit (1001) is connected to a scanner (1002) which is an image input device and a printer (1003) which is an image output device, while a LAN (1004) and a public line (WAN) (1005) are connected.
I / O of image information and device information,
It is a controller for developing an image of PDL data.

The CPU (1006) is a processor that controls the entire system. In this embodiment, an example using two CPUs is shown. These two CPUs (1006)
It is connected to a common CPU bus (1007) and further connected to a system bus bridge (1008).

The system bus bridge (1008) is a bus switch, and includes a CPU bus (1007), a RAM controller (1009), and a ROM controller (101).
0), IO bus 1 (1011), sub-bus switch (1
012), IO bus 2 (1013), image ring interface 1 (1014), and image ring interface 2 (1015) are connected.

The sub-bus switch (1012) is a second bus switch, and includes an image DMA1 (1016), an image DMA2 (1017), a font expansion unit (1018),
A sort circuit (1019) and a bit map trace circuit (1020) are connected to arbitrate memory access requests output from these DMAs and connect to the system bus bridge (1008).

The RAM (1021) is a CPU (1006)
Is a system work memory for operating, and is also an image memory for temporarily storing image data, RAM
It is controlled by the controller (1009). In this embodiment, an example in which a direct RDRAM is adopted is shown.

The ROM (1022) is a boot ROM in which a system boot program is stored.
It is controlled by the OM controller (1010).

The image DMA1 (1016) is connected to the image compression unit (1023) and is connected to the register access ring (1023).
24), the image compression unit (1023) is controlled based on the information set, and the non-compressed data on the RAM (1021) is read, compressed, and the compressed data is written back. In this embodiment, an example in which JPEG is adopted as a compression algorithm is shown.

The image DMA2 (1017) is connected to the image decompression unit (1025) and connected to the register access ring (10).
24), the image decompression unit (1025) is controlled on the basis of the information set, and the compressed data in the RAM (1021) is read, decompressed, and the decompressed data is written back. In this embodiment, an example in which JPEG is adopted as a decompression algorithm is shown.

The font decompression unit (1018) transfers P from the outside via the LAN controller (1026) and the like.
ROM based on font code included in DL data
(1022) or the compressed font data stored in the RAM (1021) is expanded. In this embodiment, an example in which the FBE algorithm is adopted has been shown.

The sort circuit (1019) is a circuit for rearranging the order of the objects in the display list generated at the stage of expanding the PDL data.

Bitmap trace circuit (1020)
Is a circuit for extracting edge information from bitmap data.

The IO bus 1 (1011) is a type of internal IO bus, and is a standard USB bus controller, USB interface (1027), general-purpose serial port (1028), interrupt controller (1029), GPIO interface. (1030)
Are connected. The IO bus 1 (1011) includes a bus arbiter (not shown).

The operation unit interface (1031) is
Image data to be displayed on the operation unit (1032) is displayed on the operation unit (1032) in the interface unit of the operation unit (1032).
Output to 2). In addition, the information input by the system user from the operation unit (1032) is stored in the CPU (100
6) The role of telling.

The IO bus 2 (1013) is a kind of internal IO bus, and is a general-purpose bus interface 1 and 2.
The LAN controller (1026) is connected to (1033). The IO bus 2 (1013) includes a bus arbiter (not shown).

General-purpose bus interface (1033)
Is a bus bridge composed of two identical bus interfaces and supporting a standard IO bus. In this embodiment, an example in which the PCI bus (1035) is adopted is shown.

The HDD (1035) is a hard disk drive that stores system software and image data. It is connected to one PCI bus (1034) via the disk controller (1036).

The LAN controller (1026) is an MA
C circuit (1037), PHY / PMD circuit (1038)
It is connected to the LAN (1004) via the to input / output information.

The modem (1039) is a public line (100
Connect to 5) and input / output information.

The image ring (1040) is composed of a combination of a pair of unidirectional connection paths. The image ring (1040) is in the image processing unit (1041), via the image ring interface 3 (1042) and the image ring interface 4 (1043), the tile expansion unit (1044), the command processing unit (1045), and the status. It is connected to the processing unit (1046) and the tile compression unit (1047).

The tile decompression unit (1044) is connected to the image ring interface as well as the tile bus (104).
8) is a bus bridge which is connected to 8) and expands the compressed image data input from the image ring and transfers it to the tile bus (1048). The present embodiment shows an example in which JPEG is adopted as the multivalued image data and Packbits is adopted as the decompression algorithm for the binary image data.

The tile compression unit (1047) is connected to the image ring interface, and in addition to the tile bus (104).
8) is a bus bridge which is connected to 8), compresses the image data before compression input from the tile bus, and transfers it to the image ring (1040). This embodiment shows an example in which JPEG is adopted as the compression algorithm for multi-valued image data and Packbits is adopted as the binary image data.

In addition to the connection to the image ring interface, the command processing unit (1045) is connected to the register setting bus (1049) and receives a register setting request issued from the CPU (1006) input via the image ring. , Write to the corresponding block connected to the register setting bus. Further, based on a register read request issued by the CPU (1006), information is read from the corresponding register via the register setting bus and transferred to the image ring interface 4 (1043).

The status processing unit (1046) monitors the information of each image processing block, generates an interrupt packet for issuing an interrupt to the CPU (1006), and the image ring interface 4 (104).
Output to 3).

In addition to the above blocks, the tile bus (1048) has a rendering section interface (105
0), the image input interface (1051), the image output interface (1052), the multi-valued processing unit (10
53), the binarization processing unit (1054), the image rotation unit 1 (1
055), the image rotation unit 2 (1056), the resolution conversion unit (1057), and the image temporary storage unit (1058) are connected.

The tile bus (1048) in the figure is
It also includes a bus controller unit described later.

Rendering unit interface (105
0) is an interface for inputting a bitmap image generated by the rendering unit described later.
The rendering unit (1067) and the rendering unit interface (1050) are connected to a general video signal (105).
It is connected in 9). The rendering unit interface (1050) is connected to the memory bus (1060) and the register setting bus (1049) in addition to the tile bus (1048). Rendering unit interface (105
0) performs structural conversion of the input raster image into a tile image by a predetermined method set via the register setting bus, and at the same time performs clock synchronization, and outputs the output to the tile bus (1048). To do.

Image input interface (1051)
Receives tile image data from the tile bus as input, performs structural conversion into a raster image, changes the clock rate, and outputs the raster image to the printer image processing unit (1061).

The image rotation unit 1 (1056) rotates image data. The image rotation unit 2 (1057) rotates image data. The resolution conversion unit 2 (1055) converts the resolution of the image. A binarization processing unit (1054) binarizes a multi-valued (color and gray scale) image. The multi-valued processing unit (1053) converts the binary image into multi-valued data.

The image temporary storage unit (1058) temporarily stores the received image data in the internal storage unit, and immediately after storing the data, transmits the received data to another block.

External bus interface section (1062)
Through the image ring interface 1, 2, 3, 4, the command processing unit, the register setting bus, the CPU (100
This is a bus bridge for converting and outputting the write / read request issued by 6) to the external bus 3 (1063).
In this embodiment, the external bus 3 (1063) includes a printer image processing unit (1061) and a scanner image processing unit (1).
064).

The memory control unit (1065) is connected to the memory bus (1060), and according to the request of each image processing unit,
By preset address division, image data writing / reading to / from the image memories 1 and 2 (1066) and an operation such as refreshing as necessary are performed. In this embodiment, the example in which the SDRAM is used as the image memory is shown.

In the scanner image processing unit (1065),
Image data scanned by a scanner (1002) which is an image input device is subjected to corrected image processing.

In the printer image processing unit (1061),
Corrected image processing for printer output is performed, and the result is output to the printer (1003).

The rendering unit (1067) develops the PDL code or the intermediate display list into a bitmap image.

FIG. 2 includes the image processing apparatus of the present invention.
It is a block diagram of the whole network system.

Reference numeral 2001 denotes an image processing apparatus such as a digital multi-function peripheral to which the present invention is applied. The image processing apparatus is composed of a scanner and a printer, and an image read from the scanner is sent to a local area network (2002) (hereinafter LAN) or LA.
The image received from N can be printed out by the printer. In addition, the image read from the scanner is transmitted to the PSTN or ISDN (20
The image received from PSTN or ISDN can be printed out by the printer. 20
Reference numeral 04 denotes a database server, which is an image processing device (200
The binary image and multi-valued image read in 1) are managed as a database.

Reference numeral 2005 denotes a database server (200
In the database client of 4),
The image data stored in 004) can be browsed / searched.

An electronic mail server 2006 can receive an image read by the image processing apparatus (2001) as an electronic mail attachment. Reference numeral 2007 denotes an e-mail client, which can receive an e-mail received by the e-mail server (2006), browse it, and send an e-mail.

The WWW server (2008) is a server for providing an HTML document to the LAN, and is an image processing device (200).
According to 1), the HTML document provided by the WWW server can be printed out.

The router (2009) is the LAN (2002)
Is connected to the Internet and Intranet (2010). The aforementioned database server (2004) and WWW server (20
08), an electronic mail server (2006), and an image processing device (2001), respectively,
12, 2013 are connected. On the other hand, the image processing apparatus (2001) uses the PSTN or ISDN (200
It is possible to transmit and receive with the FAX machine (2014) via 3).

A printer (2015) is also connected to the LAN (2002), and the image processing apparatus (200)
The image read in 1) can be printed out.

Next, the packet format in this embodiment will be described in detail.

The controller unit (100
In 1), the image data, the command by the CPU (1006), and the interrupt information from each block are transferred in a packetized format.

[Data Packet] FIG. 3 is a diagram showing in detail a data packet in which image data is packetized.

In this embodiment, the image data of one page is divided into image data of tile image unit (3001) of 32 pixels × 32 pixels and handled. This tile-unit image data (3002) has necessary header information (3003),
And image additional information (3004) are added to form a data packet.

The information contained in the header information (3003) will be described below.

The packet type is header information (300
It is distinguished by PcktType (3005) in 3).
The PcktType (3005) includes a repeat flag, and when the image data of the data packet is the same as the image data of the data packet transmitted immediately before, the repeat flag is set. ChipID (3006)
Indicates the ID of the target chip when transmitting a packet. ImageType (3007) is an image type of image data (for example, monochrome binary data,
Or a type such as monochrome 8-bit data). PageID (3008) is an ID in page units
JobID (3009) is an ID for software management. The tile number is represented as YnXn by the combination of the coordinate (3010) in the Y direction and the coordinate (3011) in the X direction.

The data packet may or may not be compressed image data. In the present embodiment, as the compression algorithm, JPEG is used for a multi-value color (including multi-value gray scale) image and Packbits is used for a binary image. The distinction between compressed and non-compressed is indicated by CompressFlag (3018).

ProcessInstruction
(3012) is left-justified, and the ID and processing mode of each image processing block are set in the processing order.
After processing, ProcessInstruction (30
The data in 12) is shifted to the left by 8 bits. Proc
essInstruction (3012) is UnitID (3020) which is the ID of each image processing block.
And 8 sets of Mode (3021) which is the processing mode are stored. As a result, one packet can be continuously processed by eight processing blocks.

PacketByteLength (30
13) indicates the total number of bytes in the packet. Image
eDataByteLength (3016) is the number of bytes of the image data, ZDataByteLength (3
017) indicates the number of bytes of the image additional information, and is Image
DataOffset (3014), ZDataOff
set (3015) represents the offset from the beginning of the packet of each data.

[Description of Packet Transfer Route Setting] Next, a packet transfer method in this embodiment will be described in detail.

In FIG. 1, the tile bus (1048) is a crossbar switch, and the image processing unit (1053) .about.
Arbitration is performed between the image processing unit of the master and the image processing unit of the target, which is either (1057), and the bus is connected. When both the image processing unit serving as the master and the image processing unit serving as the target are different from each other, it is possible to connect a plurality of paths at the same time, and it is possible to perform packet transfer through a plurality of paths at the same time. However, if the targets are different but the masters are different,
The paths cannot be connected at the same time. In this case, one master and the target are connected, and after the transfer of one packet is completed, the master is switched to another master to transfer the packet.

The arbitration of the tile bus will be described below.

When the master wants to transfer data to the target, it issues a request signal indicating a transfer request. The arbiter monitors a busy signal indicating whether the target is connected to another master, and asserts a grant signal indicating connection permission to the master if it is not busy. At the same time, a start signal indicating the start of connection is asserted to the slave, and the master and target are connected to the bus. After the data transfer, when the target busy signal is deasserted, the arbiter deasserts the grant signal to the master to disconnect the bus connection.

When a plurality of masters make connection requests to one slave, they are connected in a predetermined order.

The above-mentioned image processing units (1053) to (10)
57) have different data processing speeds. For example,
Since the binarization processing unit (1054), the image rotation unit (1056), and the like have a light processing load, the packet can be processed at high speed, and the packet can be transmitted / received to / from the tile bus at high speed. On the other hand, the resolution converter (10
In 57), since the processing load is heavy, it takes time to process the packet, and the packet transmission / reception to / from the tile bus also becomes slow.

In the tile bus (1048), one packet cannot be switched to another path during transfer. Therefore, if the packet transmission / reception speed of the image processing unit is slow, the connection time of the tile bus becomes long and the packet transmission / reception speed is increased. Is faster, the connection time will be shorter.

The image processing block described above includes an image repeater (105) for temporarily storing packets in addition to each image processing unit.
8) is prepared. The image repeater simply holds the data transmitted from each image processing unit as it is and does not perform image processing, so that packet transmission / reception can be performed at high speed.

The flow of packet processing in the conventional image processing apparatus without repeater will be described.

In FIG. 4, the packet binarization processing unit (105
4) and the processing flow in the case of performing processing by the image rotation unit 1 (1055). FIG. 5 shows a temporal processing flow when a packet is processed by the resolution conversion unit (1057) and the image rotation unit 1 (1055).

In FIG. 4, the image rotation unit (1056) can perform high-speed processing, but in FIG. 5, it takes a long time to receive a packet. This is the resolution converter (105
This is because the transmission speed from 7) is low, so that it can be received only at an equivalent speed.

In FIG. 6, packets of different images such as the image A and the image B are transferred to the binarization processing unit (105) shown in FIG.
4) and a system for performing processing by the image rotation unit 1 (1055), the resolution conversion unit (1057) and the image rotation unit 1 shown in FIG.
The flow of processing in time when the processing is performed in parallel in the system performing processing at (1055) is shown.

The packet of the image A and the packet of the image B are respectively a binarization processing unit (1054) and a resolution conversion unit (10).
57) are processed in parallel, but both images pass through the image rotation unit 1 (1055), so when one image is processed by the image rotation unit 1 (1055), the other image is rotated. There is a delay in sending a packet to the part 1 (1055). Since the packet of the image B is transmitted from the resolution conversion unit (1057) to the image rotation unit 1 (1055) at a low speed, it can be seen that the image rotation unit 1 (1055) is occupied for a long time.

In this embodiment, the arbiter determines whether the transfer speed of each image processing unit (1053) to (1057) is fast or slow, and when each image processing unit serves as a master and transfers data to the target, The image processing unit having a slow transmission speed transfers data via the repeater block.

FIG. 7 shows a flow chart when the image processing unit as a master transfers to the target.

When the master is ready to send packets,
ProcessInstruction of the packet header
A transfer request is made to the target designated by n (3012) (S701).

The master asserts the transfer request signal together with the Unit ID signal. The arbiter discriminates from the UnitID whether the transfer rate of the master requesting the transfer is fast or slow (S702), and if the master is fast, the arbitration to the target is performed as it is (S70).
3). When the transfer permission signal is asserted from the target side, packet transfer is executed (S704).

On the other hand, if it is determined in step S702 that the master requesting the transfer is the slow master,
The arbiter changes the bus connection destination to a repeater and performs arbitration (S705). Repeater (1058)
When the transfer permission signal is asserted from, the packet transfer is executed (S706).

The data transfer from the repeater (1058) to the real target treats the repeater as an early master.

The repeater (1058) asserts the transfer permission signal when the packet reception is ready, and starts packet reception. When the repeater (1058) finishes receiving the packet, the process I of the packet header
A transfer request is issued to the target designated by nstruction (3012) and data transfer to the target is performed. At this time, the repeater is ProcessInst
Output to the target as it is without performing the left shift of the subtraction (3012). Like this Process
By copying the Instruction (3012), it is not necessary to set the repeater (1058) in the transmission path setting, and the same number of image processing paths as when there is no repeater can be set.

In the present embodiment, as in the case of FIG. 6, packets of different images such as image A and image B are
Consider a case where the binary processing unit (1054) and the image rotation unit (1056) perform processing in parallel, and the resolution conversion unit (1057) and the image rotation unit (1056) perform processing in parallel. FIG. 8 shows a temporal processing flow.

In this way, when a plurality of masters simultaneously transmit packets to the same target, in this embodiment, the resolution conversion unit (105) having a slow processing speed is used.
Data is transferred to the repeater (1058) in response to the transfer request from 7), and a packet is transmitted to the resolution conversion unit (1057) via the repeater (1058). On the other hand, the binarization processing unit (10
54) The transfer request from the direct image rotation unit (1056).
A packet is sent to.

Therefore, as is clear from comparison between FIG. 6 and FIG. 8, the packet is transmitted from the resolution conversion unit (1057) once via the repeater (1058),
The transmission of the packet from the repeater (1058) to the image rotation unit (1056) shortens the time for occupying the tile bus. As a result, the image rotation unit (105
The number of packets received by 6) is increasing, and the overall performance is improving.

There is no improvement in the performance of the path from the resolution conversion unit (1057) to the image rotation unit (1056), but the performance is deteriorated even though the packet is transferred via the repeater (1058). Is rarely seen. On the other hand, the binarization processing unit (10
With respect to the path from 54) to the image rotator (1056), a nearly double performance improvement is seen.

(Second Embodiment) In the first embodiment, the number of repeaters is one, but the performance can be further improved by using a plurality of repeaters. The overall structure of the image processing apparatus of the second embodiment is as shown in FIG. It differs from the block diagram of the second embodiment shown in FIG. 1 in that the color space conversion unit (1055) becomes a resolution conversion unit (9055) and a temporary storage unit 2 (repeater) (1067) is added. . Others are the same as those in the second embodiment, and thus the description thereof is omitted here.

In the present embodiment, consider the data flow when resolution conversion → image rotation processing is applied to different images A and B. For reference, FIG. 10 (A) shows the data flow when one repeater is used, and FIG. 10 (B) shows the data flow when two repeaters are used as in the present embodiment.
Shown in.

In FIG. 10A, since the number of modules passing through the repeater is increased to two, a transfer waiting time to the repeater occurs and the time for processing an image is delayed. When two repeaters are used as shown in FIG. 10B and both resolution conversion units 1 and 2 perform processing via each repeater, the processing speed of the image rotation unit increases.

(Third Embodiment) In the configurations of the first and second embodiments, even if there are a plurality of image processing blocks capable of performing the same processing, the transmission path is set in advance by the CPU, so that the setting is performed. Even if a block other than the reserved block is free, data cannot be transferred to the free block for processing.

In the present embodiment, an image processing apparatus will be described in which the tile bus is provided with a bus control function and the empty blocks are controlled so as to be effectively used, whereby the packet processing efficiency can be further improved.

FIG. 11 shows a block configuration of the image processing apparatus according to this embodiment. The difference from the configuration of the first embodiment shown in FIG. 1 is that in the image processing unit (1041), the image rotation unit 1 is used instead of the color space conversion unit (1055).
(1055) is connected, and the image rotation unit is the image rotation unit 1 (1055) and the image rotation unit 2 (1056).
It is a part that is connected.

[Description of Data Packet Transfer] Next, a packet transfer method in image input / output according to the present embodiment will be described in detail.

In FIG. 11, the tile bus (1048)
Is a crossbar switch provided with a bus controller unit, which performs arbitration between the master image processing unit, which is one of the image processing units (1053) to (1057), and the target image processing unit, and connects the bus. When both the image processing unit serving as the master and the image processing unit serving as the target are different from each other, it is possible to connect a plurality of paths at the same time, and it is possible to perform packet transfer through a plurality of paths at the same time. However, if the targets are different but the masters are different, these paths cannot be connected at the same time. In this case, one master and the target are connected, and after the transfer of one packet is completed, the master is switched to another master to transfer the packet. In this case, the masters are connected in a predetermined order.

Image processing units (1053) to (1057)
After receiving the data, the data processing is performed, and the processed data is sequentially transmitted to the target image processing unit. Rotation processing units 1 (1055) and 2 (105
6) The binarization processing unit (1054) (for example, the binarization processing by the screen) can immediately process and transmit one packet when it receives one packet.

However, the resolution converter (1057)
The multi-value quantization processing unit (1053) takes a long processing time, and thus the transmission speed becomes slow. Here, the temporal processing flow in this embodiment is the same as that described with reference to FIGS. 4 and 5 in the first embodiment.

[Simultaneous Processing of Plural Packets] In the present embodiment, packets of different images such as the image A and the image B are processed by the binarization processing unit (1054) and the image rotation unit 1 (1055) shown in FIG. FIG. 6 shows the temporal processing flow when the processing is performed in parallel with the system that performs the processing and the system that performs the processing by the resolution conversion unit (1057) and the image rotation unit 1 (1055) illustrated in FIG. Shall be the same as.

That is, the packet of the image A and the packet of the image B are processed in parallel by the binarization processing unit (1054) and the resolution conversion unit (1057), but both images are rotated by the image rotation unit 1 (1055). Since one image is being processed by the image rotating unit 1 (1055), the other image is kept waiting for the packet transmission to the image rotating unit 1 (1055). The packet of the image B is transferred from the resolution conversion unit (1057) to the image rotation unit 1 (1055).
Since the image is transmitted at low speed, the image rotation unit 1 (1055) is occupied for a long time.

However, in this embodiment, since the same image rotating unit is further provided in 1 Unit, the process of the image B is changed.
If the image rotation unit 2 (1056) is designated in sslnstruction (3012) and transmission path information is created,
As shown in FIG. 12, processing can be performed without waiting time.

Further, for three different image packets such as image A, image B, and image C, image A has resolution conversion → image rotation, and image B has multi-valued processing → image rotation, image C.
Will be described for a case where simultaneous processing is performed in a system of binarization processing → image rotation.

Normally, the transmission route information set by software is set for each image. In the above-described processing, since the three systems simultaneously perform the image rotation processing on the two image rotation units, either the image rotation unit 1 or 2 may compete for the transmission path information of the three systems. Become. Further, even if the transfer route information is set by software every time a packet is transferred, it is not accurate to judge which image rotating unit is free each time, and the control itself becomes complicated.

Therefore, in this embodiment, the tile bus (10
When the unit controller of the image rotating unit 1 or 2 is sent from the master as a target, the bus controller unit included in 48) looks at the state of each image rotating unit and transfers it to the empty rotating unit. Control is performed to easily and efficiently operate the image rotation unit. FIG. 13 shows a flowchart of control performed by the bus controller during packet transfer.

First, when the master wants to transfer data to the target, it issues a request signal indicating a transfer request and the unit ID of the transfer destination (S1301).

The bus controller monitors the busy signal which indicates whether the target is connected to another master. That is, it is determined whether the target is in use (S1302).

If the target is not busy, that is, if the target is not in use in step S1302, a grant signal indicating connection permission to the master and a UnitID of the connected target are asserted. At the same time, the start signal indicating the start of connection is asserted to the slave, the master and the target are connected to the bus, and the data packet transfer is executed (step S130).
3).

After the data transfer, when the target busy signal is deasserted, the arbiter deasserts the grant signal to the master to disconnect the bus connection.

On the other hand, the bus controller stores the function information indicating the function of each image processing unit in advance, and if the target for which the transfer request is made is busy, that is,
If it is determined in step S1302 that the target is in use, a target having the same function information is searched. When the alternative target is searched, the state of the target is monitored and it is determined whether the data packet can be transferred (S1304).

If transfer is possible, the alternative target and the master are connected. If the unit ID asserted by the bus controller is different from the target requested by itself, the master immediately executes ProcessInst.
change the ruction, and then execute data transfer (S1303).

When all targets that can be the transfer destination are busy and transfer is not possible, the target is set to the original U
back to nit, until a connectable target is found,
Repeat the same flow.

FIG. 14 shows a temporal flow of the above-mentioned simultaneous processing of three packets. Regarding the transmission path information of three packets, the image A is the rotating unit 1 (1056), and the image B is the rotating unit 2 (105).
7), the image C specifies the rotating unit 2 (1057).
After the data processing is started, packet transfer is performed based on the transfer route information while there is no competition in the rotating unit.
In the third packet of, the rotating unit 2 is used by the packet of the image B. On the contrary, the rotating unit 1 has completed the packet transfer of the image A and is in the empty state. At this time, the transmission route information of the packet of the image C is rewritten by the bus controller and transferred to the rotating unit 1 for processing.

As described above, according to the present embodiment, when a conflict of image processing units occurs, another image processing unit in the empty state is determined as an alternative image processing unit and the transmission path information in the header is rewritten. By performing packet transfer by means of packet transfer, the processing efficiency of the device can be improved.

(Other Embodiments) The present invention includes the above-mentioned first to third embodiments.
However, the present invention is not limited to this embodiment. For example, in the third embodiment, the bus controller is configured to hold the function information indicating the function of each image processing unit in advance. However, it is possible to update the function information programmatically according to the operation mode. It doesn't matter. In addition, the function information may be registered in the header information of the packet and the master may notify the bus controller of the function information.

[0119]

As described above, according to the present invention, when the unique information of the transmission block satisfies the predetermined condition, the packet is transferred from the transmission block to the predetermined storage block, and the transferred packet is stored in the storage block. Temporarily stored in the storage block, the packet once stored in the storage block,
By transferring to the reception block based on the header information, for example, the influence of the transmission block with a slow data transfer rate can be minimized. Therefore, even when different packets are processed at the same time, transmission and reception of packets between blocks are performed. Is effective.

When the processing block of the transmission destination cannot accept the packet from the processing block of the transmission source, the alternative transmission destination is determined based on the unique information of the processing block,
By sending the packet to the determined alternative destination,
Since data can be transferred to an empty block for processing, there is an effect that data processing can be efficiently executed even when different packets are simultaneously processed.

If the transmission rate of the first transmission block is slower than the transmission rate of the second transmission block, then the first transmission block
Data of the packet transmitted from the transmission block of the second transmission block is sequentially stored in the storage block, and data of the packet transmitted from the second transmission block is transferred to the reception block, and the storage block is transmitted from the first transmission block. Transfer of the data to the receiving block is temporarily stopped after the transfer of the data to the receiving block, and the data from the first transmitting block stored in the storage block is transferred to the storage block. By transferring to the receiving block, it is possible to minimize the influence of the sending block, which has a relatively low data transfer rate. Therefore, even when different packets are processed at the same time, it is possible to efficiently send and receive packets between blocks. The effect is that it can be done.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration diagram of an image processing apparatus to which the present invention can be applied in a first embodiment.

FIG. 2 is a configuration diagram of an entire network system including an image processing device of the present invention.

FIG. 3 is a diagram showing in detail a data packet obtained by packetizing image data.

FIG. 4 is a diagram showing a temporal processing flow when a packet is processed by the binarization processing unit and the image rotation unit 1.

FIG. 5 is a diagram showing a temporal processing flow when a resolution conversion unit and an image rotation unit 1 process a packet.

6 is a diagram showing a temporal processing flow when the processing of FIG. 4 and the processing of FIG. 5 are flown in parallel.

FIG. 7 is a diagram showing a flowchart in the case where an image processing unit transfers to a target as a master.

8 is a diagram showing a temporal process flow when the process of the flowchart of FIG. 7 is applied and the process of FIG. 4 and the process of FIG. 5 are flown in parallel.

FIG. 9 is a diagram illustrating an overall configuration unit of an image processing apparatus according to a second embodiment.

FIG. 10 is a diagram comparing the data flow in the first embodiment and the data flow in the second embodiment.

FIG. 11 is a diagram showing a block configuration of an image processing apparatus according to a third embodiment.

FIG. 12 is a data flow when another unit of the same image rotation unit is provided.

FIG. 13 is a diagram showing a flowchart of control performed by the bus controller during packet transfer.

FIG. 14 is a diagram showing a temporal flow of simultaneous processing of three packets.

FIG. 15 is a block diagram simply showing an image processing hardware unit in an information processing apparatus proposed by the present applicant.

[Explanation of symbols]

1001 controller unit 1002 scanner 1003 printer 1041 image processing unit 1048 tile bath 1056 Image rotation unit 1057 Resolution converter 1058 Temporary storage section 2150 System control unit 9055 Resolution converter 2

Claims (16)

[Claims] 1. An information processing apparatus for processing a packet composed of data and a header including information about the data, the packet being transmitted to a predetermined destination based on the information of the header. A transmitting unit, a receiving unit that receives the packet sent from the transmitting unit, a storing unit that temporarily stores the packet, and a bus between the transmitting unit, the receiving unit, and the storing unit. And a control means for controlling the transfer of the packet via, when the unique information of the transmission means satisfies a predetermined condition, the control means transfers the packet from the transmission means to the storage means, An information processing device, characterized in that the packet once stored in the storage means is transferred to the receiving means. 2. The control unit transfers the packet directly from the transmitting unit to the receiving unit when the unique information of the transmitting unit does not satisfy the predetermined condition. Information processing equipment. 3. The predetermined condition relates to an ID number of the transmitting means, and the ID number is a predetermined ID.
If the number is a number, the control means transfers the packet from the transmission means to the storage means, and transfers the packet once stored in the storage means to the reception means. The information processing device according to item 1 or 2. 4. The information processing apparatus according to claim 3, wherein the control unit determines whether the data transfer rate of the transmission unit is high or low based on the ID number of the transmission unit. 5. The predetermined condition relates to a data transfer rate of the transmitting means, and when the data transfer rate of the transmitting means is slow, the control means transfers the packet from the transmitting means to the storing means. 5. The information processing apparatus according to claim 1, further comprising: transferring the packet, and transferring the packet once stored in the storage unit to the receiving unit. 6. A plurality of processing blocks for performing predetermined processing on the packet are connected to the bus, and each processing block includes the transmitting means, the receiving means, and both the transmitting means and the receiving means. The information processing apparatus according to claim 1, further comprising: 7. An information processing apparatus for processing a packet composed of data and a header containing information about the data, the packet being sent from a predetermined transmission source, and the predetermined processing being performed. And a plurality of processing means for transmitting the processed packet to a predetermined destination based on the information of the header, and a control means for controlling the transfer of the packet via the bus between the plurality of processing means. If the processing means of the transmission destination cannot accept the packet from the processing means of the transmission source, the control means determines an alternative transmission destination based on the unique information of the processing means, and sends it to the determined alternative transmission destination. An information processing apparatus, which transmits the packet. 8. The header includes transmission route information of the packet, and when the processing means at the transmission destination cannot accept the packet due to competition of processing regarding a plurality of packets, the control means is Based on the unique information of the processing means, it is judged whether or not the packet can be transferred to another processing means as the alternative transmission destination, and if the packet can be transferred, the transfer route information is rewritten and the packet is transferred. The information processing device according to claim 7. 9. The unique information is information representing a data processing function of each processing unit, and the control unit sets another processing unit having the same function as the data processing function of the transmission destination as an alternative transmission destination. The information processing apparatus according to claim 7, wherein the information processing apparatus comprises: 10. The information processing apparatus according to claim 7, wherein the control unit stores the unique information in advance. 11. The information processing apparatus according to claim 7, wherein the unique information is programmable and can be updated according to an operation state of the apparatus. 12. The information processing apparatus according to claim 7, wherein the unique information is registered in the header and transmitted from the processing means to the control means. 13. An information processing apparatus for processing a packet composed of data and a header including information about the data, the packet being transmitted to a predetermined destination based on the information of the header. A plurality of transmitting means, a receiving means for receiving a packet sent from a predetermined transmission source, a storing means for storing the packet, and a bus between the transmitting means, the receiving means, and the storing means. Control means for controlling the transfer of the packet via the first transmission means, and the transmission speed of the first transmission means is slower than the transmission speed of the second transmission means. The data of the packet to be transmitted is sequentially stored in the storage means, the data of the packet transmitted from the second transmitting means is transferred to the receiving means, and the data of the packet is transmitted from the first transmitting means. After the transfer of the data to the means is completed, the transfer of the data from the second transmitting means to the receiving means is temporarily stopped, and the data from the first transmitting means stored in the storing means is transferred. An information processing device for transferring to the receiving means. 14. A data transfer method for transferring a packet composed of data and a header containing information about the data from a transmission block to a reception block via a bus based on the information of the header. If the unique information of the transmission block satisfies a predetermined condition, the packet is transferred from the transmission block to a predetermined storage block, the transferred packet is temporarily stored in the storage block, and the storage block The data transfer method, wherein the packet once stored in the packet is transferred to the reception block based on the header information. 15. A data transfer method for transferring a packet via a bus between a plurality of processing blocks for processing a packet composed of data and a header containing information about the data. When the processing block of the transmission destination cannot accept the packet from the processing block of the transmission source, an alternative transmission destination is determined based on the unique information of the processing block, and the packet is transmitted to the determined alternative transmission destination. Characteristic data transfer method. 16. A data transfer for transferring a packet composed of data and a header including information about the data from a plurality of transmission blocks to a reception block via a bus based on the information of the header. When the transmission rate of the first transmission block is slower than the transmission rate of the second transmission block, the method further comprises storing data of packets transmitted from the first transmission block in the storage block sequentially and The data of the packet transmitted from the second transmission block is transferred to the reception block, and after the transfer of the data from the first transmission block to the storage block is completed, the reception from the second transmission block is performed. The transfer of the data to the block is once paused, and the data from the first transmission block stored in the storage block is forwarded. Data transfer method, characterized by transferring to the receiving block.