JP2006229306A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost of a system employing a low speed printer by not accessing a third or fourth memory thereby reducing a memory module. <P>SOLUTION: The image processing apparatus comprises a first semiconductor substrate provided with a system control section including a CPU, an image expansion circuit, an image processing circuit, and a second semiconductor substrate provided with a multiplexer or a selector for switching the path to a memory interface, and a plurality of memory interfaces for connection with a memory module or a memory device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit configuration for image processing of a printing apparatus such as a copier, a printer, and an MFP (Multi Function Peripheral) facsimile apparatus.

  A conventional apparatus of the present invention and its operation will be described.

[hardware]
Overall Configuration The overall configuration diagram is shown in FIG.

  The Controller Unit (2000) is connected to a scanner (2070) that is an image input device and a printer (2095) that is an image output device, and on the other hand, is connected to a LAN (2011) or a public line (WAN) (2051). This is a controller for inputting / outputting information and device information and developing images of PDL data.

  A CPU (2001) is a processor that controls the entire system. In this embodiment, an example using two CPUs is shown. These two CPUs are connected to a common CPU bus (2126) and further connected to a system bus bridge (2007).

  The system bus bridge (2007) is a bus switch, and includes a CPU bus (2126), a RAM controller (2124), a ROM controller (2125), an IO bus 1 (2127), a sub bus switch (2128), and an IO bus 2 (2129). ), The image ring interface 1 (2147) and the image ring interface 2 (2148) are connected.

  The sub bus switch (2128) is a second bus switch to which the image DMA1 (2130), the image DMA2 (2132), the font expansion unit (3134), the sort circuit (2135), and the bitmap trace unit (2136) are connected. Then, the memory access request output from these DMAs is arbitrated to connect to the system bus bridge.

  A RAM (2002) is a system work memory for operating the CPU (2001), and is also an image memory for temporarily storing image data. In this embodiment, which is controlled by the RAM controller (2124), an example in which a direct RDRAM is employed is shown.

  A ROM (2003) is a boot ROM, which stores a system boot program. It is controlled by the ROM controller (2125).

  The image DMA1 (2130) is connected to the image compression unit (3131), controls the image compression unit (2131) based on information set through the register access ring (2137), and is on the RAM (2002). In this embodiment, in which uncompressed data is read, compressed, and compressed data is written back, an example in which JPEG is adopted as a compression algorithm is shown.

  The image DMA2 (2132) is connected to the image expansion unit (2133), controls the image expansion unit (2133) based on the information set through the register access ring (2137), and is on the RAM (2002). In this embodiment, in which compressed data is read, decompressed, and data is written back after decompression, JPEG is used as the decompression algorithm.

  The font decompression unit (2134) is a compressed font data stored in the ROM (2003) or RAM (2002) based on the font code included in the PDL data transferred from the outside via the LAN interface (2010) or the like. Stretching. In this embodiment, an example in which the FBE algorithm is adopted has been shown.

  The sort circuit (2135) is a circuit that rearranges the order of the objects in the display list generated at the stage of developing the PDL data.

  The bitmap trace circuit (2136) is a circuit that extracts edge information from bitmap data.

  The IO bus 1 (2127) is a kind of internal IO bus, and includes a standard USB bus controller, a USB interface (2138), a general-purpose serial port (2139), an interrupt controller (2140), and a GPIO interface (2141). Connected. The IO bus 1 includes a bus arbiter (not shown).

  An operation unit I / F (2006) is an operation unit (UI) (2012) and an interface unit, and outputs image data to be displayed on the operation unit (2012) to the operation unit (2012). Also, it plays a role of transmitting information input by the system user from the operation unit (2012) to the CPU (2001).

  The IO bus 2 (2129) is a kind of internal IO bus, and is connected to the general-purpose bus interfaces 1 and 2 (2142) and the LAN controller (2010). The IO bus 2 includes a bus arbiter (not shown).

  The general-purpose bus interface (2142) is a bus bridge that includes two identical bus interfaces and supports a standard IO bus. In this embodiment, an example in which the PCI bus (2143) is employed has been shown.

  An HDD (2004) is a hard disk drive that stores system software and image data. It is connected to one PCI bus (2143) via the disk controller (2144).

  The LAN controller (2010) is connected to the LAN (2011) via the MAC circuit (2145) and the PHY / PMD circuit (2146), and inputs and outputs information.

  The Modem (2050) is connected to the public line (2051) and inputs / outputs information.

  The image ring interface 1 (2147) and the image ring interface 2 (2148) connect the system bus bridge (2007) and the image ring (2008) for transferring image data at high speed, and the compressed data after tiling is stored in RAM ( 2002) and a tile controller (2149).

  The image ring (2008) is configured by a combination of a pair of unidirectional connection paths (image ring 1 and image ring 2). The image ring (2008) includes a tile expansion unit (2103), a command processing unit (2104), a status via the image ring interface 3 (2101) and the tile image interface 4 (2102) in the tile image processing unit (2149). The processing unit (2105) and the tile compression unit (2106) are connected. In the present embodiment, an example is shown in which two sets of tile expansion units (2103) and three sets of tile compression units are mounted.

  The tile expansion unit (2103) is connected to the tile bus (2107) in addition to the connection to the image ring interface, and expands the compressed image data input from the image ring and transfers the compressed image data to the tile bus (2107). It is a bridge. In the present embodiment, an example is shown in which JPEG is used as multi-value data and Pacbits are used as decompression algorithms for binary data.

  The tile compression unit (2106) is connected to the tile bus (2107) in addition to the connection to the image ring interface, compresses the uncompressed image data input from the tile bus, and transfers the compressed image data to the image ring (2008). It is a bridge. In the present embodiment, an example is shown in which JPEG is used for multi-value data, and Packbits is used as a compression algorithm for binary data.

  The command processing unit (2104) is connected to the register setting bus (2109) in addition to the connection to the image ring interface, and receives a register setting request issued from the CPU (2001) input via the image ring. Write to the corresponding block connected to (2109). Further, based on a register read request issued by the CPU (2001), information is read from the corresponding register via the register setting bus. The image is transferred to the image ring interface 4 (2102). The status processing unit (2105) monitors information of each image processing unit, generates an interrupt bucket for issuing an interrupt to the CPU (2001), and outputs it to the image ring interface 4.

  In addition to the above blocks, the following functional blocks are connected to the tile bus (2107).

  Rendering unit interface (2110), image input interface (2112), image output interface (2113), multi-value conversion unit (2119), binarization unit (2118), color space conversion unit (2117), image rotation unit (2030) ), A first resolution converter (2116).

  The rendering unit interface (2110) is an interface for inputting a bitmap image generated by a rendering unit described later. The rendering unit and the rendering unit interface are connected by a general video signal (2111). The rendering unit interface has a connection to the memory bus (2108) and the register setting bus (2109) in addition to the tile bus (2107), and the input raster image is set via the register setting bus, and is a predetermined one. The structure is converted into a tile image by the above method, and at the same time, the clock is synchronized and output to the tile bus (2107).

  The image input interface (2112) receives raster image data subjected to correction image processing by a scanner image processing unit (2114) to be described later, and inputs the raster image data to the tile image by a predetermined method set via the register setting bus. The structure conversion and clock synchronization are performed and output to the tile bus (2107).

  The image output interface receives tile image data from the tile bus, converts the structure into a raster image and changes the clock rate, and outputs the raster image to the printer image processing unit (2115).

  An image rotation unit (2030) rotates image data.

  The first resolution conversion unit (2116) changes the resolution of the image.

  A color space conversion unit (2117) converts the color space of the color and gray scale image.

  A binarization unit (2118) binarizes a multi-value (color, gray scale) image.

  A multi-value conversion unit (2119) converts a binary image into multi-value data.

  The external bus interface unit (2120) sends write / read requests issued by the CPU (2001) via the image ring interfaces 1, 2, 3, 4, command processing unit, and register setting bus to the external bus 3 (2121). This is a bus bridge that converts and outputs to In this embodiment, the external bus 3 (2121) is connected to the printer image processing unit (2115) and the scanner image processing unit (2114).

  The memory control unit (2122) is connected to the memory bus (2108), and in accordance with the request of each image processing unit, the image data is transferred to the image memory 1 and the image memory 2 (2123) by preset address division. Write, read, and refresh operations are performed as necessary. In this embodiment, an example in which an SDRAM is used as the image memory is shown.

  The scanner image processing unit (2114) performs correction image processing on the image data scanned by the scanner (2070) as an image input device.

  The printer image processing unit performs corrected image processing for printer output, and outputs the result to the Printer (2095).

  The rendering unit (2060) develops the PDL code or the intermediate display list into a bitmap image.

  When expanding to the bitmap, if characters with a large number of strokes and a small font size are expanded into a bitmap image, the characters may be crushed and blurred, and the intervals between the strokes constituting the characters will be uneven. Is easy to happen. In order to avoid this, high-resolution bitmap image intermediate data more than double the print resolution is prepared.

  An expansion / resolution conversion unit 2170 is connected to the resolution conversion bus controlled by the resolution conversion bus controller 2160 in order to convert the resolution to the print resolution when printing the high-resolution intermediate data.

  2170 is composed of 2171 to 2180, 2171 is a decompression / resolution conversion input interface for receiving image data from 2150, 2172 is a Packbits image decompression unit for decompressing image data compressed by Packbits, and 2173 is a third RAM write. Interface, 2174 is a third RAM, 2175 is a third RAM read interface, 2176 is a resolution converter, 2177 is a fourth RAM write interface, 2178 is a fourth RAM, 2179 is a fourth RAM read interface, 2180 Is a decompression / resolution conversion output interface.

  A write access is issued from the resolution conversion bus controller 2160 and the high resolution image data compressed from 2150 is transferred to the expansion / resolution conversion input interface 2171 in 2170. The high-resolution image data compressed using the received Pack Bits compression is received by the Pack Bits image expansion unit 2172, and the Pack Bits expansion is performed. The third RAM writing interface 2173 receives the high resolution image data expanded by pack bits and writes it to the memory 2174.

  Next, the third RAM read interface 2175 reads the memory and passes the high resolution image data to the resolution conversion unit 2176.

  The resolution converter 2176 converts the resolution of the high resolution image data read from the memory in accordance with the print resolution. Here, for explanation, it is assumed that 1200 dpi image data is input from 2150 and the resolution is converted to 600 dpi in 2170.

  The fifth RAM writing interface 2177 receives the resolution-converted bitmap image data and writes it into the memory 2178.

  Next, the fifth RAM read interface 2179 reads the memory, and the decompression / resolution conversion output interface 2180 passes the bitmap image data to the system control unit in response to a read request from the resolution conversion bus controller 2160.

Note that the usage amount of the high-speed and low-capacity primary buffer is monitored, and if the primary buffer is likely to be full, the data is saved in the low-speed and large-capacity secondary buffer. A technique for transferring data from the secondary buffer to the primary buffer when the buffer full is resolved is known (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 10-200574

  However, the above-described prior art has a problem that even in a system using a low-speed printer, two memory modules, a third memory and a fourth memory, are necessary and expensive.

  The present invention has been made paying attention to the above points, and in a system using a low-speed printer, it is possible to reduce the memory modules by not accessing the third or fourth memory, thereby reducing the cost. It is an object of the present invention to provide an image processing apparatus that can be configured.

  In order to solve the above-mentioned problems, the present invention is characterized by comprising means for switching whether or not to access a memory module.

  If it demonstrates in detail, this invention could solve the said subject with the following structure.

  (1) A first semiconductor substrate having a system control unit including a CPU, an image expansion circuit, an image processing circuit, and a multiplexer or selector for switching a path to a memory interface. An image processing apparatus comprising: a second semiconductor substrate having a plurality of memory interfaces for connection.

  According to the present invention, in a system using a low-speed printer, it is possible to reduce memory modules by reducing access to the third or fourth memory, thereby reducing the cost.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples.

  FIG. 7 is a diagram that best represents the embodiment of the present invention. In FIG. 7, reference numeral 7000 denotes an expansion / resolution conversion unit that performs image expansion and resolution conversion, which is an improvement over the conventional 2170, and is an MFP controller. Used to replace 2170 and 7000 on the system.

  The decompression / resolution conversion unit 7000 according to the present invention includes 2171 to 2180 and 7001 to 7004, 2171 is an decompression / resolution conversion input interface for receiving image data from 2150, and 2172 is a pack for decompressing pack-bits compressed image data. Bits image decompression unit, 7001 is a selector for allocating the output destination of the pack bits image decompression unit, 2173 is a third RAM write interface, 2174 is a third RAM, 2175 is a third RAM read interface, and 7002 is a third RAM A multiplexer for selecting the image data from the memory reading unit 2175 or the image data from the selector 7001, 2176 is a resolution conversion unit, 7003 is a selector for distributing the output destination of the resolution conversion unit 2176, 21 7 is a fourth RAM write interface, 2178 is a fourth RAM, 2179 is a fourth RAM read interface, and 7004 is for selecting image data from the fourth memory read unit 2179 or image data from the selector 7003. A multiplexer 2180 is an expansion / resolution conversion output interface.

  The selectors 7001 and 7003 and the multiplexers 7002 and 7003 are switched by a register (not shown) in the expansion / resolution conversion unit 7000 prior to image processing.

  The operations for the high speed, medium speed, and low speed image processing apparatuses of the circuit of FIG. 7 will be described below.

  FIG. 8 is a diagram for explaining the operation when the circuit of FIG. 7 is for a high-speed image processing apparatus, and uses both the third and fourth RAMs 2174 and 2178.

  In FIG. 8, prior to image processing, the resolution conversion bus controller 2160 performs write access to a register (not shown) in the decompression / resolution conversion unit 7000 through the resolution conversion bus, and the connection destination of the selector 7001 is the memory write circuit 2173, The expansion / resolution conversion unit 7000 when the register is set so that the connection destination of the multiplexer 7002 is the memory read circuit 2175, the connection destination of the selector 7003 is the memory write circuit 2177, and the connection destination of the multiplexer 7004 is the memory read circuit 2179. It is a figure for demonstrating operation | movement of.

  In FIG. 8, a write access is issued from the resolution conversion bus controller 2160 and high-resolution image data compressed from 2150 is transferred to the expansion / resolution conversion input interface 2171 in 2170. The pack-bits image expansion unit 2172 receives high-resolution image data compressed using pack-bits compression, and performs pack-bit expansion. The selector 7001 has a register setting so that the pack bits expansion unit 2172 and the third RAM write interface 2173 are connected. The third RAM write interface 2173 has high resolution image data expanded by the pack bits expansion unit 2172. Is written into the memory 2174. Next, the third RAM read interface 2175 reads the memory. The multiplexer 7002 is set so that the RAM read interface 2175 and the resolution conversion unit 2176 are connected. The resolution conversion unit 2176 matches the high resolution image data read by the third RAM read interface 2173 with the print resolution. Convert the resolution. Here, for explanation, it is assumed that 1200 dpi image data is input from 2150 and the resolution is converted to 600 dpi in 2170.

  The selector 7003 is set so that the resolution conversion unit 2176 and the RAM writing interface 2177 are connected. The bitmap image data whose resolution has been converted is received by the fifth RAM writing interface 2177 through the selector 7003 and written to the memory 2178.

  Next, the fifth RAM read interface 2179 reads the memory. The multiplexer 7004 is set in a register so that the resolution RAM read interface 2179 and the expansion / resolution conversion output interface 2180 are connected, and the bitmap image data from the fifth RAM read interface 2179 is transmitted to the expansion / resolution conversion output interface 2180. Then, in response to a read request from the resolution conversion bus controller 2160, the decompression / resolution conversion output interface 2180 passes the bitmap image data to the system control unit.

  As described above, in the case of a high-speed image processing apparatus, image processing using both the third and fourth RAMs 2174 and 2178 is performed. By using both the third and fourth RAMs 2174 and 2178, it becomes possible for the decompression / resolution conversion unit 7000 to receive a large amount of data, and the image processing can be speeded up by increasing the processing unit called a band. .

  FIG. 9 is a diagram for explaining the operation when the circuit of FIG. 7 is for a high-speed image processing apparatus, and uses both the third and fourth RAMs 2174 and 2178.

  In FIG. 9, prior to image processing, the resolution conversion bus controller 2160 performs write access to a register (not shown) in the decompression / resolution conversion unit 7000 through the resolution conversion bus, and the connection destination of the selector 7001 is the multiplexer 7002 and the multiplexer 7002. Operation of the expansion / resolution conversion unit 7000 when the register is set to the resolution conversion circuit 2176, the selector 7003 is connected to the memory write circuit 2177, and the multiplexer 7004 is connected to the memory read circuit 2179. It is a figure for demonstrating.

  In FIG. 9, a write access is issued from the resolution conversion bus controller 2160 and high-resolution image data compressed from 2150 is transferred to the expansion / resolution conversion input interface 2171 in 2170. The pack-bits image expansion unit 2172 receives high-resolution image data compressed using pack-bits compression, and performs pack-bit expansion. The selector 7001 is register-set so that the image expansion unit 2172 and the multiplexer 7002 are connected, the multiplexer 7002 is register-set so that the selector 7001 and the resolution conversion unit 2176 are connected, and the resolution conversion unit 2176 is the image expansion unit 2172. The resolution of the high-resolution image data expanded in step 1 is converted according to the print resolution. Here, for explanation, it is assumed that 1200 dpi image data is input from 2150 and the resolution is converted to 600 dpi in 2170.

  The selector 7003 is set so that the resolution conversion unit 2176 and the RAM writing interface 2177 are connected. The bitmap image data whose resolution has been converted is received by the fifth RAM writing interface 2177 through the selector 7003 and written to the memory 2178.

  Next, the fifth RAM read interface 2179 reads the memory. The multiplexer 7004 is set in a register so that the resolution RAM read interface 2179 and the expansion / resolution conversion output interface 2180 are connected, and the bitmap image data from the fifth RAM read interface 2179 is transmitted to the expansion / resolution conversion output interface 2180. Then, in response to a read request from the resolution conversion bus controller 2160, the decompression / resolution conversion output interface 2180 passes the bitmap image data to the system control unit.

  As described above, in the case of a medium-speed image processing apparatus, image processing using the fourth RAM 2178 is performed without using the third RAM 2174. By not using the third RAM 2174, the cost of the third RAM 2174 can be reduced.

  Here, instead of using the fourth RAM 2178, a third RAM 2174 can be connected to configure a medium-speed image processing apparatus.

  FIG. 10 is a diagram for explaining the operation when the circuit of FIG. 7 is for a low-speed image processing apparatus, and neither the third RAM 4174 nor the second RAM 2178 is used.

  In FIG. 10, prior to image processing, the resolution conversion bus controller 2160 performs write access to a register (not shown) in the decompression / resolution conversion unit 7000 through the resolution conversion bus, and the connection destination of the selector 7001 is the multiplexer 7002 and the multiplexer 7002. In order to explain the operation of the expansion / resolution conversion unit 7000 when the register is set to the selector 7001, the connection destination of the selector 7003 is the multiplexer 7004, and the connection destination of the multiplexer 7004 is set to expansion / resolution conversion. FIG.

  In FIG. 10, a write access is issued from the resolution conversion bus controller 2160 and high-resolution image data compressed from 2150 is transferred to the expansion / resolution conversion input interface 2171 in 2170. The pack-bits image expansion unit 2172 receives high-resolution image data compressed using pack-bits compression, and performs pack-bit expansion. The selector 7001 is register-set so that the Packbits expansion unit 2172 and the multiplexer 7002 are connected, the multiplexer 7002 is register-set so that the image expansion unit 2172 and the resolution conversion unit 2176 are connected, and the resolution conversion unit 2176 The high resolution image data expanded by the expansion unit 2172 is subjected to resolution conversion in accordance with the print resolution. Here, for explanation, it is assumed that 1200 dpi image data is input from 2150 and the resolution is converted to 600 dpi in 2170.

  The selector 7003 registers the bitmap image data subjected to resolution conversion so that the expansion / resolution conversion output interface 2180 is connected through the selector 7003 and the multiplexer 7004, and the image data is transmitted to the expansion / resolution conversion output interface 2180.

  Next, in response to a read request from the resolution conversion bus controller 2160, the decompression / resolution conversion output interface 2180 passes the bitmap image data to the system control unit.

  As described above, both the third and fourth RAMs 2174 and 2178 are not used for a low-speed image processing apparatus. By not using both the third and fourth RAMs 2174 and 2178, the cost can be reduced.

  The register setting at 7000 will be described. Prior to image transfer, register setting is performed on a register (not shown) in the expansion / resolution conversion unit 7000 through the expansion / resolution conversion bus controller 2160 of the system control unit 2150.

  The register is a register that stores a start address of a memory to be secured on the memory 2174 and a data size area to be secured on the memory 2174, and a top address of the memory to be secured on the memory 2178, and is secured on the memory 2178. There are a register for storing a data size area, a register for setting the connection state of the selectors 7001 and 7003 and the multiplexers 7002 and 7004, and a register for starting data transfer.

  The decompression / resolution conversion unit input interface 2171 has a buffer (not shown). After a value indicating the start of data transfer was written in the register for starting data transfer, the buffer of the expansion / resolution conversion unit input interface 2171 was less than the transfer data size of the resolution conversion bus twice. In this case, the decompression / resolution conversion unit input interface 2171 sets a buffer full signal of the resolution conversion bus. When the buffer full signal of the resolution conversion bus is set, the expansion / resolution conversion bus controller 2160 does not start a new data write transfer. When the buffer full signal of the resolution conversion bus is not raised, the expansion / resolution conversion unit input interface 2171 receives the write request from the expansion / resolution conversion bus controller 2160 and receives the image data.

  The decompression / resolution conversion unit output interface 2180 has a buffer (not shown). After the value indicating the start of data transfer is written in the register for starting data transfer, the valid data in the buffer of the expansion / resolution conversion unit output interface 2180 is larger than the transfer data size of one time of the resolution conversion bus. If there are fewer, the decompression / resolution conversion unit output interface 2180 raises a buffer empty signal of the resolution conversion bus. When the buffer empty signal of the resolution conversion bus is set, the expansion / resolution conversion bus controller 2160 does not start a new data read transfer. When the resolution conversion bus buffer empty signal is not set, the expansion / resolution conversion unit output interface 2180 receives a read request from the expansion / resolution conversion bus controller 2160 and transmits image data.

  For the purpose of explanation here, the image decompression unit 2171 has been described as being Pacbits, but it is not necessarily Pacbits, and what is the image compression algorithm such as run length, JPEG, MMR, MH, JBIG? The object of the present invention can also be achieved.

[Whole system]
A configuration diagram of the entire network system of the present invention is shown in FIG.

  An apparatus 1001 according to the present invention includes a scanner and a printer. An image read from the scanner can be sent to a local area network (1010) (hereinafter referred to as LAN), and an image received from the LAN can be printed out by a printer. Further, the image read from the scanner can be transmitted to the PSTN or ISDN (1030) by a FAX transmission means (not shown), and the image received from the PSTN or ISDN can be printed out by the printer. Reference numeral 1002 denotes a database server which manages binary images and multi-valued images read by the apparatus (1001) of the present invention as a database.

  Reference numeral 1003 denotes a database client of the database server (1002), which can browse / search image data stored in the database (1002).

  An e-mail server 1004 can receive an image read by the apparatus (1001) of the present invention as an e-mail attachment. Reference numeral 1005 denotes an e-mail client that can receive and browse e-mail received by the e-mail server (1004) and send e-mail.

  Reference numeral 1006 denotes a WWW server that provides an HTML document to a LAN, and an HTML document provided by the WWW server can be printed out by the apparatus (1001) of the present invention.

  Reference numeral 1007 denotes a router that connects the LAN (1010) to the Internet / intranet (1012). The database server (1002), WWW server (1006), e-mail server (1004), and apparatus similar to the apparatus (1001) of the present invention are connected to the Internet / intranet as 1020, 1021, 1022, and 1023, respectively. ing. On the other hand, the apparatus (1001) of the present invention can transmit and receive with the FAX apparatus (1031) via the PSTN or ISDN (1030).

  A printer (1040) is also connected to the LAN, and is configured to print out an image read by the apparatus (1001) of the present invention.

[Tile image (packet) format]
In the System Controller Unit (2000) according to the present invention, image data, commands from the CPU (2001), and interrupt information issued from each block are transferred in a packetized form.

  In this embodiment, three different types of packets are used: a data packet shown in FIG. 3, a command packet shown in FIG. 4, and an interrupt packet shown in FIG.

Data packet (Figure 3)
In this embodiment, an example in which the image data is handled by being divided into image data (3002) in units of Tile of 32 pixels × 32 pixels is shown.

  Necessary header information (3001), image additional information, etc. (3003) are added to this Tile unit image to form a data packet.

  Information included in the header information (3001) will be described below.

  The packet type is distinguished by the PcktType (3004) in the header information (3001). PcktType (3004) includes a repeat flag. If the Data Packet image Data is the same as the previous Data Packet image Data, the Repeat flag is set.

  ChipID (3005) indicates the ID of a target chip that transmits a packet.

  DataType (3006) indicates the type of data.

  PageID (3007) indicates a page, and JobID stores Job ID (3008) for management by software.

  The Tile number is a combination of the Y-direction Tile coordinate (3009) and the X-direction Tile coordinate (3010), and is represented by YnXn.

  Data packets may be compressed or uncompressed. In the present embodiment, as an example of compression algorithm, JPEG is used for multi-valued colors (including multi-value grayscale), and Pacbits are used for binary values.

  A distinction between compressed and uncompressed is indicated by CompressFlag (3017).

  Process Instruction (3011) is left-justified and set in the processing order, and each process unit performs 8-bit shift to the left after the process instruction. In Process Instruction (3011), eight sets of UnitID (3019) and Mode (3020) are stored. UnitID (3019) designates each process unit, and Mode (3020) designates an operation mode in each process unit. As a result, one packet can be processed continuously in eight units.

  PacketByteLength (3012) indicates the total number of bytes of the packet.

  ImageDataByteLength (3015) represents the number of bytes of image data, ZDataByteLength (3016) represents the number of bytes of image additional information, and ImageDataOffset (3013) and ZDataOffset (3014) represent the Offset from the head of each data packet.

Packet Table (Figure 6)
Each packet is managed by a packet table (6001).

  The components of the packet table (6001) are as follows. When 0 is added to the value of the table, 5 bits are added to the top address (6002) of the packet and the byte length (6005) of the packet.

Packet Address Pointer (27 bits) + 5b00000 = Packet head Address
Packet Length (11 bits) + 5b00000 = Packet Byte Length
The packet table (6001) and the chain table (6010) are not divided.

The Packet Table (6001) is always arranged in the scanning direction, and Yn / Xn = 000 / 000,000 / 001,000 / 002,. . . . It is lined up in this order. The entry of the packet table (6001) uniquely indicates one tile. In addition, the following Entry of Yn / Xmax becomes Yn + 1 / _{X 0.}

  When the packet is exactly the same data as the previous packet, the packet is not written on the memory, and the same packet address pointer and packet length as the first entry are stored in the entry of the packet table. A single packet data is pointed to by two table entries. In this case, Repeat Flag (6003) of the second Table Entry is set.

  When the packet is divided into a plurality by Chain DMA, the Divide Flag (6004) is set, and the Chain Table number (6006) of the Chain Block containing the head portion of the packet is set.

  The entry of the chain table (6010) is composed of a chain block address (6011) and a chain block length (6012), and 0 is stored in both the address and the length of the last entry of the table.

Command Packet Format (Figure 4)
This Packet Format is used to access the register setting bus (2109). By using this packet, the COU (2001) can also access the image memory (2123).

  The ChipID (4004) stores an ID representing the image processing unit (2149) that is the transmission destination of the command packet.

  Page ID (4007) and Job ID (4008) store Page ID and Job ID for management by software.

  Packet ID (4009) is expressed in one dimension. Only X-coordinate of Data Packet is used.

  The packet byte length (4010) is fixed to 128 bytes.

  The packet data part (4002) can store a maximum of 12 commands, with a set of address (4011) and data (4012) as one command. The type of command for writing or reading is indicated by CmdType (4005), and the number of commands is indicated by Cmdnum (4006).

Interrupt Packet Format (Figure 5)
This PacketFormat is for notifying an interruption from the image processing unit (2149) to the CPU (2001). When the status processing unit (2105) transmits the interrupt packet, the status processing unit (2105) must not transmit the interrupt packet until the next transmission is permitted.

  The packet byte length (5006) is fixed to 128 bytes.

  The packet data part (5002) stores status information (5007) of each internal module of the image processing part (2149). The status processing unit (2105) can collect the status information of each module in the image processing unit (2149) and collectively send it to the system control unit (2150).

  In ChipID (5004), an ID representing the system control unit (2150) that is the destination of the Interrupt Packet is stored. In IntChipID (5005), an ID representing the image processing unit (2149) that is the source of the Interrupt Packet is stored. Is done.

The figure showing the actual use environment of this system. The whole block diagram of the prior art example of this system controller. The figure showing an image packet. The figure showing a command packet. The figure showing an interrupt packet. The figure showing a packet table. The figure showing the Example of the expansion | extension / resolution conversion part of this system controller. The figure showing the operation example for the high-speed image processing apparatus of the expansion | extension / resolution conversion part of this system controller. The figure showing the operation example for medium-speed image processing apparatuses of the expansion | extension / resolution conversion part of this system controller. The figure showing the operation example for the low-speed image processing apparatus of the expansion | extension / resolution conversion part of this system controller.

Explanation of symbols

2170 Decompression / Resolution Conversion Unit 2171 Decompression / Resolution Conversion Input Interface 2172 Packbits Image Expansion Unit 2173 Third RAM Write Interface 2174 Third RAM
2175 Third RAM read interface 2176 Resolution converter 2177 Fourth RAM write interface 2178 Fourth RAM
2179 Fourth RAM read interface 2180 Decompression / resolution conversion output interface 7000 Decompression / resolution conversion unit 7001, 7003 selector 7002, 7004 multiplexer according to the present invention

Claims (15)

A first semiconductor substrate including a system control unit including a CPU;
Has an image expansion circuit, an image processing circuit, and a multiplexer or selector for switching the path to the memory interface,
A second semiconductor substrate having a plurality of memory interfaces for connecting to memory modules or memory devices;
An image processing apparatus comprising:   2. The image processing apparatus according to claim 1, wherein said image processing circuit has a smaller data size for output image data than for input image data.   The image processing apparatus according to claim 1, wherein the image processing circuit is resolution conversion.   The image processing apparatus according to claim 1, wherein the image processing circuit is image expansion. An image processing apparatus that accesses the memory interface before and after image processing; and
An image processing apparatus that accesses the memory interface only before or after image processing; and
An image processing apparatus characterized by not accessing the memory interface both before and after image processing,
The image processing apparatus according to claim 1, wherein the image processing apparatus can be set by register setting.   4. The image processing apparatus according to claim 3, wherein the image processing circuit is resolution conversion for inputting high resolution image data and outputting low resolution image data.   5. The image processing apparatus according to claim 4, wherein the image expansion circuit is a Packbits expansion circuit.   5. An image processing apparatus according to claim 4, wherein the image expansion circuit is a run-length expansion circuit.   5. The image processing apparatus according to claim 4, wherein the image expansion circuit is an MMR expansion circuit.   5. The image processing apparatus according to claim 4, wherein the image expansion circuit is an MH expansion circuit.   5. An image processing apparatus according to claim 4, wherein the image expansion circuit is a JPEG expansion circuit.   5. The image processing apparatus according to claim 4, wherein the image expansion circuit is a JBIG expansion circuit.   5. The image processing apparatus according to claim 4, wherein the image expansion circuit is a JBIG expansion circuit.   An image processing apparatus comprising a register for selecting an input source or an output destination of the selector or multiplexer according to claim 1. The bus connecting the first semiconductor substrate and the second semiconductor substrate according to claim 1 is a reception buffer full signal for notifying the first semiconductor substrate of the availability of the reception buffer in the second semiconductor substrate. A transmission buffer empty signal for notifying the first semiconductor substrate of valid data in the transmission buffer in the second semiconductor substrate;
When the reception buffer full signal indicates that the reception buffer is empty, the first semiconductor substrate issues a reception request to the second semiconductor substrate, and the transmission buffer empty signal indicates that valid data is stored in the transmission buffer. An image processing apparatus, wherein a first semiconductor substrate issues a transmission request to a second semiconductor substrate when a certain state is indicated.

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