JP2003331279A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor in which register setting can be changed in an arbitrary tile position. <P>SOLUTION: The image processor is constructed to comprise a plurality of image processing circuit blocks (image processing units) which divide an image into grid for processing. Data is transmitted in packet unit in which data attribution information such as data type, data processing destination, data processing content, data size, and data position is added to image data included in the tile. Also, the packet (command packet) for reading out or writing the registers of the image processing circuit blocks (image processing units) and the image processing data (data packet) are transmitted using the same bus. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanner, a printer, a copying machine, a composite type image processing apparatus having a network function, and more particularly to an image processing apparatus in which color, gray scale and black and white two-tone images are mixed.

[0002]

2. Description of the Related Art Heretofore, an image processing apparatus has been proposed in which an image is divided into cells having the same size as tiles and image processing is performed for each tile.

In the above-mentioned conventional example, the image data included in a tile to which data attribute information such as data type, data processing destination, data processing content, data size, and data position is added is called a packet. Make a transmission.

The image processing section will be described below with reference to FIG.

The image ring (2008) is composed of a pair of unidirectional connection paths (image ring 1 and image ring 2). Image Ring (2008) is a tile image processing unit
In (2149), the tile expansion unit (2103), the command processing unit (2104), and the status processing unit via the image ring interface 3 (2101) and the tile image interface 4 (2102).
(2105) is connected to the tile compression unit (2106). In this example,
An example is shown in which two sets of tile expansion units (2103) and three sets of tile compression units are mounted.

The tile decompression unit (2103) is connected to the tile ring (2107) in addition to the connection to the image ring interface, and decompresses the compressed image data input from the image ring to the tile bus (2107). It is a bus bridge to transfer. In this example, JPEG is used for multi-valued data and Packbits is used for decompression data as binary data.

The tile compression unit (2106) is connected to the tile ring (2107) in addition to the connection to the image ring interface, and compresses the image data before compression input from the tile bus to the image ring (2008). It is a bus bridge to transfer. In this example, JPEG is adopted for multi-valued data and Packbits is adopted for binary data as a compression algorithm.

The command processing unit (2104) has a register setting bus (2109) in addition to the connection to the image ring interface.
Connected to and input through the image ring CPU (2001)
Register setting request issued by the register setting bus
Write to the corresponding block connected to (2109). Also, CP
Based on the register read request issued by U (2001), the information is read from the corresponding register via the register setting bus and transferred to the image ring interface 4 (2102).

In addition to the above blocks, the following functional blocks are connected to the tile bus (2107).

Rendering unit interface (2110),
Image input interface (2112), image output interface (2113), multi-value conversion unit (2119), binarization unit (2118), color space conversion unit (2117), image rotation unit (2030), resolution conversion unit (211)
6).

Rendering unit interface (2110)
Is an interface for inputting a bitmap image generated by a rendering unit described later. The rendering unit and the rendering unit interface are connected by a general video signal (2111). The rendering unit interface has a connection to the memory bus (2108) and the register setting bus (2109) in addition to the tile bus (2107),
The input raster image is structurally converted into a tile image by a predetermined method set via the register setting bus, and at the same time, clocks are synchronized and output to the tile bus (2107).

The image input interface (2112) receives the raster image data that has been subjected to the corrected image processing by the scanner image processing unit (2114), which will be described later, and inputs it to a tile image by a predetermined method set via the register setting bus. Of the tile bus (210
Output to 7).

The image output interface receives tile image data from the tile bus as input, performs structural conversion to a raster image and changes the clock rate, and outputs the raster image to the printer image processing unit (2115).

The image rotation unit (2030) rotates image data. The resolution conversion unit (2116) changes the resolution of the image.

The color space conversion unit (2117) converts the color spaces of the color and grayscale images. The binarization unit (2118)
Binarize multi-valued (color, grayscale) images.

A multi-value conversion unit (2119) converts a binary image into multi-value data.

The external bus interface unit (2120) issues write and read requests issued by the CPU (2001) via the image ring interfaces 1, 2, 3, 4, the command processing unit, and the register setting bus to the external bus 3 ( It is a bus bridge that converts and outputs to 2121). External bus 3 (2121)
In this example, is connected to the printer image processing unit (2115) and the scanner image processing unit (2114).

The memory control unit (2122) is connected to the memory bus (2108).
Are connected to the image memory 1 and the image memory 2 by preset address division according to the request of each image processing unit.
Image data is written in and read from (2123), and operations such as refreshing are performed as necessary. In this example, an example in which SDRAM is used as the image memory is shown.

The scanner image processing unit (2114) corrects and processes the image data scanned by the scanner (2070) which is an image input device.

The printer image processing unit performs a correction image process for printer output, and outputs the result to the Printer (2095).

The rendering unit (2060) develops the PDL code or the intermediate display list into a bitmap image. [Entire System] FIG. 2 shows a block diagram of the entire network system of the present invention.

An apparatus 1001 of the present invention is composed of a scanner and a printer, and an image read from the scanner can be sent to a local area network (1010) (hereinafter, LAN), or an image received from the LAN can be printed out by the printer. Further, the image read from the scanner can be transmitted to the PSTN or ISDN (1030) by a FAX transmission means (not shown), or the image received from the PSTN or ISDN can be printed out by the printer. 1002 is a database server,
The binary image and multi-valued image read by the device (1001) of the present invention are managed as a database.

Reference numeral 1003 denotes a database client of the database server (1002), which can browse / search image data stored in the database (1002).

Reference numeral 1004 denotes an electronic mail server, which is the device of the present invention.
The image read by (1001) can be received as an e-mail attachment. An e-mail client 1005 is capable of receiving and viewing e-mails received by the e-mail server (1004) and sending e-mails.

WWW 1006 provides HTML document to LAN
On the server, the HTML document provided by the WWW server can be printed out by the device (1001) of the present invention.

A router 1007 connects the LAN (1010) to the Internet / Intranet (1012). The database server (1
002), WWW server (1006), email server (1004),
Devices similar to the device (1001) of the present invention are 1020 and 102, respectively.
They are connected as 1, 1022, 1023.

On the other hand, the device (1001) of the present invention is a PSTN or IS.
It is possible to transmit and receive with the FAX machine (1031) via the DN (1030).

A printer (1040) is also connected to the LAN so that an image read by the device (1001) of the present invention can be printed out. [Tile image (packet) format] According to the conventional example
In SystemControllerUnit (2000), image data, C
PU (2001) commands and interrupt information issued by each block are transferred in packetized form.

In the conventional example, the data packet shown in FIG.
Two different types of packets are used, the command packets shown in FIG.

Data Packet (FIG. 3) In the conventional example, an example is shown in which the image data is divided into 32 pixel × 32 pixel Tile unit image data (3002) and handled.

Required header information for this Tile-based image
(3001) and image additional information (3003)
Let et.

The information contained in the header information (3001) will be described below.

The Packet Type is Pckt in the header information (3001)
It is distinguished by Type (3004). The PcktType (3004) includes a repeat flag, and when the image Data of the Data Packet is the same as the image Data of the Data Packet transmitted immediately before, the repeat flag is set.

ChipID (3005) indicates the ID of a chip that is a target for transmitting a packet.

DataType (3006) indicates the type of data.

PageID (3007) indicates a page, and JobI
D stores JobID (3008) for managing by software.

The Tile numbers are the Tile coordinates (3009) in the Y direction and the X
It is a combination of Tile coordinates (3010) of directions and is represented by YnXn.

The data packet may or may not be compressed image data. In this example, as the compression algorithm, JPEG is used in the case of multi-value color (including multi-value gray scale) and Packbits is used in the case of binary.

The distinction between the compressed case and the non-compressed case is indicated by CompressFlag (3017).

Process Instruction (3011) is set left-justified in the processing order, and each processing unit is a Process Instructio after processing.
Shift n to the left by 8 Bit. Process Instruction (3011)
Stores 8 sets of Unit ID (3019) and Mode (3020). UnitID (3019) specifies each processing unit, and Mode (3020) specifies the operation Mode in each processing unit. As a result, one packet can be continuously processed by eight units.

PacketByteLength (3012) indicates the total number of bytes in the packet.

ImageDataByteLengh (3015) represents the number of bytes of image data, ZDataByteLength (3016) represents the number of bytes of image additional information, and ImageDataOffset (3013) and ZDataOffset
(3014) is Off from the beginning of each data packet
represents a set.

Packet Table (Fig. 5) Each Packet is managed by Packet Table (6001).

The constituent elements of the Packet Table (6001) are as follows.
Start address (6002) of et, Byte Length of packet (6005)
Becomes

Packet Address Pointer (27bit) ＋ 5b0000
0 = Packet Start Address Packet Length (11bit) + 5b00000 = Packet Byte L
The ength Packet Table (6001) and the Chain Table (6010) are not divided.

The Packet Table (6001) is always arranged in the scanning direction, and is arranged in the order of Yn / Xn = 000/000, 000 / 001,000 / 002, .... Entry of this Packet Table (6001) uniquely shows one Tile. Also, the next Entry after Yn / Xmax is Yn
It becomes + 1 / X ₀ .

When the Packet has exactly the same Data as the previous Packet, the Packet is not written in the Memory, and the Packet is
Same Entry as the first Entry in Table Entry
Stores Pointer and Packet Length. 1 Packet
Data is in the form of two Table Entry points. In this case, the Repeat Flag (6003) of the second Table Entry is Se
is done.

When the Packet is divided into multiple by the Chain DMA, Divide Flag (6004) is set and the Chain Table number of the Chain Block containing the beginning of the Packet is set.
Set (6006).

Entry of Chain Table (6010) is Chain Bloc
It consists of k Address (6011) and Chain Block Length (6012), and 0 is stored for both Address and Length in the last Entry of Table.

Command Packet Format (FIG. 4) This Packet Format is for accessing the register setting bus (2109). By using this packet, the image memory (2123) can be accessed from the CPU (2001).

The ChipID (4004) stores an ID representing the image processing unit (2149) that is the destination of the command packet.

PageID (4007) and JobID (4008) store PageID and JobID for managing by software.

The Packet ID (4009) is represented in one dimension. Da
Only the X-coordinate of ta Packet is used.

Packet byte length (4010) is 128 bytes
It is fixed.

In the packet data section (4002), the address (4
It is possible to store a maximum of 12 commands, with the combination of 011) and data (4012) as one command. The command type of write or read is indicated by CmdType (4005), and the number of commands is indicated by Cmdnum (4006).

Tile Configuration (FIG. 6) In FIG. 6, tile coordinates and image coordinates are defined from the upper left, and the tile coordinates and image coordinates are (0, 0) at the upper left. In FIG. 6, Tile (0,0) and the like indicate one tile, and the numbers in the brackets indicate tile coordinates (X, Y). The X coordinate of the tile coordinates is set to increase from left to right, and the Y coordinate of the tile coordinates is set to increase from top to bottom. Paper size is A4 (horizontal), resolution is
When the size of one tile is 32 × 32 pixels at 600 dpi, one page has 220 (horizontal) × 156 (vertical) tiles.

[0057]

However, the conventional technique has a problem that register setting cannot be performed in synchronization with image processing. Generally, the image processing coefficient and the image processing mode are switched by register setting, but in the conventional technology, since the tile bus and the register setting bus operate independently, register settings are synchronized with the image. The setting cannot be changed and the coefficient of image processing and the image processing mode cannot be optimally changed according to the image, such as when the characteristics of the image change in the middle of the page. If the setting is changed during the image processing, the image is disturbed in most cases.

The present invention has been made in view of the above problems, and an object thereof is to provide an image processing apparatus capable of changing register settings at arbitrary tile positions.

[0059]

In order to achieve the above object, the invention according to claim 1 has a plurality of image processing circuit blocks (image processing units) for dividing and processing an image in a grid pattern. And

According to a second aspect of the present invention, in the first aspect of the invention, the image data included in the tile includes data attribute information such as a data type, a data processing destination, a data processing content, a data size, and a data position. It is characterized in that transmission is performed in units of added packets.

According to a third aspect of the present invention, in the second aspect of the invention, a packet (command packet) for reading or writing a register of the image processing circuit block (image processing unit) and image processing data (data packet). ) Are transmitted using the same bus.

According to a fourth aspect of the present invention, in the third aspect of the invention, the image processing unit can process both the command packet and the data packet.

According to a fifth aspect of the invention, in the fourth aspect of the invention, the image processing unit reads or writes a register when a command packet is input, and an image when a data packet is input. It is characterized by performing processing.

Therefore, according to the present invention, since the image data and the command for register setting are on the same bus, the order of the image data and command is not reversed, and the register setting is changed at any tile position. be able to.

[0065]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 7 is a block diagram of an image processing apparatus that best represents the present invention. In FIG. 7, 6010, 6012, 60
13, 6016 to 6020, 6022, and 6030 are command processing units built in each image processing unit.

A command packet or a data packet is input to the command processing section incorporated in each image processing unit.

FIG. 8 shows the extended command packet format of the present invention.
11 pieces of information are added.

The operation when the packets are input to the image processing unit 2149 in the order of the first data packet, the extended command packet, and the second data packet will be described. For explanation,
These three packets are all packets directed to the same resolution conversion unit 2116, and these three packets are the image ring interface 1 (2147) → image ring interface 3 (2101) → tile expansion unit 1 (2103) → tile. bus
2107 → command conversion unit 6016 → resolution conversion unit 2116 → tile bus 2107 → tile compression unit 3 (2106) → image ring interface 4 (2102) → image ring interface 2 (214
Communicate in the order of 8).

Hereinafter, description will be made in order.

The image ring interface 1 (2147) → image ring interface 3 (2101) is the same as the conventional example. Image ring interface 3 (2101) → Tile decompression unit 1 (2103) uses Packet Type ID 3
Based on the information of 004, the image ring interface 3
Although it is determined whether the packet is a data packet or a command packet, in the present invention, the Packet Type ID 3004 is used only in the command conversion unit, and it is determined to which block the packet should be passed next based on the information of Process Instruction 3011. In this way, the packet can be transmitted to the command conversion unit 6016.

In the command conversion unit 6016, Packet Type ID 3
Judge whether the packet is a command packet or a data packet based on 004. When a command packet is input, register setting or register reading of each image processing unit is performed. When a data packet is input,
The tile data is passed to each image processing unit, and each image processing unit outputs the data packet to the next image processing unit written in the Process Instruction of the data packet via the tile bus. After that, the operation is similar to that of the conventional example.

[0073]

As is apparent from the above description, according to the present invention, each image processing unit has the function of the command processing unit, so that the image data and the command for register setting use the same bus. By changing the register setting from the desired tile position, it is possible to perform the image processing suitable for the characteristics of the image.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing unit according to a conventional example of the present invention.

FIG. 2 is a configuration diagram of a network system according to a conventional example of the present invention.

FIG. 3 is a diagram for explaining a data packet according to a conventional example of the present invention.

FIG. 4 is a diagram for explaining a command packet according to a conventional example of the present invention.

FIG. 5 is a diagram for explaining a packet table according to a conventional example of the present invention.

FIG. 6 is a diagram for explaining a tile position in a page and image coordinates according to a conventional example of the present invention.

FIG. 7 is a block diagram of an image processing unit according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a command packet according to an embodiment of the present invention.

[Explanation of symbols]

2104 Command processing unit 2107 Tile bus 2108 Memory bus 2109 Register setting bus 6012, 6013, 6016 to 6020 Command processing unit 4011 built in each image processing unit 4011 Process Instruction 2116 Resolution conversion unit

Claims (5)

[Claims] 1. An image processing apparatus comprising a plurality of image processing circuit blocks (image processing units) for dividing an image into cells and processing the cells. 2. The image data included in a tile is transmitted in packet units in which attribute information of data such as a data type, a data processing destination, a data processing content, a data size, and a data position is added. The image processing apparatus according to item 1. 3. A packet (command packet) for reading or writing a register of the image processing circuit block (image processing unit) and image processing data (data packet) are transmitted using the same bus. The image processing apparatus according to claim 2. 4. The image processing apparatus according to claim 3, wherein the image processing unit can process both the command packet and the data packet. 5. The image processing unit according to claim 4, wherein the image processing unit reads or writes a register when a command packet is input and performs image processing when a data packet is input. Processing equipment.