JP2007220943A - Wiring circuit board having passive element built therein, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring circuit board having passive elements built therein which can be made compact in addition to the passive elements with a wide adaptive range, and to provide a method of easily and conveniently manufacturing such a wiring circuit board. <P>SOLUTION: The wiring circuit board having passive elements built therein comprises a silicon substrate, a first thin-film multilayer wiring layer formed on at least one of surfaces of the silicon substrate, a pattern electrode formed on the first thin-film multilayer wiring layer, a thin-film passive element film connected to the pattern electrode, and a second thin-film multilayer wiring layer formed so as to cover the above members. The first thin-film multilayer wiring layer and/or the second thin-film multilayer wiring layer contains a thin-film passive element film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board incorporating a passive element such as a capacitor, a resistor, and an inductor, and a manufacturing method for manufacturing such a wiring board.

  In recent years, in semiconductor chips, the operation speed has increased year by year as the density of integrated circuit elements such as ICs and LSIs has increased. When the operation speed of such an integrated circuit element increases, there is a problem that switching noise generated in the semiconductor chip causes a malfunction of the integrated circuit element. In order to reduce switching noise, it is effective to arrange a capacitor between the power supply bus line and the ground bus line.

When such passive elements such as capacitors and inductors are required, they are externally mounted on a multilayer wiring board as in the case of semiconductor chips. However, if the capacitor is arranged as an external component on the wiring board, the connection distance between the capacitor and the semiconductor chip becomes long and the wiring inductance becomes large, so that the effect of the capacitor becomes insufficient. For this reason, a passive element such as a capacitor is required to be as close to an integrated circuit element as possible, and is preferably formed directly on a semiconductor chip. However, in this case, the area of the semiconductor chip is increased and the cost is increased, and the manufacturing process is complicated and lengthy. Therefore, there is a problem in that the manufacturing yield of the semiconductor chip itself is lowered due to the defect of the capacitor.
In order to cope with these problems, it has been proposed to incorporate a passive element in a multilayer wiring layer laminated on a core substrate (Patent Document 1).
JP 2002-94247 A

However, since the passive element incorporated in the multilayer wiring layer shown in Patent Document 1 is a thin-film passive element, high accuracy can be achieved, but it can be used for applications requiring high withstand voltage and high resistance. In other words, there is a problem that all required electrical characteristics cannot be satisfied.
The present invention has been made in view of the above circumstances, and a passive element-embedded wiring board that can be downsized while incorporating passive elements with a wide range of application, and such a passive element-embedded wiring board are simplified. It aims at providing the manufacturing method for manufacturing to.

  In order to achieve such an object, a wiring board with a built-in passive element according to the present invention includes a silicon substrate, a first thin film multilayer wiring layer formed on at least one surface of the silicon substrate, and the first thin film. A pattern electrode formed on the multilayer wiring layer; a thick-film passive element film connected to the pattern electrode; and a second thin-film multilayer wiring layer formed so as to cover them. The thin film multilayer wiring layer and / or the second thin film multilayer wiring layer is configured to incorporate a thin film passive element film.

  The passive element built-in wiring board of the present invention is formed on a silicon substrate, a first thin film multilayer wiring layer formed on at least one surface of the silicon substrate, and the first thin film multilayer wiring layer. A pattern electrode, a thick film passive element film connected to the pattern electrode, and an overcoat layer formed so as to cover them, wherein the first thin film multilayer wiring layer includes a thin film passive element film The configuration is built-in.

As another aspect of the present invention, the second thin-film multilayer wiring layer is formed on the pattern electrode and the thick-film passive element film via a planarization layer, and the planarization layer is for front-back conduction. The structure has a via.
As another aspect of the present invention, the thick film passive element film is configured to constitute at least one of a capacitor, a resistor, and an inductor.
As another aspect of the present invention, the pattern electrode is a thick film conductive electrode.
As another aspect of the present invention, the thin film passive element film is configured to constitute at least one of a capacitor, a resistor, and an inductor.
As another aspect of the present invention, the silicon substrate is configured to include a plurality of through holes that are electrically connected to each other by a conductive material.

  The method for manufacturing a wiring board with a built-in passive element according to the present invention includes a step of forming a first thin film multilayer wiring layer on a silicon substrate, and a pattern electrode so as to be connected to a desired portion of the first thin film multilayer wiring layer. A step of forming, a step of forming a thick film passive element film by a low-temperature thermosetting process in which the curing temperature is in a range of 100 to 200 ° C. so as to be connected to a desired portion of the pattern electrode, and a desired portion of the pattern electrode, Forming a second thin film multilayer wiring layer so as to be connected, and at least one of the step of forming the first thin film multilayer wiring layer and the step of forming the second thin film multilayer wiring layer, The thin film passive element film is formed by a thin film process.

  The method for manufacturing a wiring board with a built-in passive element according to the present invention includes a step of forming a first thin film multilayer wiring layer on a silicon substrate and a pattern so as to be connected to a desired portion of the first thin film multilayer wiring layer. A step of forming an electrode, a step of forming a thick film passive element film by a low-temperature thermosetting process having a curing temperature in the range of 100 to 200 ° C. so as to connect to a desired portion of the pattern electrode, the pattern electrode, and the pattern electrode Forming an overcoat layer so as to cover the thick film passive element film, and forming the thin film passive element film by a thin film process in the step of forming the first thin film multilayer wiring layer. It was.

As another aspect of the present invention, a planarization layer is formed after the thick film passive element film is formed, and the second thin film multilayer wiring layer is formed on the planarization layer.
As another embodiment of the present invention, the pattern electrode is formed by printing, drying, and thermosetting using a low-temperature thermosetting thick film conductor paste having a curing temperature in the range of 100 to 250 ° C. did.
As another aspect of the present invention, the thin film multilayer wiring layer is formed by any one of a sputtering / semi-additive method, a sputtering / full additive method and a sputtering / full-surface plating / subtractive method.

Since the passive element built-in wiring board of the present invention has a built-in passive element having a thick film passive element film, it can be used for applications requiring high withstand voltage and high resistance, and a thin film multilayer wiring. Since the layer is equipped with a thin film passive element film, it is possible to meet the requirements for high accuracy, low power consumption, low resistance, and low capacitance of resistors, capacitors, and inductors, satisfying all required electrical characteristics, Further, since the thick film passive element film has good moisture resistance, it has high reliability and can be miniaturized.
In addition, the method of manufacturing a wiring board with a built-in passive element according to the present invention forms a thick film passive element film by a thick film high-temperature baking process, and forms a thin film passive element film by a thin film process. It is possible to manufacture a wiring board that incorporates passive elements that require high resistance and passive elements that require high precision of resistance, capacitance, and inductor, low power consumption, low resistance, and low capacitance. Thus, it is possible to easily cope with changes in the position and size of the passive element.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Passive element built-in wiring board]
FIG. 1 is a partial longitudinal sectional view showing an embodiment of a wiring board with a built-in passive element of the present invention. In FIG. 1, a passive element built-in wiring substrate 1 according to the present invention is formed on a silicon substrate 2, a first thin film multilayer wiring layer 10 formed on one surface of the core substrate 2, and a thin film multilayer wiring layer. The patterned electrode 21, the thick film passive element film 22 connected to the pattern electrode 21, and the second thin film multilayer wiring layer 30 formed thereon via the planarization layer 25 are provided.
The silicon substrate 2 constituting the passive element built-in wiring substrate 1 is formed with a plurality of through holes 4, and an insulating layer 3 is formed on the entire surface including the inner wall surface of the through holes 4. Each through hole 4 is provided with a conductive material 5.

The through hole 4 formed in the silicon substrate 2 may have an inner diameter in the range of 10 to 300 μm, and may have a straight shape with an inner diameter substantially constant in the thickness direction of the silicon substrate 2 as illustrated. Alternatively, a tapered shape having one wide opening diameter, a shape in which the inner diameter is narrow at the approximate center in the thickness direction of the silicon substrate 2, or the like may be used. The silicon substrate 2 can have a thickness in the range of 20 to 600 μm, preferably 50 to 250 μm. If the thickness of the silicon substrate 2 is less than 20 μm, sufficient strength cannot be maintained as a support, and if it exceeds 600 μm, the semiconductor device is undesirably thinned.
The material of the insulating layer 3 formed on the silicon substrate 2 can be an electrical insulating film such as silicon dioxide or silicon nitride.

The conductive material 5 constituting the silicon substrate 2 is, for example, a metal material such as copper, silver, gold, tungsten, or tantalum, a known conductive paste containing conductive particles such as copper particles or silver particles, or tin- The solder may be zinc, tin-silver, tin-bismuth, tin-lead, or the like. Moreover, these can also be used in combination.
The first thin-film multilayer wiring layer 10 constituting the passive element built-in wiring substrate 1 includes the first to third electric insulating layers 11a, 11b, and 11c, and the first layer formed on each electric insulating layer. Third-layer wirings 12a, 12b, and 12c are provided.

  An opening 13a is formed in the first electrical insulating layer 11a so that a desired portion of the conductive material 5 is exposed, and a via 14a is disposed in the opening 13a. Therefore, a desired portion of the first-layer wiring 12a is electrically connected to the conductive material 5 in the through hole 4 as the through electrode via the via 14a. An electrode 16 is formed on the wiring 12a. In the illustrated example, the electrode 16 includes electrodes 16a, 16b, and 16c. Among these, a thin film passive element film 17a is formed between the electrodes 16a and 16b to constitute a passive element 18 as a resistor. A thin film passive element film 17b is formed on the electrode (lower electrode) 16c, and further an electrode (upper electrode) 16d is formed thereon, thereby forming a passive element 19 as a capacitor. Yes.

A desired portion of the second-layer wiring 12b is vertically connected to the first-layer wiring 12a and the electrode 16 via a via 14b disposed in the opening 13b of the second-layer electrical insulating layer 11b. Has been made.
Further, a desired portion of the third-layer wiring 12c is vertically connected to the second-layer wiring 12b through a via 14c disposed in the opening 13c of the third-layer electrical insulating layer 11c. Yes.
The material of the thin film passive element film 17a can be, for example, titanium, chromium, etc., and the thickness can be, for example, about 0.01 to 1 μm, preferably about 0.05 to 0.2 μm. The material of the thin film passive element film 17b can be, for example, barium titanate (BaTiO ₃ ), titanium oxide (TiO ₅ ), etc., and the thickness is, for example, 0.01 to 1 μm, preferably 0.05. It can be set to about ˜0.2 μm.
When forming a passive element as an inductor by forming a thin film passive element film, for example, a conductive material such as copper, silver, gold, silver / palladium can be used as the thin film passive element film.

The material of the electrical insulating layers 11a, 11b, and 11c constituting the first thin film multilayer wiring layer 10 is, for example, an organic insulating material such as epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, fluorene, or the like. An insulating material such as a combination of a material and glass fiber can be used. Moreover, the material of wiring 12a, 12b, 12c, electrode 16a, 16b, 16c, 16d, and the material of via | veer 14a, 14b, 14c located in opening part 13a, 13b, 13c are copper, silver, gold | metal | money, aluminum, for example Or a conductive material such as
On the first thin-film multilayer wiring layer 10 as described above, the pattern electrode 21 is formed in a desired pattern so as to be connected to the third-layer wiring 12c. The pattern electrode 21 includes electrodes 21a, 21b, and 21c in the illustrated example. Among these, the electrodes 21a and 21b constitute a passive element 23 as a resistor. The electrode 21c is a lower electrode constituting the passive element 24 as a capacitor. The material of the pattern electrode 21 can be a conductive material such as copper, silver, gold, silver / palladium, for example. The thickness of the pattern electrode 21 is, for example, about 1 to 10 μm, preferably about 3 to 7 μm, and can be a thick film conductive electrode. The pattern electrode 21 may be made of the same material as the wiring 12c. Of course, the pattern electrode 21 may include desired wiring in addition to the electrodes 21a, 21b, and 21c.

The thick film passive element film 22 connected to the pattern electrode 21 includes thick film passive element films 222a and 22b in the illustrated example. Among these, the thick film passive element film 22a is formed between the electrodes 21a and 21b and constitutes the passive element 23 as a resistor. The material of the thick film passive element film 22a can be, for example, tin oxide (SnO ₂ ), lanthanum bolite (LaB ₆ ), ruthenium oxide (RuO ₂ ), etc., and the thickness is, for example, 1 to 10 μm, Preferably, it can be about 3 to 7 μm.

Further, the thick film passive element film 22b is formed on the electrode (lower electrode) 21c, and further an electrode (upper electrode) 21d is formed thereon, whereby the passive element 24 as a capacitor is formed. It is configured. The material of the thick film passive element film 22b can be, for example, barium titanate (BaTiO ₃ ), and the thickness can be, for example, about 1 to 10 μm, preferably about 3 to 7 μm. The material of the electrode 21d constituting the passive element 24 may be the same as that of the electrodes 21a, 21b, and 21c, and the thickness is, for example, about 1 to 10 μm, preferably about 3 to 7 μm. can do.
In the case of configuring a passive element as an inductor, for example, a conductive material such as copper, silver, gold, silver / palladium can be used as the thick film passive element film.

The planarization layer 25 covers and planarizes the pattern electrode 21 (21a, 21b, 21c), the electrode 21d, and the thick film passive element films 22a, 22b. The planarization layer 25 has an opening 25a located at a desired portion of the pattern electrode 21 and the electrode 21d, and a via 26 is formed in the opening 25a. A wiring 27 is provided on the planarizing layer 25, and a desired part of the wiring 27 is connected to the via 26. The planarization layer 25 is made of an insulating material such as glass, and has a thickness of, for example, 1 to 15 μm, preferably about 3 to 12 μm. The material of the via 26 and the wiring 27 can be a conductive material such as copper, silver, gold, or aluminum.
In the illustrated example, the second thin-film multilayer wiring layer 30 includes first to second electric insulating layers 31a and 31b formed on the planarizing layer 25, and one layer formed on each electric insulating layer. First to second layer wirings 32a and 32b are provided.

An opening 33a is formed in the first electrical insulating layer 31a so as to be located at a desired portion of the wiring 27, and a via 34a is disposed in the opening 33a. Therefore, a desired portion of the first layer wiring 32a is vertically connected to the wiring 27 on the planarization layer 25 through the via 34a.
Similarly, a desired portion of the second-layer wiring 32b is vertically connected to the first-layer wiring 32a through a via 34b disposed in the opening 33b of the second-layer electrical insulating layer 31b. ing.
The material of the electrical insulating layers 21a and 21b constituting the thin film multilayer wiring layer 30 as described above can be the same insulating material as that of the electrical insulating layers 11a, 11b, and 11c. The material of the wirings 32a and 32b and the material of the vias 34a and 34b located in the openings 33a and 33b can be conductive materials such as copper, silver, gold, and aluminum.

  In the passive element built-in wiring board 1 of the present invention as described above, the first thin film multilayer wiring layer 10 includes the passive elements 18 and 19 including the thin film passive element films 17a and 17b, and the thin film multilayer wiring layer. Since the passive elements 23 and 24 including the thick film passive element films 22a and 22b are built in the upper layer of the tenth layer, the resistance, the capacity and the inductor have high accuracy, low power consumption, low resistance and low capacity. In addition, it can be used for applications requiring high withstand voltage and high resistance. Further, since the thick film passive element films 22a and 22b have high moisture resistance, the reliability is high and the passive element built-in wiring board 1 can be miniaturized.

  The passive element built-in wiring board of the present invention may include an overcoat layer as shown in FIG. 2 instead of the second thin film multilayer wiring layer 30. In FIG. 2, a passive element built-in wiring substrate 1 ′ of the present invention includes a silicon substrate 2, a first thin film multilayer wiring layer 10 formed on one surface of the core substrate 2, and the thin film multilayer wiring layer. A pattern electrode 21 formed, a thick film passive element film 22 connected to the pattern electrode 21, and an overcoat layer 41 formed thereon are provided.

This passive element built-in wiring board 1 ′ is the same as the above-described passive element built-in wiring board 1 except that an overcoat layer 41 is provided instead of the second thin film multilayer wiring layer 30, and the same members are the same members. A number is attached and explanation is omitted.
The overcoat layer 41 may be an insulating material such as an organic insulating material such as epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, fluorene, or a combination of these organic materials and glass fiber. it can.

The passive element built-in wiring board of the present invention may also include a thin film passive element film in the second thin film multilayer wiring layer. FIG. 3 is a partial longitudinal sectional view showing a wiring board with a built-in passive element having such a configuration.
In FIG. 3, a passive element built-in wiring substrate 1 ″ according to the present invention includes a silicon substrate 2, a first thin film multilayer wiring layer 10 formed on one surface of the core substrate 2, and a thin film multilayer wiring layer. The formed pattern electrode 21, the thick film passive element film 22 connected to the pattern electrode 21, and the second thin film multilayer wiring layer 50 formed thereon via the planarization layer 25 are provided. This passive element built-in wiring board 1 ″ is the same as the above-described passive element built-in wiring board 1 except that the second thin film multilayer wiring layer 50 is provided with a thin film passive element film. The description is omitted. Therefore, the second thin film multilayer wiring layer 50 will be described below.

The second thin-film multilayer wiring layer 50 constituting the passive element built-in wiring board 1 ″ includes first to second electric insulating layers 51a and 51b formed on the planarizing layer 25, and each electric insulating layer. The first to second layer wirings 52a and 52b are formed.
An opening 53a is formed in the first electrical insulating layer 51a so as to be located at a desired portion of the wiring 27, and a via 54a is disposed in the opening 53a. Therefore, a desired portion of the first layer wiring 52a is vertically connected to the wiring 27 on the planarization layer 25 through the via 54a. An electrode 56 is formed on the wiring 52a. In the illustrated example, the electrode 56 includes electrodes 56a, 56b, and 56c. Among these, a thin film passive element film 57a is formed between the electrodes 56a and 56b to constitute a passive element 58 as a resistor. Further, a thin-film passive element film 57b is formed on the electrode (lower electrode) 56c, and further, an electrode (upper electrode) 56d is formed thereon, thereby forming a passive element 59 as a capacitor. Yes.

A desired portion of the second-layer wiring 52b is vertically connected to the first-layer wiring 52a and the electrode 56 through a via 54b disposed in the opening 53b of the second-layer electrical insulating layer 51b. Has been made.
The material of the thin film passive element film 57a can be, for example, titanium, chromium, etc., and the thickness can be, for example, about 0.01 to 1 μm, preferably about 0.05 to 0.2 μm. The material of the thin film passive element film 57b can be, for example, barium titanate (BaTiO ₃ ), titanium oxide (TiO ₅ ), etc., and the thickness is, for example, 0.01-1 μm, preferably 0.05. It can be set to about 0.2 μm.
When forming a passive element as an inductor by forming a thin film passive element film, for example, a conductive material such as copper, silver, gold, silver / palladium can be used as the thin film passive element film.

  The materials of the electrical insulating layers 51a and 51b constituting the second thin film multilayer wiring layer 50 as described above are, for example, organic insulating materials such as epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, fluorene, and the like. An insulating material such as a combination of the organic material and glass fiber can be used. The material of the wirings 52a and 52b, the electrodes 56a, 56b, 56c and 56d and the material of the vias 54a and 54b located in the openings 53a and 53b are, for example, conductive materials such as copper, silver, gold and aluminum. be able to.

The above-described passive element built-in wiring board 1 ″ of the present invention incorporates the passive elements 18 and 19 including the thin film passive element films 17a and 17b in the first thin film multilayer wiring layer 10, and the thin film multilayer wiring. In the upper layer of the layer 10, the passive elements 23 and 24 including the thick film passive element films 22a and 22b are incorporated, and the passive element 58 including the thin film passive element films 57a and 57b in the second thin film multilayer wiring layer 50 is provided. , 59 built-in, high accuracy of resistors, capacitors and inductors, low power consumption, low resistance, and low capacitance are possible, and applications requiring high withstand voltage and high resistance are required. In addition, since the thick passive element films 22a and 22b have high moisture resistance, the reliability is high and the passive element built-in wiring board 1 ″ can be miniaturized.
The above-mentioned passive element built-in wiring board is an example, and the present invention is not limited to these embodiments. For example, the first thin film multilayer wiring layer may not include the thin film passive element film, and the second thin film multilayer wiring layer may include the thin film passive element film. Further, the silicon substrate 2 may not include the through-hole 4, and the second thin film multilayer wiring layers 30 and 50 may be formed without the planarization layer 25 interposed. . Furthermore, the number of layers of the first thin film multilayer wiring layer and the second thin film multilayer wiring layer is not limited to the illustrated example.

[Method for manufacturing wiring board with built-in passive element]
Next, a method for manufacturing a wiring board with a built-in passive element according to the present invention will be described with reference to the drawings.
4 to 6 are process diagrams showing an embodiment of a method for manufacturing a wiring board with a built-in passive element according to the present invention, taking the wiring board with a built-in passive element 1 shown in FIG. 1 as an example.
In the method for manufacturing a wiring board with a built-in passive element of the present invention, first, a through hole 4 is formed in the silicon substrate 2, an insulating layer 3 is formed on the surface of the silicon substrate 2 including the inner wall of the through hole 4, and then the through hole 4 The inside is filled with a conductive material 5 to form a through electrode (FIG. 4A).
The through hole 4 is formed in the silicon substrate 2 by, for example, forming a predetermined mask pattern on one surface of the silicon substrate 2, and using this mask pattern as a mask, sandblasting, or ICP-RIE (Inductively Coupled Plasma-Reactive Ion). Etching can be performed by dry etching using an inductively coupled plasma-reactive ion etching method. The opening diameter of the through hole 4 can be appropriately set within a range of 10 to 300 μm, for example, and can be adjusted by the opening diameter of the mask pattern.

  The insulating layer 3 can be formed as an insulating film such as a silicon dioxide film or silicon nitride by using a vacuum film forming method such as a plasma CVD method. Further, a silicon oxide suspension or an insulating resin such as a benzocyclobutene resin, a cardo resin, or a polyimide resin may be applied to the core material surface by a coating method and thermally cured. Furthermore, a silicon dioxide film can be formed on the surface to form the insulating layer 3 by thermal oxidation of the silicon substrate 2. When the mask pattern used for forming the through hole 4 is an electrically insulating film such as silicon nitride, the mask pattern is used without removing the mask pattern to constitute the insulating layer 3, The insulating layer 3 may be formed on the surface of the silicon substrate 2 and the inner wall surface of the through hole 4.

  The through hole 4 is filled with the conductive material 5 by, for example, forming a base conductive thin film on the silicon substrate 2 (insulating layer 3) on which the through hole 4 is formed, and then through the base conductive thin film 4 as a power feeding layer. The hole 4 can be formed by embedding a conductive material such as copper, silver, gold, or nickel by electrolytic plating. The base conductive thin film can be formed by electroless plating as a thin film of chromium, titanium, titanium nitride, nickel, vanadium, or a thin film containing these (for example, a thin film made of copper and chromium). Further, the underlying conductive thin film may be formed by a vacuum film forming method such as a sputtering method or a vapor deposition method. The filling of the conductive material 5 into the through hole 4 can also be performed by filling a conductive paste such as a silver paste or a copper paste into the through hole 4 by screen printing or the like and baking it.

  Next, the first electrical insulating layer 11 a, the opening 13 a, the via 14 a, and the wiring 12 a constituting the first thin film multilayer wiring layer 10 are formed on the silicon substrate 2. In the formation of the wiring 12a, the electrodes 16a, 16b, and 16c are formed at the same time (FIG. 4B). The thin film multilayer wiring layer can be formed by any of the so-called sputter / semi-additive method, sputter / full additive method and sputter / full plating / subtractive method such as copper / polyimide, copper / benzocyclobutene, copper / fluorene, etc. Can be performed. Specifically, a conductive layer is formed on the electrical insulating layer 11a including the inside of the opening 13a by a vacuum film formation method such as a sputtering method, a mask pattern is formed on the conductive layer, and the conductive layer is etched. Then, the via 14a, the wiring 12a, and the electrodes 16a, 16b, and 16c are formed, and then the mask pattern is removed.

Further, for example, an electrical insulating layer 11a is formed on the silicon substrate 2, and a small-diameter opening is formed so that a desired portion of the conductive material 5 is exposed by wet etching, carbon dioxide laser, UV-YAG laser, or the like. 13a is formed at a predetermined position of the electrical insulating layer 11a. Then, after cleaning, a conductive layer is formed in the opening 13a and on the electrical insulating layer 11a by electroless plating, a dry film resist is laminated on the conductive layer, and a desired pattern exposure and development are performed to perform an insulating pattern. Form. Thereafter, using this insulating pattern as a mask, a conductive material is deposited on the exposed portion including the opening 13a by electrolytic plating to form the via 14a, the wiring 12a, and the electrodes 16a, 16b, and 16c, and the insulating pattern and the conductive layer are formed. Remove.
Next, a thin film passive element film 17 (17a, 17b) is formed at a desired portion of the electrodes 16a, 16b, 16c, and on the thin film passive element film 17b for constituting the capacitor 19 out of the thin film passive element films 17a, 17b. The electrode 16d is formed (FIG. 4C).

The thin film passive element film 17a constituting the passive element 18 as a resistor is formed by, for example, laminating a dry film resist and performing desired pattern exposure and development to form an insulating pattern, and using this insulating pattern as a mask, sputtering or the like The film can be formed by depositing a thin film of titanium, chromium or the like. Further, a seed layer such as titanium or chromium is formed as a conductive layer for forming the wiring 12a and the electrodes 16a, 16b, and 16c, and the seed layer is left in a desired pattern to form the thin film passive element film 17a. Good.
The thin film passive element film 17b constituting the capacitor 19 is formed by, for example, laminating a dry film resist and performing desired pattern exposure and development to form an insulating pattern, and using this insulating pattern as a mask, titanium is formed by sputtering or the like. It can be formed by depositing barium acid (BaTiO ₃ ) or by depositing titanium oxide (TiO ₅ ) by an anodic oxidation method. In the case of a thin film passive element film for forming a passive element as an inductor, for example, a conductor paste such as copper, silver, gold, silver / palladium is printed in a desired pattern, and then dried and fired. It can be formed by a thin film process.
The electrode 16d can be formed by thin film formation such as sputtering or vapor deposition, or plating.

Next, except that the electrodes 16a, 16b, 16c, 16d and the thin film passive element film 17 are not formed, the same steps as the formation of the first electric insulating layer 11a, the opening 13a, the via 14a, and the wiring 12a are performed. A third electrical insulating layer 11b, opening 13b, via 14b, and wiring 12b are formed, and a third electrical insulating layer 11c, opening 13c, via 14c, and wiring 12c are formed.
Thus, the first thin-film multilayer wiring layer 10 incorporating the thin-film passive element film 17 is formed (FIG. 4D). On the first thin-film multilayer wiring layer 10 thus formed, a pattern electrode 21 is formed in a desired pattern so as to be connected to the third-layer wiring 12c. The pattern electrode 21 includes electrodes 21a, 21b, and 21c in the illustrated example. Among these, the electrodes 21a and 21b constitute a passive element 23 as a resistor. The electrode 21c is a lower electrode constituting the passive element 24 as a capacitor.

  The pattern electrode 21 can be formed simultaneously with the third-layer wiring 12c. The pattern electrode 21 is formed of a low temperature curing type thick film conductor paste having a curing temperature in the range of 100 to 250 ° C., for example, a thick film conductor paste containing silver or the like, and metal fine particles such as silver, gold, and nickel. A so-called MO (metal organic) paste kneaded, dispersed, and aged with a binder or the like is printed in a desired pattern, and then dried and thermally cured at a temperature lower than the heat resistance temperature of the first thin-film multilayer wiring layer 10. Can be done. The thickness of the pattern electrode 21 to be formed can be, for example, about 0.1 to 1 μm.

Next, the thick-film passive element film 22 (22a, 22b) is formed by a low-temperature thermosetting process in which the curing temperature is in the range of 100 to 200 ° C. so as to connect to the desired part of the pattern electrode 21 (FIG. 5A). ). In the case of the thick film passive element film 22a for constituting the passive element 23 as a resistor, for example, the thick film passive element film 22 has a curing temperature of 100 to 200 ° C. containing carbon phenol or the like. It can be formed by printing a low-temperature curing type thick film paste in a desired pattern, followed by drying and heat curing. In the case of the thick film passive element film 22b for constituting the capacitor 24, for example, a low temperature curing type thick film paste containing barium titanate (BaTiO ₃ ) or the like and having a curing temperature in the range of 100 to 200 ° C. Can be formed by printing in a desired pattern, followed by drying and thermosetting. In the case of a thick film passive element film for constituting a passive element as an inductor, for example, the above thick film conductive paste is printed in a desired pattern, and then dried and thermally cured. Can do.

Next, of the thick film passive element films 22a and 22b, which are the thick film passive element films 22, the electrode 21d is formed on the thick film passive element film 22b for forming the capacitor 24 (FIG. 5B). . The electrode 21d is formed by, for example, printing a low-temperature curable thick film conductor paste having a curing temperature in the range of 100 to 200 ° C. in a desired pattern, followed by drying and thermosetting. Can do.
Next, the planarization layer 25, the opening 25a, the via 26, and the wiring 27 are formed (FIG. 6A). Formation of the planarization layer 25 is, for example, an organic resin such as epoxy, polyimide, PPE (polyphenylene ether), PPS (polyphenylene sulfide), BT (bismaleimide doriadine), BCB (benzocyclobutene), or LCP (liquid crystal polymer). Can be performed by pattern printing, drying and curing. Alternatively, the planarizing layer 25 may be formed by printing the entire surface of a photosensitive organic resin using the above organic resin, exposing, developing, and curing.

The opening 25a may be formed simultaneously with the above pattern printing or exposure, or may be formed using, for example, wet etching, carbon dioxide laser, UV-YAG laser, or the like.
The via 26 and the wiring 27 are formed by, for example, first forming a conductive layer in the opening 25a and on the planarizing layer 25 by electroless plating, and laminating a dry film resist on the conductive layer to obtain a desired layer. An insulating pattern is formed by performing pattern exposure and development. Next, using this insulating pattern as a mask, a conductive material is deposited on the exposed portion including the opening 25a by electrolytic plating to form a via 26 and a wiring 27, and then the insulating pattern and the conductive layer are removed. Further, a conductive layer is formed in the opening 25a and on the planarizing layer 25 by a vacuum film formation method such as a sputtering method, a mask pattern is formed on the conductive layer, the conductive layer is etched, and the via 26 is formed. And the wiring 27 may be formed, and then the mask pattern may be removed.

  Next, the second thin film multilayer wiring layer 30 is formed to obtain the passive element built-in wiring board 1 (FIG. 6B). The second thin-film multilayer wiring layer is formed by, for example, a so-called sputtering / semi-additive method, sputtering / full-additive method and sputtering / full-surface plating / subtractive method such as copper / polyimide, copper / benzocyclobutene, and copper / fluorene. It can be done by either. Specifically, a conductive layer is formed on the electrical insulating layer 31a including the opening 33a by a vacuum film formation method such as a sputtering method, a mask pattern is formed on the conductive layer, and the conductive layer is etched to form vias. 34a and wiring 32a are formed, and then the mask pattern is removed. By repeating this operation, vias 34b and wirings 32b can also be formed through the electrical insulating layer 32b to form the second thin film multilayer wiring layer 30.

  Further, for example, an electrical insulating layer 31a is formed so as to cover the planarizing layer 25 and the wiring 27, and a desired portion of the wiring 27 is exposed by wet etching, carbon dioxide gas laser, UV-YAG laser or the like. A small-diameter opening 33a is formed at a predetermined position of the electrical insulating layer 31a. Then, after washing, a conductive layer is formed in the opening 33a and on the electrical insulating layer 31a by electroless plating, and a dry film resist is laminated on the conductive layer, and a desired pattern exposure and development are performed to perform an insulating pattern. Form. Then, using this insulating pattern as a mask, a conductive material is deposited on the exposed portion including the opening 33a by electrolytic plating to form a via 34a and a wiring 32a, and the insulating pattern and the conductive layer are removed. By repeating this operation, vias 34b and wirings 32b can also be formed through the electrical insulating layer 32b to form the second thin film multilayer wiring layer 30.

In the production of the passive element built-in wiring substrate 1 ′ shown in FIG. 2, the formation of the silicon substrate 2, the first thin film multilayer wiring layer 10, the passive elements 23 and 24, the planarization layer 25, and the wiring 27 is built in. An overcoat layer 41 is formed instead of forming the second thin-film multilayer wiring layer in the same manner as the manufacturing method of the wiring substrate 1.
The overcoat layer 41 includes, for example, an insulating material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, a polyimide resin, an organic insulating material such as fluorene, or a combination of these organic materials and glass fiber. The film paste can be printed, then dried, and formed by low-temperature thermosetting at a temperature lower than the heat resistant temperature of the first thin-film multilayer wiring layer 10. The thickness of the overcoat layer 41 to be formed can be, for example, about 1 to 10 μm.

In the production of the passive element built-in wiring substrate 1 ″ shown in FIG. 3, the formation of the silicon substrate 2, the first thin-film multilayer wiring layer 10, the passive elements 23 and 24, the planarization layer 25, and the wiring 27 is passively performed. It is assumed that the second thin film multilayer wiring layer is formed in the same manner as the manufacturing method of the element built-in wiring substrate 1 and the thin film passive element film is built in the same manner as the first thin film multilayer wiring layer 10 is formed.
In the manufacturing method of the present invention described above, a thick film passive element film is formed by a thick film high-temperature firing process, and a thin film passive element film is formed by a thin film process. Therefore, excellent moisture resistance, high withstand voltage, and high resistance value are required. It is possible to manufacture a wiring board incorporating a passive element and a passive element that requires high precision, low power consumption, low resistance, and low capacitance of a resistor, a capacitor, and an inductor. In addition, it is possible to easily cope with changes in the position and size of the passive elements.
The above-described method for manufacturing a wiring board with a built-in passive element is an example, and the present invention is not limited to these embodiments.

Next, the present invention will be described in more detail with specific examples.
(Production of silicon substrate)
A silicon wafer having a thickness of 300 μm was prepared, and a silicon nitride film (thickness 2 μm) was formed on one surface of the silicon wafer by plasma CVD. Next, a positive type photoresist (OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied onto the silicon nitride film, and exposed and developed through a photomask for forming a through hole, thereby forming a resist pattern. . Next, the silicon nitride exposed from the resist pattern was dry-etched using CF ₄ as an etching gas, and then the resist was removed to form a mask pattern made of silicon nitride. This mask pattern had circular openings with a diameter of 30 μm at a pitch of 150 to 500 μm.

Next, a silicon wafer was etched using the silicon nitride film as a mask by an ICP-RIE apparatus, and CF ₆ was used as an etching gas to form a through hole. This through hole had an opening diameter of about 22 μm.
Next, the mask pattern was removed from the core material using acetone. Thereafter, the core material on which the through hole was formed was subjected to thermal oxidation treatment (1050 ° C., 20 minutes) to form an insulating film made of silicon dioxide on the surface of the core material (including the inner wall surface of the through hole). Thereafter, a base conductive thin film having a thickness of 0.2 μm was formed on one surface of the core material and the inner wall surface of the through hole by sputtering in the order of titanium-copper. Next, a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on the underlying conductive thin film. Next, exposure and development were performed through a photomask to form a resist pattern. Electrolytic copper plating was performed using this resist pattern as a mask and the above-mentioned underlying conductive thin film as a power feeding layer. Thereby, the inside of the through hole was filled with electrolytic copper plating.

  Next, the conductive material protruding on both surfaces of the core material was polished using MCP150X manufactured by Fujikoshi Machine Industry Co., Ltd., and then the resist pattern and the underlying conductive thin film were removed to obtain a silicon substrate. This silicon substrate was electrically connected to the front and back by a conductive material filled in the through hole.

(Formation of first thin-film multilayer wiring layer)
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied to one surface of the silicon substrate with a spin coater and dried to form an electrical insulating layer having a thickness of 7 μm. Next, exposure and development were performed to form a small-diameter opening (inner diameter 25 μm) at a predetermined position of the electrical insulating layer so that a predetermined portion of the conductive material positioned in the through hole was exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the opening and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, exposure and development were performed through a photomask for electrode / wiring formation to form an insulating pattern for electrode / wiring formation. Electrolytic copper plating (thickness: 4 μm) was performed using this insulating pattern as a mask to form electrodes and wiring. The formed electrodes were an electrode for constituting a passive element as a resistor and a lower electrode (100 μm × 100 μm square) for constituting a passive element as a capacitor.

Next, the insulating pattern is removed, a negative photoresist (THB manufactured by JSR Co., Ltd.) is applied on the exposed conductive layer, and exposed through a photomask for forming a thin film passive element film as a resistive element film. A resist pattern was formed by development. Next, an unnecessary conductive layer was removed by etching using an aqueous permanganate solution to form a thin film passive element film (resistance element film) made of chromium and copper located between the electrodes.
Next, a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on the electrical insulating layer so as to cover the thin film passive element film (resistive element film). Next, exposure and development were performed through a photomask to form a resist pattern. Using this resist pattern as a mask, a thin film of barium titanate was formed by sputtering. As a result, a thin film passive element film (a square having a thickness of 0.2 μm and 100 μm × 100 μm) as a capacitive element film was formed on the lower electrode. Next, using the resist pattern as a mask, a copper thin film was formed on the thin film passive element film, which is a capacitive element film, by sputtering to form an upper electrode (square of thickness 0.2 μm, 100 μm × 100 μm).
Thus, the first thin film wiring layer containing the passive element was formed.

  Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied on the first thin film wiring layer by a spin coater and dried to form an electrical insulating layer having a thickness of 7 μm. Next, exposure and development were performed to form a small-diameter opening (inner diameter 25 μm) at a predetermined position of the electrical insulating layer so that a predetermined portion of the electrode and wiring of the first thin film wiring layer was exposed. After that, except that the electrode and the thin film passive element film are not formed, the same operation as the thin film wiring layer containing the thin film passive element film is performed, and the wiring is formed through the second electric insulating layer. did. Similarly, a wiring was formed through a third electrical insulating layer. As a result, a thin film multilayer wiring layer having a three-layer structure was formed.

(Formation of pattern electrode)
Next, after a thick film conductor paste containing silver particles (TC-3600 manufactured by Hitachi Chemical Co., Ltd.) is printed on the first thin film multilayer wiring layer by screen printing and dried (150 ° C., 60 minutes). And thermosetting (250 ° C., 60 minutes). Thereby, a pattern electrode (thickness 5 μm) was formed on the first thin film multilayer wiring layer. The formed pattern electrode was an electrode for constituting a passive element as a resistor and a lower electrode (100 μm × 100 μm square) for constituting a passive element as a capacitor.

(Formation of thick film passive element film)
Next, a thick film paste containing carbon phenol particles (YR-100, manufactured by Kobayashi Co., Ltd.) is printed by screen printing on a desired portion on the first thin-film multilayer wiring layer on which the pattern electrode is formed, and dried (150 (C, 30 minutes). Next, a thick film paste (print capacitor made by Yokohama Resistor Co., Ltd.) containing barium titanate particles was printed by screen printing and dried (150 ° C., 30 minutes). Then, thermosetting (300 degreeC, 60 minutes) was performed. As a result, a thick passive element film (thickness 1 μm) as a resistive element film was formed between desired electrodes, and a thick passive element film (thickness 1 μm) as a capacitive element film was formed on the lower electrode. Next, a thick film conductive paste containing silver particles (TC-3600, manufactured by Hitachi Chemical Co., Ltd.) is printed on the thick film passive element film, which is a capacitive element film, by screen printing and dried (150 ° C., 30 minutes) Then, thermosetting (250 ° C., 60 minutes) was performed. Thereby, an upper electrode (5 μm thick, 100 μm × 100 μm square) was formed.

(Formation of planarization layer)
Next, after the polyimide resin composition (HL-P manufactured by Hitachi Chemical Co., Ltd.) is printed by screen printing so as to cover the above thick film passive element film and electrode, it is dried (150 ° C., 30 minutes). And thermosetting (300 ° C., 60 minutes). This formed the planarization layer (thickness 10 micrometers).
Next, an opening was formed in a desired portion of the planarization layer using a carbon dioxide laser. In these openings, the electrodes constituting the passive element made of the above thick film passive element film were exposed. Next, a base conductive thin film having a thickness of 0.2 [mu] m was formed by sputtering in the order of titanium-copper in the opening and on the planarizing layer. Next, a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on the underlying conductive thin film. Next, exposure and development were performed through a photomask to form a resist pattern. Electrolytic copper plating was performed using this resist pattern as a mask and the above-mentioned underlying conductive thin film as a power feeding layer. Thus, a conductive material was deposited on the exposed portion including the opening by electrolytic plating to form a via and a wiring, and then the resist pattern and the underlying conductive thin film were removed.

(Formation of second thin-film multilayer wiring layer)
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied by a spin coater so as to cover the planarization layer on which vias and wirings are formed as described above, and is electrically insulated with a thickness of 7 μm. A layer was formed. Next, exposure and development were performed to form a small-diameter opening (inner diameter 25 μm) at a predetermined position of the electrical insulating layer so that a predetermined portion of the wiring on the planarization layer was exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the opening and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, an insulating pattern for wiring formation was formed by exposure and development through a photomask for wiring formation. Using this insulating pattern as a mask, electrolytic copper plating (thickness: 4 μm) was performed, and then the unnecessary insulating pattern and conductive layer were removed. Thereby, wiring was formed via the electrical insulating layer. The above wiring was connected to the wiring on the planarization layer by a via (diameter 25 μm).

Further, the same operation was performed to form a wiring through the second electrical insulating layer. Thereby, a thin film multilayer wiring layer having a two-layer structure was formed.
Thus, a passive element built-in wiring board of the present invention as shown in FIG. 1 was obtained. The resistance included in the first thin-film multilayer wiring layer of the passive element built-in wiring substrate was 2Ω, and the capacitance of the capacitor was 1 μF, and the resistance was low and the capacitance was low.
On the other hand, the resistance composed of the thick film passive element film was 1.5Ω, and the capacitance of the capacitor was 2 μF, and it was confirmed that the capacitor had high resistance and sufficient capacitance. Moreover, the withstand voltage of this capacitor was 200V, and it was confirmed that it has a high withstand voltage.
Therefore, it was confirmed that a wide range of requirements for electrical characteristics can be met.

  The present invention can also be applied to small semiconductor devices and various electronic devices that require high reliability.

It is a schematic longitudinal cross-sectional view which shows one Embodiment of the passive element built-in wiring board of this invention. It is a schematic longitudinal cross-sectional view which shows other embodiment of the wiring board with a built-in passive element of this invention. It is a schematic longitudinal cross-sectional view which shows other embodiment of the wiring board with a built-in passive element of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the wiring board with a built-in passive element of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the wiring board with a built-in passive element of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the wiring board with a built-in passive element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1 ', 1 "... Passive element built-in wiring board 2 ... Silicon substrate 3 ... Insulating layer 4 ... Through hole 5 ... Conductive material 10 ... 1st thin film multilayer wiring layer 16 ... Electrode 17 ... Thin film passive element film 21 ... Pattern Electrode 22 ... Thick film passive element film 25 ... Planarization layer 30, 50 ... Second thin film multilayer wiring layer 41 ... Overcoat layer 56 ... Electrode 57 ... Thin film passive element film 18, 23, 58 ... Resistance 19, 24, 59 ... Capacitors

Claims (12)

  A silicon substrate, a first thin film multilayer wiring layer formed on at least one surface of the silicon substrate, a pattern electrode formed on the first thin film multilayer wiring layer, and a thickness connected to the pattern electrode A film passive element film and a second thin film multilayer wiring layer formed so as to cover the film, and the first thin film multilayer wiring layer and / or the second thin film multilayer wiring layer are thin film passive A wiring board with a built-in passive element characterized by a built-in element film.   A silicon substrate, a first thin film multilayer wiring layer formed on at least one surface of the silicon substrate, a pattern electrode formed on the first thin film multilayer wiring layer, and a thickness connected to the pattern electrode Passive element built-in, characterized in that it comprises a film passive element film and an overcoat layer formed so as to cover these films, and the first thin-film multilayer wiring layer contains a thin-film passive element film Wiring board.   The second thin film multilayer wiring layer is formed on the pattern electrode and the thick film passive element film through a planarization layer, and the planarization layer has vias for front and back conduction. The wiring board with a built-in passive element according to claim 1.   The passive element built-in wiring board according to claim 1, wherein the thick film passive element film constitutes at least one of a capacitor, a resistor, and an inductor.   The passive element built-in wiring board according to claim 1, wherein the pattern electrode is a thick film conductive electrode.   6. The passive element built-in wiring board according to claim 1, wherein the thin film passive element film constitutes at least one of a capacitor, a resistor, and an inductor.   7. The passive element built-in wiring substrate according to claim 1, wherein the silicon substrate includes a plurality of through holes that are electrically connected to each other by a conductive material. Forming a first thin film multilayer wiring layer on a silicon substrate;
Forming a pattern electrode so as to connect to a desired portion of the first thin-film multilayer wiring layer;
Forming a thick-film passive element film by a low-temperature thermosetting process in which the curing temperature is in the range of 100 to 200 ° C. so as to connect to a desired portion of the pattern electrode;
Forming a second thin film multilayer wiring layer so as to be connected to a desired portion of the pattern electrode,
A passive element built-in wiring board, wherein a thin film passive element film is formed by a thin film process in at least one of the step of forming the first thin film multilayer wiring layer and the step of forming a second thin film multilayer wiring layer. Production method. Forming a first thin film multilayer wiring layer on a silicon substrate;
Forming a pattern electrode so as to connect to a desired portion of the first thin-film multilayer wiring layer;
Forming a thick-film passive element film by a low-temperature thermosetting process in which the curing temperature is in the range of 100 to 200 ° C. so as to connect to a desired portion of the pattern electrode;
Forming an overcoat layer so as to cover the pattern electrode and the thick film passive element film,
In the step of forming the first thin film multilayer wiring layer, a thin film passive element film is formed by a thin film process.   9. The passive element built-in wiring according to claim 8, wherein a flattening layer is formed after the thick film passive element film is formed, and the second thin film multilayer wiring layer is formed on the flattening layer. A method for manufacturing a substrate.   The pattern electrode is formed by printing, drying, and thermosetting using a low-temperature thermosetting thick-film conductor paste having a curing temperature in the range of 100 to 250 ° C. The manufacturing method of the wiring board with a built-in passive element according to any one of the above.   The thin film multilayer wiring layer is formed by any one of a sputtering / semi-additive method, a sputtering / full additive method, and a sputtering / full-surface plating / subtractive method. The manufacturing method of the passive element built-in wiring board of description.

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