JP2007324297A - Method of manufacturing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board that incorporates a capacitor by which a change in shape of a dielectric can be reduced and the accuracy of the capacitor capacity in a substrate can be improved in the method of manufacturing the printed wiring board. <P>SOLUTION: A wiring layer 21a and a wiring layer 21b are formed on one surface of an insulating substrate 11, and a conductor layer 22 is formed on the other surface thereof, so as to manufacture a wiring board midway of a process. Next, a dielectric layer 31 and a conductor layer 25 are formed on the conductor layer 22, and the conductor layer 25 is patterned to form a capacitor upper electrode 25a. Furthermore, the dielectric layer 31 is patterned to form a dielectric 31a. The dielectric layer, protruding from the capacitor upper electrode 25a, is removed by blasting method, so as to form a dielectric 31b having corrected shape. The conductor layer 24 is patterned to form a capacitor lower electrode 24a, and a wiring board 100 incorporating a capacitor is obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board used in various electronic devices, and more particularly to a method of manufacturing a wiring board with a built-in capacitor that can improve the capacitance accuracy of the capacitor.

A recent manufacturing method with built-in components will be described below.
As an example of a method of manufacturing a wiring board with a built-in capacitor, a method of forming a capacitor dielectric by performing a series of patterning processes such as pattern exposure and development using a photosensitive dielectric layer ( For example, see Patent Document 1).
An example of a method for manufacturing a wiring board with a built-in capacitor is shown in FIGS. 5 (a) to 5 (e) and FIGS. 6 (f) to 6 (i).
First, the wiring layer 121 and the wiring layer 122 are formed on the insulating layer 111, and the conductor layer 124 made of copper foil or the like is formed via the insulating layer 112. The conductor layer 124, the wiring layer 121 and the wiring layer 122 are formed by vias 123. A wiring substrate in an intermediate process that is electrically connected is manufactured (see FIG. 5A).

Next, the dielectric layer 131 is formed by either applying a dielectric material obtained by dispersing ceramic powder or the like in a positive photosensitive epoxy resin or the like on the conductor layer 124 or laminating it in a sheet form. Form. Next, the conductor layer 125 is formed on the dielectric layer 131 by a method such as laminating a copper foil (see FIG. 5B).
Here, there is a method in which a dielectric sheet in which the dielectric layer 131 and the conductor layer 125 (copper foil) are integrated is bonded (for example, see Patent Document 2).

  Next, a photosensitive layer is formed on the conductor layer 125 by a method such as applying a photoresist or laminating a dry film, and patterning processing such as pattern exposure and development is performed to form a resist pattern 141 (FIG. 5 ( c)).

  Next, using the resist pattern 141 as a mask, the conductor layer 125 is etched with an etchant made of cupric chloride or the like to form a capacitor upper electrode 125a and expose the surface of the dielectric layer 131 (FIG. 5D). )reference).

  Next, the resist pattern 141 is not peeled off, and the dielectric layer 131 is exposed using the capacitor upper electrode 125a as a mask and developed with a dedicated developer, thereby forming the dielectric 131a below the capacitor upper electrode 125a. (See FIG. 5E).

  Next, after the dielectric 131a is thermally cured, the resist pattern 141 is peeled off, and the dielectric 131a and the capacitor upper electrode 125a are formed on the conductor layer 124 (see FIG. 6F).

  Next, a photosensitive layer 142 is formed by applying a photoresist or laminating a dry film on the conductor layer 124, the dielectric 131a and the capacitor upper electrode 125a (see FIG. 6G), and pattern exposure. Then, patterning processing such as development is performed to form resist patterns 142a and 142b (see FIG. 6H).

  Next, using the resist patterns 142a and 142b as a mask, the conductor layer 124 is etched with an etchant made of cupric chloride or the like to form a capacitor lower electrode 124a and a wiring layer 124b, and the capacitor upper electrode 125a and the dielectric 131a. And a capacitor lower electrode 124a are formed (see FIG. 6I).

  As another method, ceramic powder or the like is dispersed in non-photosensitive epoxy resin or the like in place of the dielectric layer 131 in which ceramic powder or the like is dispersed in positive photosensitive epoxy resin or the like in the above process. The dielectric layer 132 and the copper foil or the like made into an integrated structure are laminated to form the dielectric layer 132 and the conductor layer 125, and then the conductor layer 125 is patterned to form the capacitor upper electrode 125a. Alternatively, the dielectric layer 132 may be formed by etching the dielectric layer 132 with a dedicated etchant using the capacitor upper electrode 125a as a mask.

  In the method for manufacturing a wiring board as described above, the dielectric layer 131 or the dielectric layer 132 is processed only by chemical processing such as exposure, development, or etching, so that the shapes of the dielectric 131a and the dielectric layer 132a are the same. There is a problem that the shape has a trapezoidal skirt, and the shape has a large variation, which deteriorates the capacitance accuracy of the capacitor.

Furthermore, the chemical processing alone has a problem that the lower side of the capacitor upper electrode 125a is largely side-etched, and the variation is added to deteriorate the accuracy of the capacitor. In addition, there is a problem in that when multiple layers are formed by large side etching, bubbles remain in the side etched portion, cracks due to heat and moisture absorption, etc. occur, resulting in poor reliability.
JP 2002-534791 A JP 2003-11270 A

  The present invention has been made in view of the above problems, and in a method of manufacturing a printed wiring board with a built-in capacitor, a wiring board that reduces the variation in the shape of the dielectric and improves the accuracy of the capacitor capacity in the board. It aims at providing the manufacturing method of.

In order to achieve the above object in the present invention, first, in claim 1, a method of manufacturing a wiring board with a built-in capacitor is provided, comprising at least the following steps.
(A) A wiring layer 21a and a wiring layer 21b are formed on one surface of the insulating substrate 11, and a conductor layer 22 is formed on the other surface. The wiring layer 21a, the wiring layer 21b, and the conductor layer 22 are electrically connected by a via 23. The process of producing the wiring board of the middle process formed by being connected to.
(B) A step of forming the dielectric layer 31 and the conductor layer 25 on the conductor layer 22.
(C) A step of forming a resist pattern 41 on the conductor layer 25.
(D) A step of etching the conductor layer 25 using the resist pattern 41 as a mask to form the capacitor upper electrode 25a.
(E) A step of patterning the dielectric layer 31 using the resist pattern 41 and the capacitor upper electrode 25a as a mask to form the dielectric 31a.
(F) A step of removing the dielectric layer protruding from the capacitor upper electrode 25a by a blast method to form a shape-corrected dielectric 31b.
(G) A step of forming resist patterns 42a and 42b at predetermined positions of the conductor layer 24.
(H) A step of forming the capacitor lower electrode 24a by etching the conductor layer 24 using the resist patterns 42a and 42b as a mask and peeling the resist patterns 42a and 42b.

  According to a second aspect of the present invention, in the method for manufacturing a wiring board according to the first aspect, the blasting method is wet blasting.

  According to the method for manufacturing a wiring board of the present invention, after a dielectric layer is chemically processed to form a dielectric, a dielectric layer protruding from the capacitor upper electrode is formed using a blast method with the capacitor upper electrode as a mask. By physically removing the dielectric, a shape-corrected dielectric having the same size as the capacitor upper electrode can be obtained. By improving the shape of the dielectric, the capacitance accuracy of the capacitor in the wiring board is improved, and the capacitor Miniaturization is possible.

  In addition, since the dielectric layer is not chemically processed to the final shape, the processing is completed with less side etching, and the shape is corrected to the final shape by the blast method. In doing so, it is possible to prevent bubbles from remaining in the side-etched portion and causing cracks due to heat and moisture absorption.

  Further, by using wet blasting in the blasting method, smaller abrasive grains can be used, and since water is used, there is no heat generation of the substrate, metal oxidation and deformation can be prevented, and post-treatment can be reduced.

Hereinafter, embodiments of the present invention will be described.
FIGS. 1A to 1F and FIGS. 2G to 2J are partial schematic cross-sectional views showing an embodiment of a method of manufacturing a wiring board with a built-in capacitor according to the present invention.
First, the wiring layer 21a and the wiring layer 21b are formed on one surface of the insulating substrate 11, and the conductor layer 22 is formed on the other surface. The wiring layer 21a, the wiring layer 21b, and the conductor layer 22 are electrically connected by the vias 23. The connected double-sided wiring board 20 is produced (see FIG. 1A).

Next, a dielectric sheet 30 having a semi-cured dielectric layer 31 is formed on one side of the conductor layer 24 made of copper foil or the like (see FIG. 1B).
For example, the dielectric sheet 30 is formed by laminating a dielectric material sheet such as a resin sheet in which ceramic powder is dispersed in an organic insulating resin or a green sheet on the conductor layer 25 made of copper foil or the like, and performing a desired heat treatment. It is formed by a method or a method of directly applying a dielectric material on the conductor layer 25 made of copper foil or the like. Further, by forming the dielectric layer 31 on the smooth surface or the smoothed surface of the conductor layer 24 made of copper foil or the like, the film thickness accuracy of the dielectric layer 31 can be improved, and the capacitance of the capacitor can be increased.

Next, the dielectric layer 31 in a semi-cured state of the dielectric sheet 30 is laminated on the conductor layer 22 of the double-sided wiring board 20 and heat-cured, so that the dielectric layer is formed on the conductor layer 22 of the double-sided wiring board 20. 31 and the conductor layer 24 are formed (see FIG. 1C).
Here, after smoothing the surface of the conductor layer 22, the dielectric sheet 30 is adhered, thereby improving the film thickness accuracy of the dielectric layer 31 and improving the accuracy of the capacitor capacity.

  Next, a photosensitive layer is formed on the conductor layer 24 by a method such as applying a photoresist or laminating a dry film, and patterning processing such as pattern exposure and development is performed to form a resist pattern 41 (FIG. 1). (See (d)).

  Next, using the resist pattern 41 as a mask, the conductor layer 24 is etched with an etchant made of cupric chloride or the like to form a capacitor upper electrode 24a and expose the surface of the dielectric layer 31 (FIG. 1 (e)). )reference).

Next, the resist pattern 41 is not peeled off (may be peeled off), the capacitor upper electrode 24a is used as a mask, the dielectric layer 31 is exposed, and development processing is performed with a dedicated developer, whereby the capacitor upper electrode is exposed. A dielectric 31a is formed below 24a (see FIG. 1 (f)).
Here, when the dielectric layer 31 is a layer having no photosensitivity, the dielectric 31a is formed by performing a chemical etching process using the capacitor upper electrode 24a as a mask.

Next, after the dielectric 31a is heat-cured, the dielectric layer protruding from the capacitor upper electrode 24a is removed by blasting, for example, wet blasting using the capacitor upper electrode 24a as a mask, and the resist pattern 41 is physically removed. As a result, the shape-corrected dielectric 31b having the same size as the capacitor upper electrode 24a is formed (see FIG. 2G).
Here, the reason why the dielectric 31a is thermally cured before blasting is that workability during blasting is improved, and may be thermally cured after blasting.

  Next, a photosensitive layer 42 is formed by applying a photoresist or laminating a dry film on the conductor layer 22 and the capacitor upper electrode 24a (see FIG. 2 (h)), pattern exposure, development, etc. A patterning process is performed to form resist patterns 42a and 42b (see FIG. 2I).

Next, using the resist patterns 42a and 42b as a mask, the conductor layer 22 is etched with an etchant made of cupric chloride or the like, and the resist patterns 42a and 42b are stripped to form the capacitor lower electrode 22a and the wiring layer 22b. A wiring board 100 is formed on which a capacitor is formed, which is formed of the capacitor upper electrode 24a, the shape-corrected dielectric 31b, and the capacitor lower electrode 22a (see FIG. 2J).
Although the wiring board with a built-in capacitor has been described here, a spiral inductor can be formed simultaneously with the formation of the wiring layer 24b, and a passive element such as a resistance element can also be formed.

Furthermore, by performing a series of manufacturing steps of a wiring board such as an insulating layer, a wiring layer, a via, and a capacitor by a build-up process or the like, a multilayer wiring board with a built-in capacitor having a desired number of layers can be obtained.
The substrate on which the dielectric layer 31 is formed may be one in which the capacitor lower electrode 22a, the wiring layer 22b, etc. are formed in advance, and further, a smoothing resin layer between the capacitor lower electrode 22a and the wiring layer 22b. By providing 12, a smoother dielectric layer 31 can be formed (see FIG. 3).

  As described above, the method for manufacturing a wiring board according to the present invention is particularly effective for reducing the size of a wiring board for portable devices and the like, and particularly effective for increasing the capacity accuracy and reducing the size of a built-in capacitor. .

  First, a copper foil of a single-sided copper-clad plate impregnated with an epoxy resin in a non-woven glass is patterned by a photo-etching process, so that the wiring layer 21a and the wiring layer 21b are provided on one side of the insulating substrate 11, and the other side. Via 23 and conductor layer 22 are formed by an additive process using electroless copper plating and electrolytic copper plating, and the surface of conductor layer 22 is polished smoothly to form wiring layer 21a, wiring layer 21b, and conductor layer 22 A double-sided wiring board 20 electrically connected by vias 23 was produced (see FIG. 1A).

  Next, a dielectric material in which barium titanate or the like is mixed in a positive photosensitive epoxy resin is applied to the surface of the conductor layer 24 made of a copper foil whose surface is polished smoothly, dried at a desired temperature, A dielectric sheet 30 having a cured dielectric layer 31 was produced (see FIG. 1B).

Next, the dielectric layer 31 in a semi-cured state of the dielectric sheet 30 is laminated on the conductor layer 22 of the double-sided wiring board 20, and heated and pressed under the conditions of 130 ° C. and 30 N / cm ² to double-sided wiring. A dielectric layer 31 and a conductor layer 24 were formed on the conductor layer 22 of the plate 20 (see FIG. 1C).

  Next, a photosensitive dry film having a thickness of 15 μm was laminated on the conductor layer 24 to form a photosensitive layer, and pattern exposure processing and development processing were performed to form a resist pattern 41 (see FIG. 1D). .

  Next, using the resist pattern 41 as a mask, the conductor layer 24 is etched with an etchant made of cupric chloride to form a capacitor upper electrode 24a and expose the surface of the dielectric layer 31 (FIG. 1 (e)). )reference).

  Next, the resist pattern 41 is not peeled off, the capacitor upper electrode 24a is used as a mask, the dielectric layer 31 is exposed, developed with a dedicated developer, and subjected to a heat treatment at 200 ° C. for 1 hour. A dielectric 31a was formed below the upper electrode 24a (see FIG. 1 (f)).

  Next, by using the capacitor upper electrode 24a as a mask, the dielectric protruded from the capacitor upper electrode 25a by wet blasting in which fine abrasive grains such as alumina having a diameter of about 6 μm are jetted together with water from the nozzle at an air pressure of 0.2 MPa or the like. By removing the body layer and simultaneously removing the resist pattern 41 at the same time, the shape-corrected dielectric 31b having the same size as the capacitor upper electrode 24a was formed (see FIG. 2G).

  Next, a photosensitive dry film is laminated on the conductor layer 22 and the capacitor upper electrode 24a to form the photosensitive layer 42 (see FIG. 2 (h)), and pattern exposure processing and development patterning are performed to form the resist pattern 42a and 42b was formed (see FIG. 2 (i)).

  Next, using the resist patterns 42a and 42b as a mask, the conductor layer 22 is etched with an etching solution made of cupric chloride, and the resist patterns 42a and 42b are stripped to form the capacitor lower electrode 22a and the wiring layer 22b. Then, the wiring substrate 100 on which the capacitor composed of the capacitor upper electrode 24a, the shape-corrected dielectric 31b, and the capacitor lower electrode 22a was formed (see FIG. 2J).

  First, a copper foil of a single-sided copper-clad plate impregnated with an epoxy resin in a non-woven glass is patterned by a photo-etching process, so that the wiring layer 21a and the wiring layer 21b are provided on one side of the insulating substrate 11, and the other side. Via 23 and conductor layer 22 are formed by an additive process using electroless copper plating and electrolytic copper plating, and the surface of conductor layer 22 is polished smoothly to form wiring layer 21a, wiring layer 21b, and conductor layer 22 A double-sided wiring board 20 electrically connected by vias 23 was produced (see FIG. 1A).

  Next, a dielectric material in which barium titanate or the like is mixed with an epoxy resin is applied to the surface of the conductor layer 24 made of a copper foil whose surface is polished smoothly, dried at a desired temperature, and semi-cured dielectric A dielectric sheet 30a having a body layer 32 was produced (see FIG. 1B).

Next, the dielectric layer 32 in a semi-cured state of the dielectric sheet 30a is laminated on the conductor layer 22 of the double-sided wiring board 20, and heated and pressed under the conditions of 130 ° C. and 30 N / cm ² to double-sided wiring. A dielectric layer 32 and a conductor layer 24 were formed on the conductor layer 22 of the plate 20 (see FIG. 1C).

Next, a photosensitive dry film having a thickness of 15 μm was laminated on the conductor layer 24 to form a photosensitive layer, and pattern exposure processing and development processing were performed to form a resist pattern 41 (see FIG. 1D). .

  Next, using the resist pattern 41 as a mask, the conductor layer 24 is etched with an etchant made of cupric chloride to form a capacitor upper electrode 24a and expose the surface of the dielectric layer 32 (FIG. 1 (e)). )reference).

  Next, the resist pattern 41 is not peeled, and the surface of the lower conductive layer 22 does not appear on the dielectric layer 32 exposed using a dedicated etching solution using the capacitor upper electrode 24a as a mask (side etching is reduced). Etching and heat treatment at 200 ° C. for 1 hour were performed to form a dielectric 32a under the capacitor upper electrode 24a (see FIG. 4).

  Next, by using the capacitor upper electrode 24a as a mask, the dielectric protruded from the capacitor upper electrode 25a by wet blasting in which fine abrasive grains such as alumina having a diameter of about 6 μm are jetted together with water from the nozzle at an air pressure of 0.2 MPa or the like. By removing the body layer and simultaneously physically removing the resist pattern 41, the shape-corrected dielectric 32b having the same size as the capacitor upper electrode 24a was formed (see FIG. 2G).

  Next, a photosensitive dry film is laminated on the conductor layer 22 and the capacitor upper electrode 24a to form the photosensitive layer 42 (see FIG. 2 (h)), and pattern exposure processing and development patterning are performed to form the resist pattern 42a and 42b was formed (see FIG. 2 (i)).

  Next, using the resist patterns 42a and 42b as a mask, the conductor layer 22 is etched with an etching solution made of cupric chloride, and the resist patterns 42a and 42b are stripped to form the capacitor lower electrode 22a and the wiring layer 22b. Then, a wiring substrate 100a on which a capacitor composed of the capacitor upper electrode 24a, the shape-corrected dielectric 32b, and the capacitor lower electrode 22a was formed (see FIG. 2J).

(A)-(f) is typical structure sectional drawing which shows a part of process in the manufacturing method of the wiring board of this invention. (G)-(j) is typical structure sectional drawing which shows a part of process in the manufacturing method of the wiring board of this invention. 3 is a schematic cross-sectional view illustrating an example in which a dielectric layer 31 is formed by providing a smoothing resin layer between a capacitor lower electrode 22a and a wiring layer 22b. FIG. 3 is a schematic cross-sectional view showing an example of the shape of a dielectric 32a obtained by etching a dielectric layer 32. FIG. (A)-(e) is typical structure sectional drawing which shows a part of process in the manufacturing method of the conventional wiring board. (F)-(i) is typical structure sectional drawing which shows a part of process in the manufacturing method of the conventional wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating base material 12 ... Smoothing resin layer 21a, 21b, 22b, 121, 122 ... Wiring layer 20 ... Double-sided wiring board 22, 124 ... Conductor layer 22a, 124a ... Capacitor lower electrode 23, 123 ... via 24, 125 ... conductor layer (copper foil)
24a, 125a: Capacitor upper electrodes 30, 30a: Dielectric sheets 31, 32, 131, 132 ... Dielectric layers 31a, 32a, 131a, 132a ... Dielectrics 31b, 32b ... Shape-corrected dielectrics 41, 42a, 42b, 141, 142a, 142b... Resist pattern 42, 142... Photosensitive layer 100, 100a .. wiring substrate 111, 112.

Claims (2)

A method for manufacturing a wiring board with a built-in capacitor, comprising at least the following steps.
(A) A wiring layer (21a) and a wiring layer (21b) are formed on one surface of the insulating substrate (11), and a conductor layer (22) is formed on the other surface, and the wiring layer (21a) and the wiring layer (21b) are formed. ) And the conductor layer (22) are electrically connected by vias (23), and a process for producing a wiring substrate in the middle process.
(B) A step of forming a dielectric layer (31) and a conductor layer (25) on the conductor layer (22).
(C) A step of forming a resist pattern (41) on the conductor layer (25).
(D) A step of etching the conductor layer (25) using the resist pattern (41) as a mask to form a capacitor upper electrode (25a).
(E) A step of patterning the dielectric layer (31) using the resist pattern (41) and the capacitor upper electrode (25a) as a mask to form a dielectric (31a).
(F) A step of removing the dielectric layer protruding from the capacitor upper electrode (25a) by a blast method to form a shape-corrected dielectric (31b).
(G) A step of forming resist patterns (42a) and (42b) at predetermined positions of the conductor layer (24).
(H) Using the resist patterns (42a) and (42b) as a mask, the conductor layer (24) is etched, and the resist patterns (42a) and (42b) are stripped to form the capacitor lower electrode (24a). Process.   2. The method for manufacturing a wiring board according to claim 1, wherein the blasting method is wet blasting.

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