JP2005045000A - Method for manufacturing multilayered printed wiring board with built-in passive element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing multilayered wiring board with built-in passive element by which the productivity of a multilayered printed wiring board with a built-in passive element can be improved by shortening the laser beam machining time at the time of forming an opening for forming the passive element by laser beam machining. <P>SOLUTION: The method of manufacturing the multilayered printed wiring board with the built-in passive element includes a step of forming a lower electrode 31a for passive element at least at a prescribed position of a circuit board 50, a step of forming a resin layer 51 having a weak alkali resistance on the lower electrode 31a, and a step of forming an insulating layer 61. The method also includes a step of forming the opening 62 by punching the insulating film 61 formed on the lower electrode 31a, a step of forming a dielectric layer 71 in the opening 62, and a step of forming the passive element 80 by forming an upper electrode 81 for passive element on the dielectric layer 71. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a multilayer printed wiring board composed of a printed wiring board or an interposer used for various electronic devices, and more particularly to a method for manufacturing a multilayer printed wiring board with a built-in passive element.

  With recent thinning and high density of printed wiring boards or interposers, passive element built-in multilayer printed wiring boards in which passive elements are built into the printed wiring board have been proposed (for example, see Patent Document 1).

  A method for manufacturing a conventional multilayer printed wiring board with built-in passive elements will be described below.

  An example of the manufacturing method of the multilayer printed wiring board with a built-in passive element is shown in FIGS.

  First, the passive element lower electrode 121 is formed at a predetermined position on the circuit board 110 (see FIG. 2A).

  Next, the insulating layer 131 is formed by a method such as laminating an insulating resin sheet (see FIG. 2B).

  Next, the insulating layer 131 on the passive element lower electrode 121 is perforated with a carbon dioxide laser or the like to form an opening 132, and a residual treatment is performed with a strong alkaline solution made of permanganic acid, sodium hydroxide, or the like. (See FIG. 2 (c)).

  Next, a dielectric paste or a resistance paste is embedded in the opening 132 on the passive element lower electrode 121 by screen printing or a dispenser, and is cured by heating, and the surface is polished to form the passive element layer 141 (FIG. 2 (d)).

  Next, a passive element upper electrode 122 is formed on the passive element layer 141 by a process such as a semi-additive method, and a passive element 140 made of a capacitor element or a resistance element is formed to obtain a passive element built-in printed wiring board ( (Refer FIG.2 (e)).

  In the manufacturing method of the multilayer printed wiring board with a built-in passive element as described above, the insulating layer 131 is punched with a carbon dioxide gas laser, and a laser beam is overlapped when forming an opening with an area of several hundred μm to several mm square. Irradiation reduces the residual resin in the processed part, so there is a problem that the processing time is long and productivity is insufficient.

For example, when processing a carbon dioxide laser beam of 240 μmφ at 500 shots / second, the laser beam feed pitch must be set to 80 μm, which is 1/3 of the beam diameter of 240 μm, and processing is performed when a 4 mm square opening is formed. The time is about 5 seconds, and when about 300 4 mm square openings are formed on a 300 mm square printed wiring board, the processing time is about 1500 seconds. In the case of the UV-YAG laser, it is about 15000 seconds or more, which is about 10 times or more.
Japanese Patent Laid-Open No. 2003-100553

  The present invention has been made in view of the above-described problems. When forming an opening for forming a passive element by laser processing, the laser processing time is shortened, and the multilayer printed wiring board with a built-in passive element is designed to improve productivity. An object is to provide a manufacturing method.

In order to achieve the above object in the present invention, a method for manufacturing a multilayer printed wiring board with a built-in passive element includes the following steps in the method for manufacturing a multilayer printed wiring board with a built-in passive element. Is.
(A) A step of forming the passive element lower electrode 31 a at a predetermined position of the circuit board 50.
(B) The process of providing the resin layer 51 with weak alkali resistance on the lower electrode 31a for passive elements.
(C) A step of forming the insulating layer 61.
(D) A step of forming an opening 62 by drilling the insulating layer 61 on the passive element lower electrode 31a.
(E) A step of forming the dielectric layer 71 in the opening 62.
(F) A step of forming the passive element upper electrode 81 on the dielectric layer 71 and forming the passive element 80.

  In the method for manufacturing a multilayer printed wiring board with a built-in passive element according to the present invention, when forming an opening for forming a passive element, a resin layer weak in alkali resistance is formed on the lower electrode for the passive element. The pitch feed by the beam can be reduced to three times that of the prior art, and the processing time can be shortened to 1/9 of the conventional one, and the productivity of the multilayer printed wiring board with built-in passive elements can be improved.

  Hereinafter, embodiments of the present invention will be described.

  1A to 1F show an embodiment of a method for producing a multilayer printed wiring board with a built-in passive element according to the present invention.

  Hereinafter, a method for producing a multilayer printed wiring board with a built-in passive element according to the present invention will be described.

  The multilayer printed wiring board mentioned here is a generic term for a printed wiring board and an interposer board, and the interposer board is used to mediate between an IC chip or a semiconductor element and the printed wiring board, and is a BGA board or MCM board. , SCM substrates and the like.

  First, the first wiring layers 21a, 21b, 21c, and 21d are formed on both surfaces of the insulating base material 11, and the second wiring layers 31b, 31c, and 31d and the passive element lower electrode 31a are formed through the insulating layer 12. Thus, a four-layer circuit board 50 is manufactured (see FIG. 1A).

  Here, a four-layer circuit board is used as the base substrate for forming the passive elements. However, any circuit board can be used as the base substrate, and the number of wiring layers of the circuit board is not limited to this.

  Next, a resin paste is applied on the passive element lower electrode 31a by screen printing, and heated and cured to form a resin layer 51 having a predetermined thickness and poor alkali resistance (see FIG. 1B).

  As the resin layer 51 that is weak in alkali resistance, a carboxyl group-containing acrylic resin can be usually used, and the film thickness is preferably about 2 μm.

Next, an insulating resin sheet made of an epoxy resin or the like is laminated to form the insulating layer 61 (see FIG. 1C).

  Next, the insulating layer 61 on the passive element lower electrode 31a is drilled with a carbon dioxide laser or the like to form an opening 62, and the inside of the opening 62 is a strong alkaline solution made of permanganic acid, sodium hydroxide, or the like. The residual process is performed to expose the passive element lower electrode 31a (see FIG. 1D).

  Here, in the conventional method of forming an opening by laser processing, when a 4 mm square opening is laser processed using a laser beam having a diameter of 240 μm, for example, 500 shots / second, a 5 mm square opening with a feed pitch of 80 microns. The processing time is 5 seconds or more, and if about 300 openings are formed on a 300 mm square printed wiring board, the processing time is about 1500 seconds.

  In the method for forming an opening by the method for manufacturing a multilayer printed wiring board with a built-in passive element according to the present invention, since the resin layer 51 having weak alkali resistance is formed on the lower electrode 31a for the passive element that forms the opening, for example, 240 μm When laser processing is performed using a laser beam of a diameter, the feed pitch of the laser beam can be set to 240 μm, which is the same as the laser beam diameter, and when processing at 500 shots / second and a feed pitch of 240 μm, the processing time of a 5 mm square opening is about 0 .6 seconds, assuming that about 300 openings are formed on a 300 mm square printed wiring board, the processing time is about 160 seconds.

  As described above, by applying the processing method of the present invention, the processing time of the opening becomes about 1/9 of the conventional one, and the laser processing time can be shortened and the productivity can be improved.

  Next, a dielectric paste or a resistance paste is embedded in the opening by screen printing or a dispenser or the like, dried and cured, and subjected to a surface polishing process to form the passive element layer 71 (see FIG. 1E).

  Next, a passive element upper electrode 81 is formed by a semi-additive process or the like, and a passive element 80 such as a capacitor element or a resistance element is formed to obtain a passive element built-in multilayer printed wiring board 100 (FIG. 1F). reference).

  Hereinafter, the present invention will be described in detail by way of examples.

  First, a copper-clad laminate obtained by impregnating a non-woven glass with an epoxy resin is subjected to patterning to form first wiring layers 21a, 21b, 21c, and 21d. Further, the insulating layer 12 and the second layer are formed by a build-up process. The wiring layers 31b, 31c, 31d and the passive element lower electrode 31a were formed to produce a four-layer circuit board 50 (see FIG. 1A).

  Next, an acrylic resin paste was screen-printed on the lower electrode 31a for passive elements, dried and cured, and a resin layer 51 having a thickness of 2 μm and weak against alkali resistance was formed (see FIG. 1B).

  Next, an insulating insulating sheet 61 was formed by vacuum-pressure laminating an epoxy insulating resin sheet (see FIG. 1C).

  Next, the insulating layer 61 on the passive element lower electrode 31a is drilled at a pitch of 240 μm using a 240 μmφ carbon dioxide laser beam to form openings 62, and the inside of the openings 62 is permanganic acid, water Residue treatment was performed for about 20 minutes with a strong alkali solution made of sodium oxide or the like to expose the lower electrode 31a for the passive element (see FIG. 1D).

  Next, a dielectric paste in which barium titanate powder or the like is highly filled in an epoxy resin is embedded in the opening 62 with a dispenser, heat-cured, and subjected to a surface polishing process to form a dielectric layer. A passive element layer 71 was formed (see FIG. 1E).

  Next, for electrical connection between the insulating layers, a via hole of 60 μmφ is formed by a carbon dioxide laser, and the via hole is left for about 20 minutes with a strong alkaline solution made of permanganic acid, sodium hydroxide, or the like. An inspection process and a roughening process on the surface of the insulating layer were performed, a reduction process was performed, and a plating base conductive layer (not shown) was formed by electroless copper plating.

  Next, a photosensitive layer was formed on the base conductive layer, and a series of patterning processes such as pattern exposure and development were performed to form a plating resist pattern (not shown).

  Next, electrolytic copper plating is performed using the plating resist pattern as a mask, the plating resist pattern is peeled off, and the plating base conductive layer under the plating resist pattern is soft etched with an aqueous solution of ammonium persulfate, etc. The upper electrode 81 was formed to form a passive element 80 made of a capacitor element, and a multilayer printed wiring board 100 with a built-in passive element was obtained (see FIG. 1 (f)).

(A)-(f) is typical structure fragmentary sectional view which shows one Example of the manufacturing method of the multilayer printed wiring board with a built-in passive element of this invention in process order. (A)-(e) is a typical structure fragmentary sectional view which shows one Example of the manufacturing method of the conventional multilayer printed wiring board with a built-in passive element in order of a process.

Explanation of symbols

11 ... Insulating substrate 12 ... Insulating layers 21a, 21b, 21c, 21d ... First wiring layers 31a, 121 ... Passive element lower electrodes 31b, 31c, 31d ... Second wiring layers 50, 110 ... Circuit board 51... Resin layers 61, 131... Insulating layers 62, 132... Openings 71 and 141... Passive element layers 80 and 140... Passive elements 81 and 122. 100 …… Multilayer printed wiring board with built-in passive elements

Claims (1)

In the manufacturing method of the multilayer printed wiring board with a built-in passive element, the manufacturing method of the multilayer printed wiring board with a built-in passive element characterized by including the following processes at least.
(A) A step of forming a passive element lower electrode (31a) at a predetermined position on the circuit board (50).
(B) A step of forming a resin layer (51) having low alkali resistance on the passive element lower electrode (31a).
(C) A step of forming an insulating layer (61).
(D) A step of drilling the insulating layer (61) on the passive element lower electrode (31a) to form the opening (62).
(E) A step of forming a dielectric layer (71) in the opening (62).
(F) A step of forming a passive element upper electrode (81) on the dielectric layer (71) to form a passive element (80).