JP2007184455A - 電子回路基板 - Google Patents
電子回路基板 Download PDFInfo
- Publication number
- JP2007184455A JP2007184455A JP2006002275A JP2006002275A JP2007184455A JP 2007184455 A JP2007184455 A JP 2007184455A JP 2006002275 A JP2006002275 A JP 2006002275A JP 2006002275 A JP2006002275 A JP 2006002275A JP 2007184455 A JP2007184455 A JP 2007184455A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- outflow prevention
- hole
- electronic component
- soldered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】電子部品が半田付けされる位置にスルーホール(11)を設けると共に、基板裏面(1B)においてスルーホール(11)の周囲に枠状の半田流出阻止層(13,14)を設けることで、スルーホール(11)から基板裏面(1B)に流出しようとする半田を塞き止め、スルーホール(11)内に半田を充填する。また、枠状の半田流出阻止層(13,14)に切れ目部(13a,14a)を形成することで、スルーホール(11)内の充填量を超える余剰な半田を半田流出阻止層(13,14)の枠外に逃がす。
【選択図】図2
Description
Claims (4)
- 電子部品が半田付けされる位置に設けられるスルーホールと、前記電子部品が半田付けされる面の裏面において前記スルーホールの周囲に設けられる枠状の半田流出阻止層とを備える共に、前記枠状の半田流出阻止層に少なくとも1箇所の切れ目部を形成したことを特徴とする電子回路基板。
- 電子部品が半田付けされる位置に設けられるスルーホールと、前記電子部品が半田付けされる面の裏面に半田付けされる放熱板と、前記放熱板において前記スルーホールと対峙する部位の周囲に設けられる枠状の半田流出阻止層とを備えることを特徴とする電子回路基板。
- 請求項2に記載の電子回路基板において、
前記枠状の半田流出阻止層に少なくとも1箇所の切れ目部を形成したことを特徴とする電子回路基板。 - 請求項1または3に記載の電子回路基板において、
前記枠状の半田流出阻止層が複数設けられると共に、前記複数の半田流出阻止層のそれぞれに前記切れ目部が形成されることを特徴とする電子回路基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006002275A JP4746990B2 (ja) | 2006-01-10 | 2006-01-10 | 電子回路基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006002275A JP4746990B2 (ja) | 2006-01-10 | 2006-01-10 | 電子回路基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007184455A true JP2007184455A (ja) | 2007-07-19 |
JP4746990B2 JP4746990B2 (ja) | 2011-08-10 |
Family
ID=38340272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006002275A Active JP4746990B2 (ja) | 2006-01-10 | 2006-01-10 | 電子回路基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4746990B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015056546A (ja) * | 2013-09-12 | 2015-03-23 | アルプス電気株式会社 | 電子回路モジュール |
CN108513433A (zh) * | 2018-04-24 | 2018-09-07 | 苏州维信电子有限公司 | 一种隔锡的柔性线路板pad及其制造方法 |
JP7455078B2 (ja) | 2021-02-02 | 2024-03-25 | 株式会社日立産機システム | プリント配線板 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318579A (ja) * | 2002-04-24 | 2003-11-07 | Toyoda Mach Works Ltd | 放熱板付きfetの放熱方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5441102B2 (ja) * | 1975-03-04 | 1979-12-06 |
-
2006
- 2006-01-10 JP JP2006002275A patent/JP4746990B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318579A (ja) * | 2002-04-24 | 2003-11-07 | Toyoda Mach Works Ltd | 放熱板付きfetの放熱方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015056546A (ja) * | 2013-09-12 | 2015-03-23 | アルプス電気株式会社 | 電子回路モジュール |
CN108513433A (zh) * | 2018-04-24 | 2018-09-07 | 苏州维信电子有限公司 | 一种隔锡的柔性线路板pad及其制造方法 |
JP7455078B2 (ja) | 2021-02-02 | 2024-03-25 | 株式会社日立産機システム | プリント配線板 |
Also Published As
Publication number | Publication date |
---|---|
JP4746990B2 (ja) | 2011-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3639505B2 (ja) | プリント配線基板及び半導体装置 | |
JP2008078271A (ja) | 放熱構造を備えたプリント基板の製造方法および放熱構造を備えたプリント基板 | |
JP2004103998A (ja) | 回路部品内蔵モジュール | |
JP2007012850A (ja) | 回路基板 | |
JP2006080168A (ja) | プリント配線板の放熱構造 | |
JP4746990B2 (ja) | 電子回路基板 | |
JP5213074B2 (ja) | プリント配線板及びそれに用いるパッド設計手法 | |
JP2010267869A (ja) | 配線基板 | |
WO2016157478A1 (ja) | 配線基板および電子装置 | |
TW201340792A (zh) | 印刷電路板 | |
JP2011108814A (ja) | 面実装電子部品の接合方法及び電子装置 | |
JP4821710B2 (ja) | プリント配線板 | |
JP2012227349A (ja) | 電子部品の実装方法 | |
JP2005340233A (ja) | 電子回路基板 | |
JP2013171963A (ja) | プリント基板装置および電子機器 | |
JP2016181575A (ja) | 放熱基板及び半導体装置 | |
JP2008172094A (ja) | 回路基板及び電子機器 | |
JP2004221415A (ja) | 半導体パッケージの実装構造 | |
WO2017221419A1 (ja) | 回路基板およびその製造方法ならびに電子装置 | |
JP2004079872A (ja) | 電子回路ユニットの半田付け構造 | |
JP2018116976A (ja) | プリント回路基板 | |
JP6488669B2 (ja) | 基板 | |
JP6430894B2 (ja) | 半導体装置及びその製造方法 | |
JP2007258654A (ja) | 回路基板のランド接続方法及び回路基板 | |
JP2009099779A (ja) | プリント配線板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110125 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110326 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110510 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110516 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4746990 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |