JP2007122483A5 - - Google Patents

Download PDF

Info

Publication number
JP2007122483A5
JP2007122483A5 JP2005314842A JP2005314842A JP2007122483A5 JP 2007122483 A5 JP2007122483 A5 JP 2007122483A5 JP 2005314842 A JP2005314842 A JP 2005314842A JP 2005314842 A JP2005314842 A JP 2005314842A JP 2007122483 A5 JP2007122483 A5 JP 2007122483A5
Authority
JP
Japan
Prior art keywords
data
bus
remaining
master
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005314842A
Other languages
English (en)
Japanese (ja)
Other versions
JP4974508B2 (ja
JP2007122483A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2005314842A priority Critical patent/JP4974508B2/ja
Priority claimed from JP2005314842A external-priority patent/JP4974508B2/ja
Priority to US11/550,857 priority patent/US7685344B2/en
Publication of JP2007122483A publication Critical patent/JP2007122483A/ja
Publication of JP2007122483A5 publication Critical patent/JP2007122483A5/ja
Application granted granted Critical
Publication of JP4974508B2 publication Critical patent/JP4974508B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005314842A 2005-10-28 2005-10-28 バスマスタ装置、バス調停装置及びバス調停方法 Expired - Fee Related JP4974508B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005314842A JP4974508B2 (ja) 2005-10-28 2005-10-28 バスマスタ装置、バス調停装置及びバス調停方法
US11/550,857 US7685344B2 (en) 2005-10-28 2006-10-19 Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005314842A JP4974508B2 (ja) 2005-10-28 2005-10-28 バスマスタ装置、バス調停装置及びバス調停方法

Publications (3)

Publication Number Publication Date
JP2007122483A JP2007122483A (ja) 2007-05-17
JP2007122483A5 true JP2007122483A5 (enExample) 2008-12-04
JP4974508B2 JP4974508B2 (ja) 2012-07-11

Family

ID=38024207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005314842A Expired - Fee Related JP4974508B2 (ja) 2005-10-28 2005-10-28 バスマスタ装置、バス調停装置及びバス調停方法

Country Status (2)

Country Link
US (1) US7685344B2 (enExample)
JP (1) JP4974508B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5408844B2 (ja) * 2006-07-04 2014-02-05 キヤノン株式会社 バスシステム
JP4953794B2 (ja) * 2006-12-20 2012-06-13 キヤノン株式会社 バスシステムのバス調停方法及びバスシステム
KR20080074545A (ko) * 2007-02-09 2008-08-13 삼성전자주식회사 버스 시스템 및 그 제어 방법
FR2916873B1 (fr) * 2007-05-29 2009-09-18 Schneider Electric Ind Sas Dispositif de controle de communication entre un module et un bus de transmission
JP2009151685A (ja) * 2007-12-21 2009-07-09 Fujitsu Ltd ディスクアレイ装置管理システム、ディスクアレイ装置、ディスクアレイ装置の制御方法および管理サーバ
JP2010282405A (ja) * 2009-06-04 2010-12-16 Renesas Electronics Corp データ処理システム
JP5677007B2 (ja) * 2010-10-04 2015-02-25 キヤノン株式会社 バス調停装置、バス調停方法
US8527684B2 (en) * 2010-11-12 2013-09-03 Lsi Corporation Closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC
JP5776022B2 (ja) * 2011-04-13 2015-09-09 パナソニックＩｐマネジメント株式会社 制御装置
JP2014016730A (ja) * 2012-07-06 2014-01-30 Canon Inc バス調停装置、バス調停方法、及びコンピュータプログラム
US9372818B2 (en) * 2013-03-15 2016-06-21 Atmel Corporation Proactive quality of service in multi-matrix system bus
US9851902B2 (en) * 2014-10-09 2017-12-26 Memobit Technologies Ab Searching memory for a search key
US10223312B2 (en) * 2016-10-18 2019-03-05 Analog Devices, Inc. Quality of service ordinal modification

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03263158A (ja) * 1990-03-13 1991-11-22 Nec Corp 共通バス調停制御方式
FR2664772A1 (fr) * 1990-07-13 1992-01-17 Thomson Csf Reseau local d'intercommunication de modules de traitement de donnees.
JPH05173930A (ja) * 1991-12-19 1993-07-13 Yokogawa Electric Corp Ｄｍａ制御回路
JPH0660017A (ja) * 1992-08-06 1994-03-04 Nec Eng Ltd 競合回路
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5506969A (en) * 1993-11-29 1996-04-09 Sun Microsystems, Inc. Method and apparatus for bus bandwidth management
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade
US6178475B1 (en) * 1994-12-19 2001-01-23 Advanced Micro Devices Inc. Multimedia system employing timers to properly allocate bus access
US5787482A (en) * 1995-07-31 1998-07-28 Hewlett-Packard Company Deadline driven disk scheduler method and apparatus with thresholded most urgent request queue scan window
JPH09231165A (ja) * 1996-02-28 1997-09-05 Sharp Corp バス調停制御システム
US5907688A (en) * 1996-06-28 1999-05-25 Intel Corporation Smart arbitration for non-symmetric data streams
DE69735614T2 (de) * 1996-10-18 2006-09-07 Matsushita Electric Industrial Co., Ltd., Kadoma Datenübertragungsgerät und Datenübertragungssystem zur Arbitrierung von mehreren E/A Ports in DMA
US5901296A (en) * 1996-12-06 1999-05-04 International Business Machines Corporation Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus
US6553476B1 (en) * 1997-02-10 2003-04-22 Matsushita Electric Industrial Co., Ltd. Storage management based on predicted I/O execution times
US6324570B1 (en) * 1997-02-25 2001-11-27 E-Parcel, Llc Prioritized delivery and content auto select system
US6028843A (en) * 1997-03-25 2000-02-22 International Business Machines Corporation Earliest deadline first communications cell scheduler and scheduling method for transmitting earliest deadline cells first
JPH10289203A (ja) 1997-04-14 1998-10-27 Matsushita Electric Ind Co Ltd バス調停装置
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture
US5948089A (en) * 1997-09-05 1999-09-07 Sonics, Inc. Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation
JPH11242506A (ja) * 1998-02-24 1999-09-07 Omron Corp プログラマブルコントローラ
US6731295B1 (en) * 1998-11-09 2004-05-04 Broadcom Corporation Graphics display system with window descriptors
WO2000042515A1 (en) * 1999-01-12 2000-07-20 Fujitsu Limited Access control device and method for controlling access to recording medium
US6801943B1 (en) * 1999-04-30 2004-10-05 Honeywell International Inc. Network scheduler for real time applications
JP2001077835A (ja) * 1999-08-31 2001-03-23 Sony Corp 情報通信方法及び装置
US6785283B1 (en) * 1999-12-30 2004-08-31 Lucent Technologies Inc. Quality of service (QOS) enforcement method
US7002980B1 (en) * 2000-12-19 2006-02-21 Chiaro Networks, Ltd. System and method for router queue and congestion management
US6877053B2 (en) * 2001-01-03 2005-04-05 Nec Corporation High performance communication architecture for circuit designs using probabilistic allocation of resources
US6728792B2 (en) * 2001-01-04 2004-04-27 International Business Machines Corporation Priority queue with arbitrary queuing criteria
JP2002207691A (ja) * 2001-01-11 2002-07-26 Matsushita Electric Ind Co Ltd データ転送制御装置
US6820150B1 (en) * 2001-04-11 2004-11-16 Microsoft Corporation Method and apparatus for providing quality-of-service delivery facilities over a bus
US7302686B2 (en) * 2001-07-04 2007-11-27 Sony Corporation Task management system
US6804738B2 (en) * 2001-10-12 2004-10-12 Sonics, Inc. Method and apparatus for scheduling a resource to meet quality-of-service restrictions
US6845417B2 (en) * 2002-01-09 2005-01-18 Hewlett-Packard Development Company, L.P. Ensuring fairness in a multiprocessor environment using historical abuse recognition in spinlock acquisition
US7080177B2 (en) * 2002-03-01 2006-07-18 Broadcom Corporation System and method for arbitrating clients in a hierarchical real-time DRAM system
US20030167381A1 (en) * 2002-03-04 2003-09-04 Israel Herscovich System and method for dynamic memory access management
JP2003316727A (ja) * 2002-04-25 2003-11-07 Matsushita Electric Ind Co Ltd バス調停方法、及びバス調停装置
JP2004021613A (ja) * 2002-06-17 2004-01-22 Seiko Epson Corp データ転送制御装置、電子機器及びデータ転送制御方法
JP4151362B2 (ja) * 2002-09-26 2008-09-17 日本電気株式会社 バス調停方式、データ転送装置、及びバス調停方法
US7093256B2 (en) * 2002-12-13 2006-08-15 Equator Technologies, Inc. Method and apparatus for scheduling real-time and non-real-time access to a shared resource
US7472159B2 (en) * 2003-05-15 2008-12-30 International Business Machines Corporation System and method for adaptive admission control and resource management for service time guarantees
JP2005085079A (ja) * 2003-09-10 2005-03-31 Matsushita Electric Ind Co Ltd データ転送制御装置
US7089381B2 (en) * 2003-09-24 2006-08-08 Aristos Logic Corporation Multiple storage element command queues
US7197577B2 (en) * 2003-12-12 2007-03-27 International Business Machines Corporation Autonomic input/output scheduler selector
US20050207441A1 (en) * 2004-03-22 2005-09-22 Onggosanusi Eko N Packet transmission scheduling in a multi-carrier communications system
US7379953B2 (en) * 2005-02-22 2008-05-27 International Business Machines Corporation Systems and methods for resource-adaptive workload management
US8473563B2 (en) * 2005-04-22 2013-06-25 GM Global Technology Operations LLC Extensible scheduling of messages on time-triggered busses

Similar Documents

Publication Publication Date Title
JP2007122483A5 (enExample)
JP2006277620A5 (enExample)
CN102203752B (zh) 具有多个队列之间的仲裁的数据处理电路
JP5069325B2 (ja) タスク実行制御装置及びプログラム
JP5666722B2 (ja) メモリ・インターフェース
RU2012149789A (ru) Измерительное средство для функций адаптера
CN103116563B (zh) 一种主机通信方法、一种主机及通信系统
JP2016186828A5 (ja) 記憶装置および記憶制御方法
TW201447563A (zh) Cpu的總線測試裝置及其方法
EP1811393B1 (en) Method and system for data transfer
US7685344B2 (en) Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter
USRE40261E1 (en) Apparatus and method of partially transferring data through bus and bus master control device
CN100547572C (zh) 动态建立直接内存访问通路的方法及系统
JP2009048298A5 (enExample)
JP2008515090A5 (enExample)
JP2011133940A5 (enExample)
JP6039522B2 (ja) 外部入出力装置および調停設定結果格納方法
TW200736920A (en) Arbiter and arbitrating method
JP3987750B2 (ja) メモリ制御装置及びｌｓｉ
JP4953794B2 (ja) バスシステムのバス調停方法及びバスシステム
JP2011059915A (ja) 半導体装置
JPH0696014A (ja) バス使用優先順位制御装置
JP2013196696A (ja) 仮想マシンのメモリー管理システム及びその方法
CN108647098A (zh) 一种确定数值变化速度的方法及装置
EP1424634A3 (en) Avoidance of extended bus occupancy through simple control operation