JP2007103736A - Electronic component, manufacturing method therefor, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component that is low-priced, easy to process, and realizes a good manufacturing yield, particularly an interposer substrate having a decoupling capacitor. <P>SOLUTION: In the electronic component, a substrate 10 comprises at least capacitors 20 that are disposed on at least one main surface of the substrate and are capable of being connected to a semiconductor device; an insulator 11 that comprises a glass ceramic having a ceramic aggregate and a glass material; and a via electrode 12 that is formed in the insulator and exposed to both main surfaces of the substrate. It is preferable that the capacitor, in particular, is manufactured by a thin film process, and that the substrate is a multilayer substrate wired therein. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic component having a substrate on which an electric element such as a capacitor, a coil, and a resistor can be formed, and in particular, an electronic component including a substrate on which a decoupling capacitor is formed and a semiconductor element such as a CPU can be mounted. It is about.

  In recent years, as the operating frequency of integrated circuits such as LSIs has increased, the clock rise time has become very short. Furthermore, there is a case where the power supply voltage is reduced due to low power consumption, and the power supply voltage of the LSI tends to become unstable when the power supply load accompanying the operation of the LSI suddenly fluctuates. Need to stabilize.

  For this reason, a method has been adopted in which a decoupling capacitor is disposed between the LSI voltage power supply line and the ground line to stabilize the operating power supply voltage.

  In order to stabilize this operating power supply voltage, it is necessary to reduce the equivalent series inductance and increase the capacity of the decoupling capacitor. Furthermore, in order to maximize the function of the decoupling capacitor, it is necessary to dispose the decoupling capacitor as close to the LSI as possible to reduce the inductance of the wiring between the LSI and the decoupling capacitor.

In order to solve such problems, an interposer is disposed between the mounting substrate and the semiconductor chip on which the mounting substrate is mounted, and a through via electrode (through-hole electrode) is provided on the interposer, Discloses a semiconductor device in which a capacitor is formed (Patent Document 1). And the insulator used for the interposer described in the same document uses silicon and glass, and a capacitor is formed on the silicon or glass substrate by using a thin film technique.
JP 2001-326305 A

  However, the electronic parts such as the semiconductor device have the following problems.

  First, there is a problem associated with the formation of through vias.

  In an electronic component having an interposer substrate provided with a through via electrode (through hole), it is required to design the via electrode diameter (or area) as small as possible in order to secure a patterning region of the through via electrode. Specifically, a via electrode diameter of about 50 to 100 μm and in some cases less than 50 μm is required. In order to stably form such a small diameter via electrode, it is necessary to reduce the thickness of the wafer on which the interposer substrate is formed. For example, when a via diameter of about 50 to 100 μm is required, the thickness of the wafer needs to be about 100 to 200 μm. In addition, when a via diameter of less than 50 μm is required, the thickness of the wafer may have to be 100 μm or less.

  However, if silicon or glass is used for the wafer to reduce its thickness, the strength of the wafer is reduced and the entire wafer is easily warped. In particular, a decrease in the strength of the wafer affects handling in each processing process, and problems such as breakage of the wafer itself may occur.

  In addition, when a via electrode is formed on a substrate using silicon or glass, wiring in the substrate is difficult and a through type is used. For this reason, when the electrode pitch of the connection electrodes formed in the IC such as a CPU is narrow, the IC side via electrode pitch width of the interposer substrate connected thereto is also narrowed. Further, the electrode pitch width exposed from the IC side to the mounting substrate side through the through via electrode is also narrowed. For this reason, electrodes having a narrow pitch width are connected to each other, which tends to be a factor of deteriorating the manufacturing yield.

  A second problem is cost.

  For example, in order to form a through via in a silicon substrate, it is formed through the following steps.

First, a resist pattern is formed on a silicon substrate using a photolithographic technique, and a via is formed to an appropriate depth not penetrating through etching using a dry etcher such as ICP (inductively coupled plasma). Thereafter, an SiO ₂ film is formed on the surface of the silicon substrate by thermal oxidation to form an insulating layer. Then, in order to form a base film for electroplating Cu or the like, a base conductor layer is formed on the substrate surface and the via inner surface using a CVD (Chemical Vapor Deposition) method or the like, and Cu or the like is formed by via fill plating or the like. Are deposited in the substrate surface and in the vias. Next, the surface of the substrate is polished using CMP (Chemical Mechanical Polishing), and the via is filled with a conductive material such as Cu. Further, the back surface side of the substrate is polished until the via electrode is exposed, and an insulating layer is formed on the back surface of the substrate by thermal oxidation to form a through via electrode.

  As described above, forming a through via in a silicon substrate requires a complicated process using many processes such as an expensive vacuum film forming method and a processing technique, so that it tends to be expensive in terms of manufacturing cost. Furthermore, in order to form a thin film capacitor on a silicon substrate, the surface roughness (Ra) of the substrate surface needs to be mirror-finished to about several nanometers, so that the cost of the substrate material is also expensive.

  SUMMARY OF THE INVENTION Accordingly, the present invention is to provide an electronic component, particularly an interposer substrate having a decoupling capacitor, which is inexpensive, easy to process, and has a good manufacturing yield.

  An electronic component according to the present invention is a substrate on which at least a capacitor is formed that can be connected to a semiconductor element, and the capacitor is provided on at least one main surface of the substrate. The substrate includes a ceramic aggregate and a glass material. And a plurality of via electrodes formed inside the insulator and exposed on both main surfaces of the substrate.

  Here, the element formed on the substrate may be a coil or a resistor in addition to the capacitor. Moreover, it is preferable to connect a semiconductor element on the main surface of the substrate on which the capacitor is formed. This is because a low inductance can be achieved when the capacitor is used as a decoupling capacitor. In addition, the via electrode formed inside may have a three-dimensionally wired structure that has no wiring pattern in the direction of each sheet surface, such that the two main surfaces of the substrate are simply electrically connected, A simple through electrode structure may be used.

Further, the via electrodes of the substrate are exposed on both main surfaces of the substrate, and the number of via electrodes exposed on one main surface is preferably different from the number of via electrodes exposed on the other main surface. . Furthermore, it is preferable that the number of via electrodes exposed on the other main surface is smaller than the number of via electrodes exposed on the main surface of the substrate to which the semiconductor element can be connected. That is, an external element is connected to the other main surface, but it is preferable to reduce the number of via electrodes formed on the external element connection surface side. Furthermore, it is preferable to increase the pitch width of the via electrode.

  Further, the via electrode of the substrate preferably has a larger area of the via electrode exposed on the other main surface, that is, the external element connection surface, than the area of the via electrode exposed on the main surface connected to the semiconductor element. . Note that the shape of the via electrode exposed on the main surface is not limited to a circle and is not particularly limited to a polygon or the like.

  The substrate is preferably a multilayer substrate, and the thickness of the layer having the main surface connected to the semiconductor element is preferably smaller than the thickness of the layer having the other main surface. Specifically, the thickness of the layer having the main surface connected to the semiconductor element is 20 to 80 μm, the thickness of the layer having the other main surface, that is, the thickness of the layer having the external element connection surface is 50 to 160 μm. It is preferable to do.

  The capacitor formed on the substrate preferably includes at least a lower electrode film, a dielectric thin film, and an upper electrode film, and at least the dielectric thin film is preferably formed by a thin film process. Here, the thin film process indicates a gas phase method such as a sputtering method or a CVD method, a solution method such as a MOD method or a sol-gel method, and the like, and refers to a process capable of forming a thin film having a thickness of about 500 nm or less.

  The capacitor is preferably formed directly on the via electrode exposed on at least one main surface of the substrate.

  Preferably, a semiconductor element is connected to one main surface of the electronic component, and a CPU package is connected to a main surface opposite to the connection surface to form a semiconductor device. That is, it is preferable to use the electronic component according to the present invention as an interposer substrate. At that time, the electronic component may be mounted on the CPU package or embedded in the CPU package.

  The method for manufacturing an electronic component according to the present invention includes a step of forming a predetermined via hole in a green sheet having a ceramic aggregate and a glass material, a step of filling the via hole with an electrode, and a predetermined electrode on the surface of the green sheet. At least one of a step of forming a pattern, a step of laminating a green sheet on which a predetermined via electrode and electrode pattern are formed, a step of firing a laminate obtained by laminating, and a fired body obtained by firing Polishing a main surface of the substrate, forming a capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are sequentially stacked on the processed surface, and forming a semiconductor element connection electrode capable of connecting a semiconductor element; The dielectric thin film of the capacitor is formed by a thin film formation process.

Further, in the method of manufacturing the electronic component, in the step of forming a predetermined via hole in the green sheet having the ceramic aggregate and the glass material, the thickness of the green sheet on the side on which the semiconductor element connection electrode is formed is changed to the semiconductor. It is preferable to form the via hole using a sheet thinner than the thickness of the green sheet on the side opposite to the side where the element connection electrode is formed. By using a relatively thin sheet as a green sheet for forming a semiconductor element connection electrode to which a semiconductor element can be connected, a smaller through hole can be formed. Therefore, the pitch of the via electrodes can be reduced and the area (or diameter) thereof can be reduced. Specifically, it is preferable to use a sheet having a thickness after firing of 20 to 80 μm. On the other hand, it is preferable to use a relatively thick sheet as the green sheet on the side opposite to the side on which the semiconductor element connection electrode is formed, that is, on the external element connection surface side. By using a thick sheet, the number of stacked layers can be reduced. Further, by using a relatively thick sheet, a larger through hole can be formed, and the area (or diameter) of the via electrode can be increased. Specifically, it is preferable to use a sheet having a thickness after firing of 50 to 160 μm.

  Further, in the method of manufacturing the electronic component, after polishing at least one main surface of a fired body obtained by firing, an external element connection electrode is formed on the other main surface by a thick film method. It is preferable to have.

  Further, in the method of manufacturing the electronic component, the step of forming the capacitor may include forming the capacitor by sequentially forming the lower conductive layer, the dielectric layer, and the upper conductive layer, and then etching each layer at once. preferable.

  According to the present invention, the following effects can be achieved.

  The electronic component according to the present invention can form a thin film capacitor by selecting a wide range of conditions in order to form a substrate using a glass ceramic that is thermally or chemically stable compared to a silicon substrate or a glass substrate. Furthermore, it is possible to mount a semiconductor element with a configuration that allows free multilayer wiring inside the substrate. In addition, when forming a via electrode on a substrate, it is not necessary to use a lot of expensive processes such as a vacuum film forming method and a processing technique, so that it is cheaper than a substrate made using a wafer such as silicon. Semiconductor devices and the like can be manufactured.

  Further, the number of via electrodes exposed on one main surface is different from the number of via electrodes exposed on the other main surface, and further, the number of via electrodes exposed on the main surface of the substrate to which a semiconductor element can be connected, Since the number of via electrodes exposed on the other main surface, that is, the external device connection surface is small, the via electrode pitch exposed on the external device connection surface can be increased, and the connection to the external device is more reliable. Manufacturing yield can be improved. In addition, in order to increase the pitch, it is possible to form the external element connection electrode by using the thick film method, and it is possible to form it at a lower cost compared to the case of forming by using the thin film method.

  Also, since the area of the via electrode exposed on the other main surface, that is, the external element connection surface, is larger than the area of the via electrode exposed on the main surface connected to the semiconductor element, it is the same as increasing the electrode pitch. In addition, the connection with the external element can be made more reliable. Also, a large current can be passed by increasing the area of the via electrode exposed on the external element connection surface.

  By using the internal wiring on the semiconductor element mounting surface side, the patterning process can be simplified for the capacitor formed on the substrate surface. Further, since the via electrode area exposed on the semiconductor element connection surface is small, more capacitors can be formed.

  In addition, the substrate is a multilayer substrate, and the thickness of the layer having the main surface connected to the semiconductor element is smaller than the thickness of the layer having the other main surface, thereby exposing the via exposed to the semiconductor element mounting surface. The electrode area can be further reduced, that is, the through hole having a smaller area can be formed by reducing the layer thickness.

  In addition, since the capacitor can be efficiently designed by forming the capacitor immediately above the via electrode exposed on at least one main surface of the substrate, the capacitor has a sufficient electrode overlapping area. The capacity can be increased. Further, when the capacitor is formed by a thin film process, it can be formed by etching the lower electrode film, the dielectric film, and the upper electrode film at once, and the process can be simplified. Furthermore, by making the upper electrode and the lower electrode of the capacitor have the same shape, the capacitor capacity can be obtained efficiently.

  In addition, since the semiconductor device according to the present invention uses the electronic component as an interposer, it is possible to obtain a device that is inexpensive and has a good manufacturing yield.

  In addition, the method of manufacturing an electronic component according to the present invention has a wide range for forming a capacitor by a thin film process on a substrate using a glass ceramic that is thermally or chemically stable as compared with a silicon substrate or a glass substrate. A thin film capacitor can be formed by selecting these conditions, and further, a semiconductor element can be mounted with a configuration that allows free multilayer wiring inside the substrate. In addition, a semiconductor device can be manufactured at a lower cost than a wafer such as silicon.

  In the step of forming a predetermined via hole in the green sheet having the ceramic aggregate and the glass material, the thickness of the green sheet on the side on which the semiconductor element connection electrode is formed is opposite to the side on which the semiconductor element connection electrode is formed. Since the via hole is formed using a sheet thinner than the thickness of the green sheet, a through hole having a small area can be formed in the green sheet. Therefore, it becomes possible to form via electrodes with a narrower pitch.

  In addition, since at least one main surface of the fired body obtained by firing is lapped (planarized), and the external element connection electrode is formed on the other main surface by the thick film method, the external surface is relatively inexpensive. An element connection electrode can be formed.

  Further, when forming the capacitor, the lower conductive layer, the dielectric layer, and the upper conductive layer are sequentially formed, and then the layers are etched together, so that a thin film capacitor can be easily formed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an embodiment of an electronic component according to the present invention.

  In the electronic component according to the present invention, a substrate 10 and a capacitor 20 are provided on the substrate. The substrate 10 includes an insulator 11 and a via electrode 12 made of glass ceramics made of ceramic aggregate and glass material. The via electrodes 12 are exposed on both main surfaces of the substrate 10 and are wired inside the substrate. The capacitor 20 provided on the substrate is composed of a lower electrode film 21, an upper electrode film 22, and a dielectric thin film 23, and is formed between the plurality of via electrodes 12 exposed on the main surface. The lower electrode 21 and the upper electrode 22 are electrically connected to the via electrode 12 exposed on the main surface, and an electrode portion formed on the surface where the via electrode 12 is exposed is connected to the semiconductor element. The semiconductor element (not shown) functions as the electrode 30 and is bump-connected to the semiconductor element connection electrode 30. Furthermore, a protective film 40 is provided on the upper electrode of the capacitor.

  The internal structure (wiring configuration) of the substrate 12 will be described in detail with reference to FIGS.

FIG. 2 shows an external perspective view of the substrate according to the present invention. A plurality of via electrodes 12 are exposed on the substrate surface, and semiconductor elements are bump-connected to the electrodes via the semiconductor element connection electrodes. FIG. 3 is an exploded perspective view of the substrate according to the present invention. This illustrates a four-layer substrate. The first layer 101 has a plurality of via electrodes 121 exposed on the semiconductor element connection surface A. These via electrodes 121 are three-dimensionally connected to the fourth-layer via electrodes 124 via the wiring patterns 131, 132, and 133 of the first layer 101, the second layer 102, and the third layer 103 and the via electrodes 122 and 123. Wired to By making the internal wiring as shown in the figure, the pitch width of the via electrodes 124 can be doubled with respect to the via electrode pitch of the semiconductor connection surface in the external element connection surface B of the fourth layer. Also, the via electrode area is large.

  By adopting such a configuration, a semiconductor element having a narrow pitch electrode can be mounted and a large current can be passed through the external element. In addition, by increasing the via pitch on the external element connection surface side, it is possible to form the external terminal connection electrode using the thick film method, and it can be formed at a lower cost than when using the thin film method. It becomes. Furthermore, since the via area and via pitch can be increased in connection with an external element, a connection shift can be suppressed and the yield of the product is improved.

  The electronic component according to the present invention uses a low-temperature fired substrate made of a composite material of ceramic aggregate and glass material, and forms a via hole in each of these layers and forms a conductor pattern to obtain conduction between the front and back surfaces of the substrate. Configure the substrate. Therefore, it is cheaper than an electronic component using a substrate such as Si.

  Here, although the constituent material of the glass ceramic used for the insulator 11 is not particularly limited, the ceramic aggregate is, for example, alumina, magnesia, spinel, silica, mullite, forsterite, steatite, cordierite, zirconia, or the like. What is necessary is just to select suitably from at least 1 type. In particular, alumina is preferred for enhancing the substrate strength.

  As the glass material, for example, a general glass frit such as borosilicate glass, lead borosilicate glass, borosilicate barium glass, borosilicate strontium glass, or borosilicate zinc glass can be used. In particular, strontium borosilicate glass is preferable from the viewpoint of melting temperature and strength. The content of the glass material in the glass ceramic is 50% by volume or more, preferably 60 to 80% by volume. When the glass content is less than 50%, a glass-ceramic composite structure is hardly obtained, and strength, formability, workability, and the like are lowered. On the other hand, if the amount of glass increases too much, the strength decreases.

  Next, FIG. 4 shows a cross-sectional view of another embodiment of the electronic component according to the present invention.

  1 is the same as the electronic component according to the present invention shown in FIG. 1 except that the capacitor 20 provided on the substrate is configured immediately above the via electrode 12 exposed on the substrate.

  That is, in the electronic component according to another embodiment of the present invention, the substrate 10 and the capacitor 20 are provided on the substrate. The substrate 10 includes an insulator 11 and a via electrode 12 made of glass ceramics made of ceramic aggregate and glass material. The via electrodes 12 are exposed on both main surfaces of the substrate 10 and are wired inside the substrate. The capacitor 20 provided on the substrate includes a lower electrode film 21, an upper electrode film 22, and a dielectric thin film 23, at least one of which is formed immediately above the via electrode 12 exposed on the main surface. And the lower electrode film 21 are electrically connected. A protective film 40 is provided on the upper electrode film of the capacitor. Further, the upper electrode 22 has a semiconductor element connection electrode 30 connected to the semiconductor element formed on the via electrode 12 exposed on the main surface.

  Since the capacitor is provided immediately above the via electrode, the capacitor capacity can be increased. That is, as will be described later, since the capacitor can be designed efficiently, it has a sufficient electrode overlap area.

  Note that it is not necessary to form capacitors immediately above all the via electrodes, and some capacitors may be provided between the via electrodes.

  In addition, as in the embodiment shown in FIG. 1, the wiring pattern of the substrate has a larger pitch of the via electrode exposed on the external element connection surface than the pitch of the via electrode exposed on the surface on which the semiconductor element is mounted. The electrode area is also large. Therefore, a semiconductor element having an electrode with a narrow pitch can be mounted, and a large current can be passed through the external element connection electrode. In addition, by increasing the via pitch on the external element connection surface side, it is possible to form the external element connection electrode using the thick film method, and it can be formed at a lower cost than when using the thin film method. It becomes. Furthermore, since the via area and via pitch can be increased on the external element connection surface side, connection deviation can be suppressed and the yield of products is improved.

  Although an example in which a capacitor is formed on a substrate is shown here, elements such as a coil and a resistor may be formed in addition to these capacitors.

  Next, with reference to FIGS. 5-7, the manufacturing method of the electronic component which concerns on this invention is demonstrated in detail.

  FIG. 5 is a diagram showing a substrate stacking process according to the present invention. As shown in the figure, green sheets 511 to 514 having a desired thickness are prepared. The green sheet is formed by mixing ceramic powder and glass powder in a vehicle such as a binder and a solvent, kneading them to obtain a paste, and using this paste, for example, by a doctor blade method, an extrusion method, etc. A predetermined number of green sheets having a certain thickness are prepared. Here, the thickness of the green sheet can be appropriately selected depending on the diameter of a through hole to be described later. The aggregate ceramic powder is preferably about 1 to 8 μm, and the glass particle size is preferably about 0.1 to 5 μm. As the vehicle binder, an acrylic resin such as ethyl cellulose resin, polyvinyl butyral resin, methacrylic resin, butyl methacrylate, or the like can be used. As the solvent, ethyl cellulose, terpineol, butyl carbitol and the like can be used. Moreover, what is necessary is just to select suitably according to the objective from various other dispersing materials, an activator, a plasticizer, etc.

  Next, a predetermined number of through holes are formed at predetermined positions on each green sheet and filled with a conductive paste, and the conductive paste is printed to form a desired circuit pattern. The conductive paste is prepared by mixing a conductive material, a binder, a solvent, (glass frit) and the like. As the conductive material, metals such as Au, Ag, Cu, Pt, and Pd, and alloys thereof can be used. The content of the conductive material is preferably about 80 to 95% by weight.

  The green sheet 511 (first layer) has a mounting surface for a semiconductor element such as a CPU, and forms a number of through-hole vias 551 corresponding to the number of electrodes of the CPU. In the substrate according to another embodiment shown in FIG. 4, in addition to the number of CPU electrodes, a capacitor via hole is formed. On the other hand, the green sheet 514 (fourth layer) has an external terminal connection surface that is connected to an external element, and it is preferable to form fewer through holes 554 than the number of through holes formed in the green sheet 511. Further, a desired number of through holes 552 and 553 are also formed in the green sheets 512 and 513. A laser processing machine is used for forming the through hole. Here, when forming a through hole in the green sheet 511 having at least a semiconductor element mounting surface, it is formed by irradiating a laser beam from the opposite surface of the semiconductor element mounting surface. This is because in via formation by laser light, the via diameter on the side where light enters is large and the opposite side is small, so the shape of the cross section of the via becomes trapezoidal. This is because a caliber via electrode can be formed on the mounting surface of the semiconductor element.

Further, in order to form a smaller diameter through hole by laser light, it is preferable to make the sheet thinner. Therefore, as for the thickness of the sheet, the sheet 511 (and the sheet 512) serving as a layer on the CPU side uses a thin sheet of about 20 to 40 μm so that a through hole having a small diameter of about 10 to 60 μm can be easily opened, and vice versa. It is preferable that the sheet 514 (and the sheet 513) to be a layer constituting the surface is a thicker sheet having a thickness of about 80 to 160 μm and a through hole having a large diameter of about 100 to 150 μm is formed to withstand a large current.

  Thereafter, a necessary conductor pattern 530 is formed on each of the sheets by using a conductor paste using a screen printing method or the like. Simultaneously with the formation of the conductor pattern, the through holes are filled with a conductor paste to form via electrodes 521, 522, 523, and 524.

And each green sheet is laminated | stacked, 40-120 degreeC, 50-1000 kgf / cm < ² >.
Hot pressing is performed at a degree to obtain a laminated body in which the green sheets 511 to 514 are integrated. As a result, a three-dimensional wiring pattern is formed, and the number of through-holes on the external element connection surface can be made smaller than the number of through-holes on the semiconductor element mounting surface, thereby improving connection displacement with other elements, that is, manufacturing yield. Can be made.

  In addition, as described above, the via electrode has a trapezoidal cross section, but for the lamination of the green sheet, the via electrode surface having a smaller area becomes the semiconductor element mounting surface side, and the side on which the conductor paste is printed Laminate sequentially so that the opposite side is on. Since the conductor paste is filled there, a via electrode having a smaller diameter can be formed on the substrate surface with the above configuration.

  Note that although the method for forming a substrate by the sheet lamination method has been described here, the substrate may be formed by a printing method or the like.

  Next, the laminate is subjected to binder removal processing and then fired. In the binder removal treatment, heat treatment is performed at least at the decomposition temperature of the binder in order to remove the binder in the laminate by heat treatment. Furthermore, it is fired by holding at about 1000 ° C. or less, preferably about 800 to 1000 ° C., more preferably about 850 to 900 ° C. for about 5 to 15 minutes. As the firing atmosphere, firing can be performed in an oxidizing atmosphere or a neutral atmosphere. Specifically, it is fired in air, oxygen, nitrogen or the like or a mixed gas thereof. Among these, air is preferable because it is simple and inexpensive. However, when Cu is used as the conductive material, it is preferably fired in an inert gas.

  In addition, about the baking process, you may apply the baking method (non-shrinkage baking) which shrinks only a vertical direction, without performing the shrinkage | contraction of the plane direction of a board | substrate.

  FIG. 6 is a diagram showing a processing step of the substrate after baking.

  FIG. 6A shows the substrate after lamination and firing. Since the substrate 100 after baking is generally warped by the baking process, it is necessary to perform lapping (planarization) processing on both surfaces of the substrate, that is, substrate grinding to perform substrate planarization. FIG. 6B is a view showing a cross section of the substrate after the lapping process. The portions corresponding to the first layer and the fourth layer are ground to produce the substrate 10 having a predetermined thickness. Further, in order to form an element such as a thin film capacitor on the surface of the substrate, the surface of the substrate on which the thin film capacitor or the like is to be formed is subjected to a mirroring (polishing) process after the planarization process. The polishing process is performed using CMP (chemical mechanical polishing) or the like.

When forming an electrode (external element connection electrode 50) on the external element connection side of the substrate 10 after lapping as shown in FIG. 6C, a conductor paste is applied by screen printing or the like after the lapping process. It is also possible to form the external element connection electrode 50 by using a sintered electrode by printing and baking. It is preferable that the mirror finishing process at that time is performed after the external terminal connection electrode 50 is formed.

  Subsequently, a capacitor is formed on the substrate 10. FIG. 7 is a diagram showing a process for forming the thin film capacitor according to the embodiment of FIG. 1 on the substrate obtained by the above process.

First, a conductor layer 210 for a capacitor lower electrode film is formed on the mirror-finished substrate 10 surface (FIG. 7A). The conductor layer 210 is formed by a thin film method (vapor phase method) such as a sputtering method. The conductor material of the conductor layer 210 is not particularly limited as long as it has conductivity. For example, metals such as Au, Pt, Ag, Ir, Ru, Co, Ni, Fe, Cu, Al or alloys thereof, semiconductors such as Si, GaAs, GaP, InP, SiC, ITO, ZnO, SnO _2, etc. Conductive metal oxides can be used. However, since the heat treatment is performed in an oxidizing atmosphere when forming the dielectric layer, at least the lower conductor is preferably a metal such as oxidation-resistant gold or platinum.

Then, using the photolithography technique, the required patterning is performed and the lower electrode film | membrane 21 is formed (the figure (b)). Thereafter, a dielectric layer 230 is formed by using a solution method such as a MOD (metal organic decomposition) method or a vapor phase method such as a sputtering method ((c) in the figure). Then, necessary dielectric patterning is performed to form the dielectric thin film 23 (FIG. 4D). The dielectric material of the dielectric thin film is not particularly limited, and for example, Ba _x Sr _1-X TiO ₃ , Bi layered compound or BaTiO ₃ , SrTiO ₃ , a compound in which other metals are added or substituted, or the like is used. be able to.

  Further, a conductor layer 220 serving as an upper conductor film is formed on the dielectric thin film 23 by a thin film method (vapor phase method) such as a sputtering method (FIG. (E)), and it is necessary to use a photolithography technique. Patterning is performed to form the upper electrode film 22 (figure (f)), and finally a passivation layer (protective layer) 400 is formed (figure (g)), and necessary patterning is performed using photolithography technology. Then, a passivation film (protective film) 40 for protection is formed ((h) in the figure). The electrode portion exposed by etching the passivation layer 400 becomes the semiconductor element connection electrode 30 with the semiconductor element mounted on the substrate.

  Through the above steps, an electronic component having a plurality of capacitors 20 formed on the substrate 10 can be obtained ((h) in the figure).

  FIG. 8 is a diagram showing a process for forming a thin film capacitor according to another embodiment according to FIG. 4 on a substrate.

First, as shown in FIG. 8, a lower conductive layer 210 that becomes a lower electrode film, a dielectric layer 230 that becomes a dielectric thin film, an upper electrode film, The upper conductive layers 220 are sequentially formed (FIG. 8A). Next, the conductive layers 210 and 220 and the dielectric layer 230 are collectively etched into a predetermined pattern (FIG. 5B). At that time, the lower electrode film 21 is formed immediately above the via electrode 12 exposed on the surface, and is patterned so as to obtain electrical connection. Etching is preferably performed by plasma of a reactive gas such as ICP, whereby a plurality of capacitors can be formed at a time. In addition, when the lower electrode film, the dielectric film, and the upper electrode film are formed by patterning each film, the design is made in consideration of the patterning deviation, and the capacitance of the capacitor is slightly reduced. However, since each layer is formed in a lump, it can be designed efficiently without considering the deviation, and the maximum electrode overlap area can be taken, so that a large capacitor capacity can be obtained.
Note that the formation method and materials of each layer are the same as those in the first embodiment.

Subsequently, a passivation layer 400 is formed (FIG. 3C), a passivation film 40 is formed using a photolithography technique (FIG. 4D), and further, a semiconductor element connection electrode 30 connected to the semiconductor element. Is formed ((e) in the figure).

  In this manufacturing process, the patterning process by etching can be reduced as compared with the manufacturing process of the first embodiment. In general, the patterning process uses a photolithographic technique to form an etching resist pattern (photoresist pattern), and then performs etching using plasma of a reactive gas such as ICP, which requires manufacturing time, manufacturing capability, manufacturing cost, and the like. Therefore, the fact that it can be reduced even once is very significant in manufacturing.

  Furthermore, since the conductor film and dielectric film of a capacitor generally composed of a thin film are formed with a very thin thickness of about 100 nm, it is extremely difficult to stop etching for each film, and a large substrate at the wafer level during mass production Therefore, it becomes difficult to control the etching depth uniformly at the wafer level. However, since the manufacturing method according to the other embodiment can be formed in a lump, there is no concern.

  Further, since there is no deviation between the upper electrode and the lower electrode, the capacitor capacity can be obtained efficiently. In addition, since the electrode for mounting the semiconductor element is formed in the last step of the manufacturing process according to the second embodiment, the area of the electrode for mounting the semiconductor element can be set regardless of the area occupied by the capacitor. Electrodes with high strength can be designed.

  9 and 10 are cross-sectional views of a semiconductor device in which the electronic component according to the present invention is used as an interposer between a CPU and its package.

  FIG. 9 is a cross-sectional view of the electronic component according to the present invention mounted on a CPU package as an interposer. In the figure, an electronic component 1 according to the present invention as an interposer is provided between a CPU package 7 and a CPU 8 formed of resin via bumps 101 and 801 and mounted on the CPU package 7. Here, the connection between the electrode pin 701 on the CPU package 7 side and the electronic component (interposer) 1 is made by a bump formed on the electronic component 1 and the wiring conductor 702 in the CPU package 7 when the CPU package 7 is manufactured. Alternatively, it may be directly connected to the external terminal connection electrode of the electronic component by dry or wet plating performed in the conductor film forming step for forming the wiring conductor pattern in the CPU package 7.

  Further, the CPU 8 and the electronic component (interposer) 1 are connected via bumps 801. The bump 801 may be formed on the CPU die side or may be formed on the external terminal connection electrode of the electronic component.

  FIG. 10 is a sectional view of the electronic component according to the present invention embedded in a CPU package as an interposer. 9 is the same as that of FIG. 9 except that the interposer is embedded in the CPU package. That is, the electronic component 1 according to the present invention, which is an interposer, is embedded in a CPU package 7 formed of resin with a surface on the side connected to the CPU 8 exposed. Here, the connection between the electrode pin 701 on the CPU package 7 side and the electronic component 1 may be made by connecting the wiring conductor 702 in the CPU package with a bump formed on the electronic component 1 when the CPU package 7 is manufactured. Or you may connect directly to the external terminal connection electrode of an electronic component by the dry type or wet plating etc. which are performed at the conductor film formation process for forming the wiring conductor pattern in CPU package 7. FIG.

Further, the CPU 8 and the electronic component 1 are connected via bumps 801. The bump 801 may be formed on the CPU die side or may be formed on the external terminal connection electrode of the electronic component.

  By embedding the interposer in the CPU package, it is possible to obtain a low-profile device and a stable connection between the interposer and the package.

  The electronic component according to the present invention is a multilayer wiring board on which electric elements such as capacitors, coils, resistors, etc. can be formed, and in particular, a decoupling capacitor is formed and can be used as an interposer on which a semiconductor element can be mounted.

It is sectional drawing which shows one Embodiment of the electronic component which concerns on this invention. The external appearance perspective view of the board | substrate which concerns on this invention is shown. The disassembled perspective view of the board | substrate which concerns on this invention is shown. Sectional drawing of other embodiment of the electronic component which concerns on this invention is shown. It is a figure which shows the lamination process of the board | substrate which concerns on this invention. It is a figure which shows the process process of the board | substrate after baking. It is a figure which shows the process at the time of forming the thin film capacitor which concerns on embodiment of FIG. 1 on a board | substrate. It is a figure which shows the process at the time of forming the thin film capacitor which concerns on other embodiment which concerns on FIG. 4 on a board | substrate. It is sectional drawing of the state which mounted the electronic component (interposer) based on this invention on CPU package. It is sectional drawing of the state which embed | buried the electronic component (interposer) which concerns on this invention in CPU package.

Explanation of symbols

1 Electronic component (interposer)
DESCRIPTION OF SYMBOLS 10 Substrate 11 Insulator 12, 121, 122, 123, 124, 521, 522, 523, 524 Via electrode 100 Laminated body 101 First layer 102 Second layer 103 Third layer 104 Fourth layer 131, 132, 133, 530 Electrode pattern 20 Capacitor 21 Lower electrode film 22 Dielectric film 23 Upper electrode film 210, 220 Conductive layer 230 Dielectric layer 30 Semiconductor element connection electrode 40 Passivation film 400 Passivation layer 50 External terminal connection electrode 511, 512, 513, 514 Green sheet 551, 552, 553, 554 Through hole

Claims (11)

  An electronic component connected to a semiconductor element and having at least a substrate and a capacitor, wherein the capacitor is provided on at least one main surface of the substrate, and the substrate is made of glass ceramics having a ceramic aggregate and a glass material And a plurality of via electrodes formed inside the insulator and exposed on both main surfaces of the substrate.   2. The electronic component according to claim 1, wherein the number of via electrodes exposed on one main surface is different from the number of via electrodes exposed on the other main surface of the via electrode of the substrate.   3. The via electrode of the substrate according to claim 1 or 2, wherein the via electrode exposed on the other main surface is larger than the area of the via electrode exposed on the main surface connected to the semiconductor element. Electronic component in any one.   The said board | substrate consists of a multilayer board | substrate, and the thickness of the layer which has a main surface connected to a semiconductor element was made thinner than the thickness of the layer which has the other main surface. The electronic component described.   5. The electronic component according to claim 1, wherein the capacitor has at least a lower electrode film, a dielectric thin film, and an upper electrode film, and at least the dielectric thin film is formed by a thin film process. .   6. The electronic component according to claim 1, wherein at least one of the capacitors is formed immediately above a via electrode exposed on at least one main surface of the substrate.   7. A semiconductor device, wherein a semiconductor element is connected on one main surface of the electronic component according to claim 1, and a CPU package is connected to a main surface opposite to the connection surface. .   A step of forming a predetermined via hole in a green sheet having a ceramic aggregate and a glass material, a step of filling the via hole with an electrode, a step of forming a predetermined electrode pattern on the surface of the green sheet, a predetermined via electrode and an electrode A step of laminating a green sheet on which a pattern is formed, a step of firing a laminate obtained by laminating, and polishing the at least one main surface of the fired body obtained by firing, on the processed surface A method of manufacturing an electronic component, comprising: a step of forming a capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are sequentially laminated; and a step of forming a semiconductor element connection electrode to which a semiconductor element can be connected. The dielectric thin film is formed by a thin film forming process.   In the method of manufacturing the electronic component, the step of forming a predetermined via hole in the green sheet having the ceramic aggregate and the glass material includes the step of forming the thickness of the green sheet on the side on which the semiconductor element connection electrode is formed. 9. The method of manufacturing an electronic component according to claim 8, wherein the via hole is formed using a sheet thinner than the thickness of the green sheet on the side opposite to the electrode forming side.   A method for manufacturing the electronic component, comprising: a step of forming an external element connection electrode on the other main surface by a thick film method after at least one main surface of the fired body obtained by firing is lapped. 10. A method of manufacturing an electronic component according to claim 8, wherein In the method of manufacturing the electronic component, the step of forming the capacitor includes forming a capacitor by sequentially forming a lower conductive layer, a dielectric layer, and an upper conductive layer, and then etching each layer at once. The manufacturing method of the electronic component in any one of Claims 8-10.