JP2006216709A - Multilayered wiring board with built-in multilayered electronic component, and multilayered electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayered wiring board with a built-in multilayered electronic component having a high performance and a high reliability, and also to provide the multilayered electronic component. <P>SOLUTION: The multilayered wiring board 10 incorporates the multilayered electronic component 13. The multilayered electronic component 13 comprises an element assembly consisting of a laminate 13B made by stacking a plurality of dielectric layers 13A, internal electrodes 13C existing between the dielectric layers 13A, and an external terminal electrode 13D formed on the connection surface of the element assembly so as to be connected to the inner electrodes 13C. The inner electrodes 13C are so formed as to substantially have no margin with the non-connection surface. The multilayered wiring board 10 comprises an element assembly consisting of a laminate 11 made by stacking a plurality of dielectric layers 11A, and predetermined wiring patterns 12 existing between the dielectric layers 11A. The non-connection surface of the multilayered electronic component 13 faces the dielectric layers 11A of the multilayered wiring board 10. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer wiring board incorporating a multilayer electronic component and a multilayer electronic component.

  As a conventional multilayer wiring board of this type, for example, techniques described in Patent Document 1 and Patent Document 2 are known. In the technique described in Patent Document 1, spaces formed by recesses or through holes are provided in a multilayer ceramic substrate, and multilayer electronic components such as multilayer capacitors and multilayer inductors are incorporated in these spaces to improve the flatness of the substrate. It is an enhanced one.

  Further, the technique described in Patent Document 2 relates to a multilayer ceramic substrate having a built-in multilayer electronic component, similar to the technique described in Patent Document 1. In this technology, a sintered body plate obtained by pre-baking is incorporated in an unsintered composite laminate, and constraining layers containing a hardly sinterable material are arranged on both upper and lower sides of the unsintered composite laminate. A multilayer ceramic substrate with electronic components built in is produced using a non-shrinking method that suppresses the shrinkage of the substrate in the planar direction by the action of the layers.

  A conventional multilayer wiring board having a built-in multilayer electronic component incorporates an existing multilayer electronic component. As an existing multilayer electronic component, for example, the multilayer multilayer ceramic capacitor disclosed in Patent Document 3 and the multilayer ceramic electronic component described in Patent Document 4 are known. These multilayer electronic components all relate to ceramic capacitors. Each of these ceramic capacitors has a margin portion such as a side margin around the internal electrode, and the reliability of the ceramic capacitor is ensured by this margin portion.

  That is, as shown in FIGS. 11A and 11B, the multilayer ceramic capacitor includes a multilayer body 1 composed of a plurality of ceramic layers 1A, and an internal electrode 2 interposed in the multilayer body 1 in a plurality of upper and lower layers. And external electrodes 3 provided on both end faces of the laminate 1 and connected to the internal electrodes 2 exposed at both end faces. As shown in FIG. 2B, the ceramic layer 1A having the internal electrode 2 is provided with side margin portions 1B having a predetermined width G1 on both sides in the width direction, and upper and lower ceramics are provided in these side margin portions 1B. Layers 1 </ b> A and 1 </ b> A are brought into close contact with each other to prevent delamination and prevent exposure from the side surface of internal electrode 2. If the internal electrode 2 is exposed from the side surface of the component, the moisture resistance is poor and the reliability is lowered. Therefore, it is necessary to provide the side margin 1B as described above. Further, as shown in FIG. 5A, in order to ensure reliability also in the thickness direction of the laminated body 1, a predetermined dimension G2 is also provided outside the uppermost internal electrode 2 and the lowermost internal electrode 2 respectively. A margin portion is provided.

JP-A-61-288498 Japanese Patent Laid-Open No. 2002-084067 JP 09-066944 A JP 2001-035738 A

  However, since the multilayer electronic component such as the conventional multilayer ceramic capacitor shown in FIG. 11 is provided with the side margin portion G1 and the upper and lower margin portions G2 in order to ensure reliability, the multilayer electronic component is downsized. Then, since it is necessary to secure the side margin portion, the requirements for the printing accuracy and cutting accuracy of the internal electrode 2 are increased. On the other hand, if the side margin portion is increased to meet this requirement, the width of the internal electrode becomes narrower and the capacity increases. Will be hindered. In addition, since the upper and lower margin portions are provided separately from the substantial capacitor portion of the internal electrode so as to ensure reliability, it hinders a reduction in height, and when built in a multilayer wiring board, Unevenness is generated on the surface of the substrate, and the surface mountability is greatly reduced. In the future, as the performance of multilayer electronic components further increases, it becomes more difficult to incorporate such multilayer electronic components in a multilayer wiring board.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer wiring board and a multilayer electronic component incorporating a multilayer electronic component having high performance and high reliability.

  The multilayer wiring board according to claim 1 of the present invention is a multilayer wiring board having a built-in multilayer electronic component, and the multilayer electronic component is an element body composed of a multilayer body in which a plurality of dielectric layers are stacked. And an internal electrode interposed between the dielectric layers, and an external terminal electrode provided on at least one side surface of the element body so as to be connected to the internal electrode, The multilayer wiring board is formed so as to have substantially no margin between the other side surfaces of the element body, and the multilayer wiring board includes an element body composed of a laminated body in which a plurality of dielectric layers are laminated, and the laminated body. A predetermined wiring pattern provided inside the body, wherein the external terminal electrode of the multilayer electronic component is connected to the wiring pattern of the multilayer wiring board, and the multilayer electronic component The other side surface of the element body of the multilayer wiring board And it is characterized in that it is collector layer and the counter.

  A multilayer wiring board according to a second aspect of the present invention is the capacitor according to the first aspect, wherein the multilayer electronic component includes a capacitor pattern formed over a plurality of layers as the internal electrode. It is a built-in component.

  According to a third aspect of the present invention, in the multilayer wiring board according to the second aspect, the multilayer electronic component is an electronic component with a built-in inductor having a coil pattern as the internal electrode. It is what.

  The multilayer wiring board according to claim 4 of the present invention is the multilayer wiring board according to any one of claims 1 to 3, wherein the wiring pattern of the multilayer wiring board includes a via-hole conductor, The external terminal electrode of the type electronic component is connected to the via-hole conductor, and a step portion is formed in the via-hole conductor in the connected state.

  A multilayer wiring board according to claim 5 of the present invention is the multilayer wiring board according to claim 4, wherein the multilayer wiring board includes a first connection conductor extending in the stacking direction of the dielectric layers as the wiring pattern. A second connection conductor extending to the opposite side of the first connection conductor, and the external terminal electrode of the multilayer electronic component is connected to the first connection conductor and the second connection conductor, respectively. It is a thing of any one of Claims 1-3 characterized by the above-mentioned.

  A multilayer wiring board according to a sixth aspect of the present invention is the invention according to any one of the first to fifth aspects, wherein the other side surface of the multilayer electronic component and the multilayer wiring board are An air gap is interposed between the dielectric layer and the dielectric layer.

  A multilayer wiring board according to claim 7 of the present invention is the invention according to any one of claims 1 to 5, wherein the other side surface of the multilayer electronic component and the multilayer wiring board are Ceramic powder is interposed between the dielectric layers.

  The multilayer wiring board according to claim 8 of the present invention is the multilayer electronic component according to any one of claims 1 to 7, wherein the multilayer electronic component includes a plurality of dielectric ceramic layers. It is a multilayer ceramic electronic component having a laminated body as a base body.

  The multilayer wiring board according to claim 9 of the present invention is the multilayer wiring board according to any one of claims 1 to 8, wherein the multilayer wiring board is formed by laminating a plurality of dielectric ceramic layers. It is a ceramic multilayer substrate which uses the laminated body as a base body.

  According to a tenth aspect of the present invention, in the multilayer wiring substrate according to the ninth aspect, the dielectric ceramic layer is a low-temperature sintered ceramic layer.

  A multilayer electronic component according to an eleventh aspect of the present invention includes an element body made of a laminate in which a plurality of dielectric layers are laminated, an internal electrode interposed between the dielectric layers, and the internal electrode. An external terminal electrode provided on at least one side surface of the element body so as to be connected to the element body, and there is substantially no margin between the other side surface of the element body and the internal electrode. It is what.

  According to the first to eleventh aspects of the present invention, it is possible to provide a multilayer wiring board and a multilayer electronic component incorporating a multilayer electronic component having high performance and high reliability.

  Hereinafter, the present invention will be described based on the embodiment shown in FIGS. 1A to 1C are views showing an embodiment of a multilayer wiring board according to the present invention, respectively, FIG. 1A is a sectional view showing the whole, and FIG. 1B is a main part of FIG. (C) is a plan view of (b), (a) and (b) of FIG. 2 are views showing the multilayer electronic component shown in FIG. FIG. 3B is a plan view showing the main part thereof, FIG. 3A is a plan view showing the main part of another type of multilayer electronic component shown in FIG. 1, and FIG. FIG. 4 is a plan view showing a main part of a conventional multilayer electronic component shown in FIG. 4A, FIG. 4 is a perspective view showing a process of manufacturing the multilayer electronic component shown in FIG. 2, and FIG. (C) is process drawing which shows the principal part of the manufacturing process of the multilayer wiring board shown in FIG. 1, respectively, (a) is sectional drawing which shows a dielectric material green sheet, (b) is the dielectric material green sheet shown in (a). FIG. 6C is a cross-sectional view showing a state in which the multilayer electronic component is placed, FIG. 6C is a cross-sectional view showing a state in which the dielectric green sheet shown in FIG. (C) is a process drawing following the manufacturing process shown in FIG. 5, (a) is a cross-sectional view showing the pressure-bonded body before firing, (b) is a cross-sectional view showing the multilayer wiring board after firing, and (c) is a cross-sectional view. Sectional drawing which shows the state which mounted the multilayer electronic component in the multilayer wiring board shown to (b), (a)-(c) of FIG. 7 is a figure which shows other embodiment of the multilayer wiring board of this invention, (A) is a cross-sectional view showing the whole, (b) is a cross-sectional view showing an enlarged main part of (a), (c) is a main part cross-sectional view showing further enlarged (b), FIG. (A), (b) is process drawing which shows the principal part of the manufacturing process of the multilayer wiring board shown in FIG. 7, respectively, (a) incorporates a multilayer electronic component. FIG. 9B is a sectional view showing a state in which a multilayer electronic component is built in, FIG. 9 is a sectional view showing a main part of still another embodiment of the multilayer wiring board of the present invention, and FIG. These are sectional drawings which show the principal part of further another embodiment of the multilayer wiring board of the present invention.

First Embodiment A multilayer wiring board 10 according to the present embodiment includes, for example, as shown in FIG. 1A, an element body composed of a laminate 11 in which a plurality of dielectric layers 11A are laminated, A wiring pattern 12 formed in an interface between the upper and lower dielectric layers 11A and a via hole penetrating the dielectric layer 11A, and a laminate provided at the interface between the upper and lower dielectric layers 11A and electrically connected to the wiring pattern 12 And a mold electronic component 13. Further, surface electrodes 14 and 14 are formed on both main surfaces (upper and lower surfaces) of the laminate 11, respectively.

  A plurality of surface mount components 20 are mounted on the upper surface of the multilayer body 11 via the surface electrodes 14. As the surface mount component 20, active elements such as silicon semiconductor elements and gallium arsenide semiconductor elements, passive elements such as capacitors, inductors, resistors, etc. are bonded via solder or conductive resin, or bonding wires such as Au, Al, Cu, etc. Is electrically connected to the surface electrode 14 on the upper surface of the laminate 11. The multilayer electronic component 13 and the surface mount component 20 are electrically connected to each other via the surface electrode 14 and the wiring pattern 12 as necessary. The multilayer wiring board 10 can be mounted on a mounting board such as a mother board via the lower surface electrode 14.

  Thus, the material of the dielectric layer 11A constituting the multilayer body 11 is not particularly limited, but can be formed of, for example, a ceramic material or a curable resin material such as a thermosetting resin or a photocurable resin. In order to increase the density of the wiring pattern 12, a ceramic material can be preferably used as the material of the dielectric layer 11A.

As the ceramic material, for example, a low temperature co-fired ceramic (LTCC) material can be used. The low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or less and can be simultaneously fired with silver, copper, or the like having a small specific resistance. Specifically, as the low-temperature sintered ceramic material, a glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as alumina, zirconia, magnesia, and forsterite, ZnO—MgO—Al ₂ O ₃ — Crystallized glass-based LTCC material using crystallized glass of SiO ₂ , BaO—Al ₂ O ₃ —SiO ₂ ceramic powder, Al ₂ O ₃ —CaO—SiO ₂ —MgO—B ₂ O ₃ ceramic powder, etc. Non-glass type LTCC materials using By using a low-temperature sintered ceramic material as the material of the dielectric layer 11A, a metal having a low resistance and a low melting point, such as Ag or Cu, can be used for both the wiring pattern 12 and the surface electrode 14. 12 can be co-fired at a low temperature of 1050 ° C. or lower.

  In addition, a high temperature co-fired ceramic (HTCC) material can be used as the ceramic material. Examples of the high-temperature sintered ceramic material include alumina, aluminum nitride, mullite, and other materials added with a sintering aid such as glass and sintered at 1100 ° C. or higher. At this time, as the wiring pattern 12, a metal selected from molybdenum, platinum, palladium, tungsten, nickel, and an alloy containing these is used.

  In the present embodiment, a case where the dielectric layer 11A is formed of a low-temperature sintered ceramic material will be described. Therefore, hereinafter, the dielectric layer 11A will be described as the dielectric ceramic layer 11A. The laminated body 11 in this embodiment has the wiring pattern 12 formed in the inside, and the surface electrode 14 formed in the upper and lower surfaces as shown to (a) of FIG. The wiring pattern 12 is formed by arranging in a predetermined pattern so as to connect the in-plane conductor 12A formed in a predetermined pattern along the interface between the upper and lower dielectric ceramic layers 11A and the upper and lower in-plane conductors 12A. And via-hole conductor 12B.

  As shown in FIGS. 2A and 2B, the multilayer electronic component 13 of the present embodiment includes an element body composed of a multilayer body 13B in which a plurality of dielectric layers 13A are laminated, and a dielectric layer 13A. It has internal electrodes 13C interposed therebetween, and external terminal electrodes 13D provided on both side surfaces (both end surfaces) of the laminated body 13B so as to be connected to the internal electrodes 13C. Hereinafter, the side surface of the multilayer body 13B provided with the external terminal electrode 13D will be described as a connection surface, and all other side surfaces not provided with the external terminal electrode 13D will be described as non-connection surfaces. The external terminal electrode 13D is formed to be folded back and forth from the connection surface of the multilayer body 13B, but it is preferable that the folded width is small. Further, a part of the internal electrode 13C exposed on the connection surface may be used as the external terminal electrode.

  The multilayer electronic component 13 is not particularly limited, but for example, a ceramic sintered body fired at 1200 ° C. or higher such as barium titanate or ferrite, for example, a capacitor, an inductor, a filter, a balun, a coupler, Examples thereof include multilayer electronic components such as resonators. These multilayer electronic components 13 can be used by appropriately selecting one or a plurality according to the purpose and combining them. Since the dielectric layer 13A of the multilayer electronic component 13 is formed of a ceramic material, the dielectric layer 13A will be described as a dielectric ceramic layer 13A below.

  The feature of the multilayer electronic component 13 in this embodiment is that there is no margin around the internal electrode 13C. That is, the internal electrode 13C extends from one connection surface side of the multilayer body 11B of the dielectric ceramic layer 13A to the vicinity of the other connection surface side. The width of the internal electrode 13C is formed to be substantially the same as the width of the dielectric layer 13B, and there is substantially a side margin between the side edges of the internal electrode 13C and the side edges of the dielectric ceramic layer 13A. No. Since the area of the internal electrode 13C can be greatly expanded as compared with the conventional case by eliminating the side margin portion in this way, the performance of the multilayer electronic component 13 is promoted, in particular, the increase in capacity, and the size is reduced. , Can promote low profile. Due to the downsizing of the multilayer electronic component 13, particularly the low profile, even if the multilayer electronic component 13 is built in the multilayer wiring substrate 10, unevenness is hardly generated on the substrate surface, and the surface mountability of the surface mount component 20 is improved. be able to. In addition, by eliminating the side margin portion, it is possible to eliminate the influence of printing misalignment of the internal electrode 13C, cut misalignment to individual parts, and misalignment, thereby improving workability and eventually improving the yield. be able to.

  In FIG. 2A, the dielectric ceramic layer 13A is present on the uppermost internal electrode 13C in the multilayer body 13B. The dielectric ceramic layer 13A has a margin portion as in the prior art. It is not necessary to make it large, the margin can be made as small (thin) as possible, and if necessary, the uppermost dielectric ceramic layer 13A may be omitted to expose the internal electrode 13C. The dielectric layer 13 </ b> C below the lowermost internal electrode 13 </ b> C can be similarly formed. By making the upper and lower margin portions small or eliminated, it is possible to realize a further reduction in the height of the multilayer electronic component 13 in combination with the absence of the side margin portions.

  Even if the side margin portion and the upper and lower margin portions are not present and the internal electrode 13C is exposed on all the non-connection surfaces of the multilayer body 13B, the multilayer electronic component 13 is incorporated in the multilayer wiring board 10 and the non-connection surface thereof. Are opposed to and in close contact with the dielectric ceramic layer 11A of the multilayer wiring board 10, so that the dielectric ceramic layer 11A shoulders the margin of the multilayer electronic component 13 and the dielectric ceramic layer 13A and the internal electrode 13C. And the reliability of the multilayer electronic component 13 in the humidity can be ensured.

  By eliminating the margin around the internal electrode 13C in this way, the area of the internal electrode 13C can be increased and the number of stacked internal electrodes 13C can be increased. Therefore, the multilayer electronic component 13 is formed of a multilayer capacitor. In some cases, the capacitance can be greatly increased even if it is the same size as the conventional multilayer capacitor, and if the capacitance is the same as that of the conventional multilayer capacitor, it can be significantly reduced in size and height. it can. Further, when the multilayer electronic component 13 is a multilayer inductor as shown in FIG. 3A, the dielectric ceramic layer has the same size as the conventional multilayer inductor shown in FIG. The number of turns of the internal electrode 13C ′ on 13A ′ can be increased, the number of stacked internal electrodes 13C ′ can be increased, and the inductance value can be significantly increased. Further, if the inductance value is the same as that of the conventional multilayer inductor, the multilayer inductor can be remarkably reduced in size and height. Therefore, the multilayer electronic component 13 of the present embodiment can be remarkably reduced in size and height as compared with the conventional one, and the flatness of the multilayer wiring board 10 can be significantly improved.

  As shown in FIG. 1A, the multilayer body 11 has a wiring pattern 12 formed therein, and surface electrodes 14 and 14 formed on both upper and lower surfaces thereof. The wiring pattern 12 has a predetermined pattern so as to connect the in-plane conductors 12A formed in a predetermined pattern along the interface between the upper and lower dielectric ceramic layers 11A and the upper and lower in-plane conductors 12A. For example, a via hole conductor 12B formed in a columnar shape.

  As shown in FIG. 1A, the multilayer electronic component 13 is disposed at the interface between the upper and lower dielectric ceramic layers 11A and 11A, and the external terminal electrode 13D is at least of the upper and lower end faces of the via-hole conductor 12B. It is directly connected to one of the end faces. The multilayer electronic component 13 is connected to the via-hole conductor 12B with a plurality of connection patterns. That is, in the present embodiment, the multilayer electronic component 13 is connected to the via-hole conductor 12B with three connection patterns of X, Y, and Z as shown by the circled portion in FIG. .

  First, the X connection pattern will be described with reference to FIGS. 1B and 1C. A pair of left and right external terminal electrodes 13D of the multilayer electronic component 13 are formed on the left and right dielectric ceramic layers 11A that are in contact with the lower surface of the multilayer electronic component 13, as shown in FIGS. The pair of via-hole conductors 12B and 12B are connected. Step portions 12C and 12C are formed on the upper end surfaces of the pair of via-hole conductors 12B and 12B so as to face each other, and the external terminal electrodes 13D and 13D are in close contact with the step portions 12C and 12C. It is connected. The step portion 12C is formed so as to cut out half of the upper end surface of the via-hole conductor 12B, and has a L-shaped cross section. Accordingly, the external terminal electrodes 13D and 13D of the multilayer electronic component 13 are connected to the via hole conductors 12B via the two surfaces of the step wall portions 12C and 12C, which are substantially opposite to each other at the lower end portions of the stepped portions 12C and 12C. , 12B. That is, the rectangular multilayer electronic component 13 is connected to the via-hole conductor 12B on at least two sides of the end surface and the bottom surface. The multilayer electronic component 13 of this embodiment is formed as a multilayer ceramic capacitor.

  In the Y connection pattern, the multilayer electronic component 13 has a stepped portion 12C formed in a via-hole conductor 12B in which one external terminal electrode 13D (on the right in the figure) is formed in the lower dielectric ceramic layer 11A. The other external terminal electrode 13D (left side in the figure) is connected by forming a via hole conductor 12B step 12C formed in the upper dielectric ceramic layer 11A. The right via-hole conductor 12B is formed in the same form as the right via-hole conductor 12B shown in FIG. The left via hole conductor 12B has a step 12C formed on the lower end surface of the via hole conductor 12B. The step portions 12C and 12C of the left and right via-hole conductors 12B and 12B are in a positional relationship rotated by 180 ° with respect to the multilayer electronic component 13 respectively. In the case of such a connection pattern, the distance between the via hole conductors 12B connected to the respective external terminal electrodes 13D is increased, so that the pitch of the via hole conductors 12B can be reduced, that is, the multilayer electronic component 13 can be reduced in size. In addition, sufficient isolation between the via-hole conductors 12B and 12B can be ensured.

  In the Z connection pattern, the multilayer electronic component 13 has a stepped portion 12C formed in the via-hole conductor 12B in which one external terminal electrode 13D (on the right in the figure) is formed in the lower dielectric ceramic layer 11A. The upper and lower stepped portions 12C and 12C of the via-hole conductors 12B and 12B in which the other external terminal electrode 13D is continuously formed on the upper and lower dielectric ceramic layers 11A and 11A. It is connected in a state of being sandwiched between. The right via-hole conductor 12B is formed in the same form as the right via-hole conductor 12B in the X connection pattern. Of the left via hole conductors 12B and 12B, the lower via hole conductor 12B is formed in the same form as the left via hole conductor 12B in the X connection pattern, and the upper via hole conductor 12C has the Y connection pattern. It is formed in the same form as the left via-hole conductor 12C. In the case of such a connection pattern, the connection reliability between the external terminal electrode 13D and the via-hole conductor 12B can be further improved.

  The via-hole conductor 12B to which the multilayer electronic component 13 is connected is not limited to the form shown in FIGS. 1A to 1C, and is formed over the entire length in the width direction of the external terminal electrode 13D with an oval cross-sectional shape. Or may be formed by dividing into a plurality of sections smaller than those shown in FIG.

  In the case shown in FIG. 1A, a plurality of multilayer electronic components 13 are arranged side by side on the same dielectric ceramic layer 11A of the multilayer wiring board 10, but the multilayer electronic components 13 may be arranged as needed. Thus, it can be arranged at any location on the interface between the upper and lower dielectric ceramic layers 11A and 11A of the multilayer wiring board 10. Further, a plurality of stacked electronic components 13 may be disposed so as to be stacked over a plurality of different upper and lower interfaces. Each of the plurality of multilayer electronic components 13 is connected in series and / or in parallel via the stepped portion 12C of the via-hole conductor 12B according to the purpose, so that the multi-layer wiring board 10 can be multifunctional and high performance. Can be realized.

  The surface mount component 20 is used in combination with the multilayer electronic component 13 as shown in FIG. The multilayer electronic component 13 and the surface mount component 20 are connected to each other via the surface electrode 14 and the wiring pattern 12 as necessary. When the surface-mounted component 20 is a component that is easily affected by power supply noise such as an integrated circuit, by connecting a capacitor as the multilayer electronic component 13 in the vicinity immediately below the power supply terminal and the ground terminal of the surface-mounted component 20, High efficiency such as stable supply of power supply voltage and prevention of output oscillation without being restricted by terminal arrangement of surface mount component 20 such as an integrated circuit and without separately mounting multilayer electronic components (capacitors) on the motherboard Noise removal.

Next, a method for manufacturing the multilayer wiring board 10 will be described with reference to FIGS.
In the present embodiment, a case where the multilayer wiring board 10 is manufactured using a non-shrinkage method will be described. The non-shrinking method refers to a method in which when a ceramic material is used as the laminate 11, the dimension in the plane direction of the multilayer wiring board does not substantially change before and after firing the multilayer wiring board.

  First, a method for manufacturing a multilayer ceramic capacitor as the multilayer electronic component 13 will be described, and then a method for manufacturing the multilayer wiring board 10 will be described. Hereinafter, the multilayer electronic component 13 will be described as the multilayer ceramic capacitor 13.

(1) Production of Multilayer Ceramic Capacitor A) After producing a predetermined number of dielectric green sheets 113A used for the multilayer ceramic capacitor 13 as shown in FIG. 4 using a doctor blade method or the like, a screen printing method or the like is used. A conductive paste containing Pd as a main component is printed on the dielectric green sheet 113A to form the internal electrode portion 113C. At this time, as shown in the figure, a conductive paste is printed over the entire width from one end of the dielectric green sheet 113A to the vicinity of the other end, and the internal electrode is made of Ni, Cu or the like with substantially no side margin. A portion 113C is formed. A predetermined number of dielectric green sheets 113A having internal electrode portions 113C are produced.

  B) Next, after sequentially stacking the dielectric green sheets 113A so that the margins of the internal electrode portions 113C are staggered, the dielectric green sheets 113A without the internal electrode portions 113C are stacked on the uppermost layer, and these are then transferred to a predetermined A green laminate is manufactured by pressure bonding.

  C) A non-fired laminated body is fired at a predetermined temperature to obtain a laminated body 13B (see FIG. 2A) that becomes an element body of the multilayer ceramic capacitor. A conductive paste mainly composed of Ag, for example, is applied to both end faces of the element body as external terminal electrodes 13D and baked by a postfire to obtain a multilayer ceramic capacitor 13.

(2) Preparation of multilayer wiring board For example, a predetermined number of dielectric green sheets are used by using a slurry containing a low-temperature sintered ceramic material (a ceramic material containing Al ₂ O ₃ as a filler and borosilicate glass as a sintering aid). Make it. Further, as shown in FIGS. 5A and 5B, via holes are formed in a predetermined pattern in the dielectric green sheet 111A for mounting the multilayer electronic component 13 thereon. These via holes are preferably formed as circular through-holes that are slightly smaller than the width dimension of the multilayer electronic component 13 and have a larger diameter than via-hole conductors formed in other dielectric green sheets. These via holes are filled with, for example, a conductive paste mainly composed of Ag or Cu to form the via hole conductor portion 112B. Further, the same type of conductive paste is applied in a predetermined pattern on the dielectric green sheet 111A using a screen printing method to form a surface electrode portion 114 (see FIG. 5C). A dielectric green sheet 111A in which the via hole conductor portion 112B is appropriately connected is prepared. A dielectric green sheet 111A having other in-plane conductors 112A and / or via-hole conductors 112B is also produced in the same manner.

  Next, an organic adhesive layer (not shown) is applied to the upper surface of the dielectric green sheet 111A on which the multilayer electronic component 13 is disposed by applying or spraying an organic adhesive onto the in-plane conductor portion 112A using a spray or the like. 5), the external terminal electrodes 13D and 13D of the multilayer electronic component 13 are aligned with the via-hole conductor portion 112B of the dielectric green sheet 111A, as shown in FIG. 13 is mounted on the dielectric green sheet 111A, and the external terminal electrode 13D of the multilayer electronic component 13 is bonded and fixed onto the via-hole conductor portion 112B via the organic adhesive layer. In addition, as an organic adhesive agent, the mixture etc. which added the synthetic rubber, the synthetic resin, and the plasticizer can be used. The thickness of the organic adhesive layer is preferably 3 μm or less in the case of coating and 1 μm or less in the case of spraying.

Thereafter, as shown in FIG. 5C, the dielectric green sheet 111A having the in-plane conductor portion 112A and / or the via-hole conductor portion 112B and the dielectric green sheet 111A on which the multilayer electronic component 13 is mounted are predetermined. The dielectric green sheet 111 </ b> A having the uppermost surface electrode portion 114 is laminated in order on the constraining layer 116, and the unfired laminate 111 is formed on the constraining layer 116. Further, a constraining layer 116 is laminated on the upper surface of the unfired laminated body 111, and the unfired laminated body 111 is pressure-bonded at a predetermined temperature and pressure via the upper and lower constraining layers 116. A crimped body 110 shown in FIG. As the constraining layer 116, a paste that contains a hardly sinterable ceramic powder that does not sinter at the sintering temperature of the unfired laminated body 111, for example, Al ₂ O ₃ as a main component and an organic binder as a subcomponent, is shown in FIG. As shown, a sheet is used.

  When the multilayer electronic component 13 is accurately arranged at a predetermined position of the via-hole conductor portion 112B of the dielectric green sheet 111A, as shown in FIG. When the multilayer electronic component 13 sinks into the dielectric green sheet 111A, the inner halves of the upper end surfaces of the left and right via-hole conductor portions 112B and 112B are evenly compressed and deformed via the left and right external electrode terminals 13D and 13D. Thus, the stepped portions 112C and 112C are formed and connected to the left and right via-hole conductor portions 112B and 112B. Accordingly, the left and right external terminal electrodes 13A and 13A are connected to the stepped portions 112C and 112C on two surfaces.

  After the pressure-bonded body 110 is manufactured as described above and the multilayer electronic component 13 is built in, the pressure-bonded body 110 shown in FIG. 6A is fired at a predetermined firing temperature in, for example, an air atmosphere. A multilayer wiring board 10 shown in FIG. When the external terminal electrode 13D and the via-hole conductor 112B of the built-in multilayer electronic component 13 are sintered, the respective metal particles grow and are integrated and connected. The firing temperature is preferably a temperature at which the low-temperature sintered ceramic material is sintered, for example, in the range of 800 to 1050 ° C. If the firing temperature is less than 800 ° C., the ceramic component of the unfired laminate 111 may not be sufficiently sintered, and if it exceeds 1050 ° C., the metal particles of the wiring pattern 12 melt and diffuse into the unfired laminate 111. There is a risk of doing.

  After firing, the upper and lower constraining layers 116 can be removed by blasting or ultrasonic cleaning to obtain the multilayer wiring board 10. Further, as shown in FIG. 6C, a final product can be obtained by mounting a predetermined surface mounting component 20 on the surface electrode 14 of the multilayer wiring board 10 by a technique such as soldering.

  As described above, according to the present embodiment, the multilayer electronic component 13 has no side margin portions on both side edges of the internal electrode 13C, and the upper and lower margin portions are small or small. And low profile can be realized. Therefore, even if the multilayer electronic component 13 is built in between the plurality of dielectric ceramic layers 11A of the multilayer wiring board 10, the unevenness on both the upper and lower surfaces of the multilayer wiring board 10 can be remarkably suppressed as compared with the conventional case. The multilayer wiring board 10 which is almost flat and excellent in surface mountability of the surface mount component 20 can be obtained. Further, since the non-connection surface of the multilayer electronic component 13 is in close contact with the dielectric ceramic layer 11A of the multilayer wiring board 10, the dielectric ceramic layer 11A functions as a margin portion of the internal electrode 13C, and the dielectric The delamination between the ceramic layer 13A and the internal electrode 13C can be prevented, and the reliability of the multilayer electronic component 13 in the humidity can be ensured.

  Further, according to the present embodiment, when the multilayer electronic component 13 is configured as a component with a built-in capacitor having a capacitor pattern formed over a plurality of layers as the internal electrode 13C, one layer of the internal electrode 13C is hit. The area can be expanded and the number of stacked layers can be increased, and a much larger capacity can be obtained as compared with the conventional one. In addition, when the multilayer electronic component 13 is configured as an inductor built-in electronic component having a coil pattern as the internal electrode 13C, the number of turns of the internal electrode 13C increases and the number of stacked internal electrodes 13C increases. A much larger inductance can be obtained as compared with the above.

  According to the present embodiment, the multilayer wiring board 10 includes the via-hole conductor 12B, and the external terminal electrode 13D of the multilayer electronic component 13 is connected to the wiring pattern 12 through the via-hole conductor 12B. Since the step portion 12C is formed in the via hole conductor 12B, the via hole conductor 12B is securely connected to the external terminal electrode 13D without disconnection, and the connection reliability between the multilayer electronic component 13 and the wiring pattern 12 is remarkably increased. Can be increased. The multilayer electronic component 13 is a sintered multilayer ceramic electronic component having a multilayer body 13B formed by laminating a plurality of dielectric ceramic layers 13A, and the multilayer wiring board 10 includes a plurality of dielectric ceramic components. A low-temperature sintered ceramic layer which is a ceramic multilayer substrate having a multilayer body 11 formed by laminating body ceramic layers 11A as a base, and the dielectric ceramic layer 11A is fired at a temperature lower than the temperature at which the multilayer electronic component 13 is fired. Therefore, even if the multilayer electronic component 13 is built in the multilayer wiring board 10 and fired together, mutual diffusion of the respective material components between the dielectric ceramic layer 11A and the multilayer electronic component 13 is prevented. The multilayer electronic component 13 can be incorporated in the multilayer wiring board 10 without impairing the initial electrical characteristics of the multilayer electronic component 13.

Second Embodiment A multilayer wiring board 10A of the present embodiment is configured in the same manner as in the first embodiment except that the connection pattern between the wiring pattern inside and the multilayer electronic component is different. The multilayer wiring board of this embodiment can also be produced in the same manner as in the first embodiment. Therefore, in the following, with reference to FIGS. 7A to 7C, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and only the structural features of this embodiment will be described. .

  As shown in FIG. 7A, the multilayer wiring board 10 </ b> A of the present embodiment uses a multilayer body 11 in which a plurality of dielectric ceramic layers 11 </ b> A are stacked as a base body, and a multilayer electronic component 13 in the multilayer body 11. Is built-in. In this embodiment, as shown in FIGS. 7A to 7C, the multilayer electronic component 13 is disposed at the interface between the upper and lower dielectric ceramic layers 11A and 11A, and the external terminal electrode 13D is connected to the connection conductor. 15 is connected to the in-plane conductor 12A provided at the interface between the upper and lower dielectric ceramic layers 11A.

  The connection conductor 15 is formed by the first and second connection conductors 15A and 15B as shown in FIGS. 7B and 7C. As shown in the figure, the first connecting conductor 15A has a lower dielectric ceramic layer from the in-plane conductor 12A provided at the interface between the upper and lower dielectric ceramic layers 11A, 11A on which the multilayer electronic component 13 is disposed. 11A and the end surface of the external terminal electrode 13D extend downward along the interface, reach the lower surface of the external terminal electrode 13D, and the cross-sectional shape of the side surface is formed in an L shape. As shown in the figure, the second connecting conductor 15B is formed from the in-plane conductor 12A provided at the interface between the upper and lower dielectric ceramic layers 11A, 11A on which the multilayer electronic component 13 is disposed, and the upper dielectric ceramic layer 11A. And the end surface of the external terminal electrode 13D extends upward, reaches the upper surface of the external terminal electrode 13D, and the cross-sectional shape of the side surface is formed in an inverted L shape. The widths of the first and second connection conductors 15 </ b> A and 15 </ b> B are preferably formed to have dimensions corresponding to at least the width of the multilayer electronic component 13.

  Accordingly, the first and second connection conductors 15A and 15B continuously cover the upper surface end, the end surface, and the lower surface end of the external terminal electrode 13D as shown in FIG. 7C, and the external terminal electrode 13D. Is integrally formed as a connection conductor 15 having a C-shape (hereinafter simply referred to as “C-shape”) having an angular cross section so that the cross section is grasped from both upper and lower surfaces, and is electrically connected to the three surfaces of the external terminal electrode 13D. It is connected to the. Further, since the first and second connection conductors 15A and 15B are formed wider than the line width of the in-plane conductor 12A, there is a positional deviation in the width direction of the in-plane conductor 12A from the in-plane conductor 12A. Even in this case, the in-plane conductor 12A is securely connected, and the in-plane conductor 12A and the external terminal electrode 13D can be reliably connected.

  In the case of producing the multilayer wiring board 10A of the present embodiment, it can be first produced by a non-shrinkage method as in the embodiment. That is, in this embodiment, as shown in FIGS. 8A and 8B, before the multilayer electronic component 13 is mounted on the dielectric green sheet 111A, the first and second dielectric green sheets 111A and 111′A are First, the multilayer wiring board 10A is manufactured in the same manner as the embodiment except that the portions to be the second connection conductors 15A and 15B are manufactured. In other words, on the dielectric green sheet 111A on which the multilayer electronic component 13 is arranged, the first connecting conductor portion 115A is simultaneously formed by the screen printing method when the in-plane conductor portion 112A is formed as shown in FIG. On the other hand, the second connection conductor 115B that forms a pair with the first connection conductor 115A is formed by screen printing on the lower surface of the green sheet 111′A laminated thereon. The second connecting conductor portion 115B may include an in-plane conductor portion 112A. Further, an in-plane conductor portion 112A and a via conductor portion 112B are formed on the dielectric green sheet 111A that does not incorporate the multilayer electronic component 13.

  Next, as shown in FIG. 8A, the multilayer electronic component 13 is bonded and fixed onto the first connecting conductor portion 115A via the organic adhesive layer, and then the dielectric green sheet 111A is attached to the dielectric green sheet 111A. As shown in FIG. 8 (a), the dielectric green sheet 111′A in which the in-plane conductor 112A and the second connection conductor 115B are integrally formed is aligned, and temporarily crimped with a predetermined pressure. As shown in FIG. 4B, the multilayer electronic component 13 is built in the interface between the upper and lower dielectric green sheets 111A and 111′A. Thereafter, the multilayer wiring board 10A is manufactured in the same manner as in the first embodiment.

  According to the present embodiment, the multilayer wiring board 10A includes, as the wiring pattern 12, the first connection conductor 15A extending above the upper and lower dielectric ceramic layers 11A and 11A and the opposite side (downward) from the first connection conductor 15A. And the external terminal electrode 13D of the multilayer electronic component 13 is connected to the connection conductor 15 formed in a substantially C shape by the first connection conductor 15A and the second connection conductor 15B. In addition, it is possible to reliably prevent disconnection between the in-plane conductor 12A and the external terminal electrode 13D due to positional deviation when the dielectric green sheets are laminated during the production of the multilayer wiring board 10A and shrinkage during firing, and the multilayer electronic component The reliability of the connection structure between the wiring pattern 13 of the multilayer wiring board 11 and the wiring pattern 13 can be increased. Also, in this embodiment, the same multilayer electronic component 13 as in the first embodiment is incorporated, so that the same effects as in the first embodiment are obtained in addition to the effects that are unique to this embodiment. Can be expected.

Third Embodiment Since the multilayer wiring board of the present embodiment is configured in the same manner as the second embodiment except that it has a structure that prevents adhesion between the dielectric ceramic layer and the multilayer electronic component, With reference to FIGS. 9 and 10, the same or corresponding parts as those of the second embodiment are denoted by the same reference numerals, and only the structural features of this embodiment will be described.

  In this embodiment, as shown in FIG. 9, the multilayer electronic component 13 is disposed at the interface between the upper and lower dielectric ceramic layers 11A and 11A, and its external terminal electrode 13D is formed at the interface between the upper and lower ceramic layers 11A and 11A. Connected to the in-plane conductor 12A. The in-plane conductor 12A and the external terminal electrode 13D are connected through the first and second connection conductors 15A and 15B of the connection conductor 15 as in the second embodiment. A space V is formed between the multilayer electronic component 13 other than the external terminal electrode 13D, that is, between the ceramic body portion and the dielectric ceramic layer 11A, and the ceramic body portion is separated from the dielectric ceramic layer 11A. Yes. This void V prevents damage such as cracks in the multilayer electronic component 13 due to the difference between the thermal expansion coefficient of the multilayer electronic component 13 and the thermal expansion coefficient of the dielectric ceramic layer 11A during firing. And has a function of preventing mutual diffusion of material components between the ceramic body portion and the dielectric ceramic layer 11A.

  In order to provide the gap V, when the multilayer electronic component 13 is built in between the dielectric ceramic layers 11A and 11A, the entire surface of the ceramic body portion other than the external terminal electrode portion 13D of the multilayer electronic component 13 is provided. A resin paste made of a thermally decomposable resin is applied as an adhesion preventing material to form a paste layer having a thickness of 1 to 30 μm, for example. Next, when the multilayer electronic component 13 is disposed between the upper and lower dielectric green sheets as in the second embodiment and fired by a non-shrinking method to produce a multilayer wiring board, the thermally decomposable resin is thermally decomposed. Alternatively, it disappears due to combustion, and a void V is formed around the ceramic body portion of the multilayer electronic component 13 as shown in FIG. As the combustible resin, for example, a butyral resin can be used, and as the decomposable resin, for example, an acrylic resin can be used. In addition, although it is preferable that the adhesion preventing material is formed on the entire peripheral surface of the ceramic body, it may be formed on at least a part thereof. In particular, it is preferably formed on the upper and lower surfaces to which a large pressure is applied. The resin paste may contain a low-temperature sintered ceramic material to such an extent that the formation of the voids V is not hindered. In this case, the portion provided with the resin paste containing the low-temperature sintered ceramic material is in a more porous state than the dielectric ceramic layer 11A.

  According to the present embodiment, a gap V is formed between the ceramic body portion of the multilayer electronic component 13 and the dielectric green sheet, and between the ceramic body portion of the multilayer electronic component 13 and the dielectric ceramic layer 11A. There is no mutual diffusion of the material components, the characteristics of the multilayer electronic component 13 are not deteriorated, and the multilayer electronic component 13 contracts via the in-plane conductor 12A when the temperature is lowered after firing. No excessive pulling force acts on the laminated electronic component 13, and the laminated electronic component 13 is not cracked and the laminated electronic component 13 is not damaged.

  As the adhesion preventive material, a multilayer electronic component similar to the case shown in FIG. 9 is used by using a powder paste containing a hardly sinterable powder as a main component and an organic binder as a subcomponent instead of a thermally decomposable resin. When applied to the ceramic body portion 13, the ceramic powder layer C remains around the ceramic body portion of the multilayer electronic component 13 as shown in FIG. 10 after firing. The ceramic powder layer C is preferably a ceramic material that does not sinter at the firing temperature of the dielectric ceramic layer 11A. As such a ceramic powder material, the aforementioned non-sinterable ceramic powder or the like is preferably used. Also in this case, the multilayer electronic component 13 can contract along the ceramic powder layer C without being constrained by the dielectric ceramic layer 11A when contracting from the expanded state when the temperature is lowered after firing, As a result, the multilayer electronic component 13 is not cracked and the multilayer electronic component 13 is not damaged.

  Specific examples will be described below.

Example 1
In this embodiment, a multilayer ceramic capacitor is manufactured as the multilayer electronic component shown in FIG. 2, a multilayer wiring board in which the multilayer ceramic capacitor is embedded is manufactured, the unevenness on the surface of the multilayer wiring board is measured, and the built-in ceramic capacitor is embedded. The insulation resistance of the laminated ceramic capacitor was measured to determine whether the characteristics were degraded.

  After preparing a predetermined number of dielectric green sheets used for multilayer ceramic capacitors using a doctor blade method, etc., a conductive paste containing, for example, Pd as a main component is printed on the dielectric green sheets using a screen printing method or the like. An internal electrode portion having no side margin was formed on the dielectric green sheet.

  Next, the dielectric green sheets are sequentially laminated so that the margins on the connection surface side of the internal electrode portions are staggered, and then the dielectric green sheets without the internal electrode portions are laminated on the uppermost layer, and then these are bonded at a predetermined pressure. A green laminate is produced by pressure bonding.

  The unsintered laminate was cut to a predetermined size and then fired at a predetermined temperature to obtain a laminate that was an element body of the multilayer ceramic capacitor. For example, a conductive paste mainly composed of Ag as an external terminal electrode was applied to both end faces of this element body and baked to obtain a multilayer ceramic capacitor.

  When the size of a conventional multilayer ceramic capacitor is 0.6 mm × 0.3 mm × 0.3 mm and the capacitance is 100 pF, the size of the internal electrode is 0.55 mm × 0.2 mm. The internal electrode size was 0.55 mm × 0.3 mm, and the length and width of the multilayer ceramic capacitor were the same. Thus, in this embodiment, the width of the internal electrode can be made 0.1 mm larger than that of the conventional one, and the number of stacked internal electrodes can be reduced by the increase in area. In this embodiment, the number of stacked layers is 2 / 3. Also, the upper and lower margins were reduced by 0.05 mm to 0.01 mm. Due to the decrease in the number of layers, the thickness between the internal electrodes became 0.13 mm, the thickness of the upper and lower margins became 0.02 mm, and the total thickness became 0.15 mm, which was ½ of the conventional thickness.

Next, a multilayer wiring board with a built-in multilayer ceramic capacitor was produced. A plurality of dielectric green sheets were produced using a low-temperature sintered ceramic material (Al ₂ O ₃ as a filler and borosilicate glass as a sintering aid) as a material for the dielectric ceramic layer. Via holes were formed in a predetermined dielectric green sheet, and via hole conductor portions and in-plane conductor portions were formed in the via holes using a conductive paste mainly composed of Ag. And after apply | coating the organic type adhesive agent by the spray on the dielectric material green sheet, the multilayer ceramic capacitor was mounted according to the in-plane conductor using the mounter, and the multilayer ceramic capacitor was fixed on the dielectric material green sheet. In the dielectric green sheet, the thickness of the fired dielectric ceramic layer was set to 210 mm □ with a thickness of 50 μm.

In this example, ten dielectric green sheets were laminated to form a laminate. At this time, all the multilayer ceramic capacitors are located in a layer 250 μm below the substrate surface, and the external terminal electrodes are arranged in the multilayer body so as to be connected to the terminal electrodes on the substrate surface via in-plane conductors and via-hole conductors In addition, the characteristics of the multilayer ceramic capacitor can be measured through the terminal electrode. Next, sheets made of Al ₂ O ₃ were laminated as constraining layers on the upper and lower surfaces of the unfired laminate, and this was temporarily pressure-bonded at a predetermined pressure. The pressure at this time is preferably 10 MPa or more. When this pressure is less than 10 MPa, the pressure bonding between the upper and lower dielectric green sheets is insufficient, and delamination may occur.

  Furthermore, the laminated body after provisional pressure bonding was subjected to main pressure bonding at a predetermined pressure to produce a pressure bonded body. This pressure is preferably 208 MPa or more and 250 MPa or less. If the pressure is less than 20 MPa, the pressure bonding is insufficient, and there is a risk of delamination during firing. If the pressure exceeds 250 MPa, the multilayer ceramic capacitor may be damaged or the wiring pattern may be disconnected. Next, this pressure-bonded body was fired at 870 ° C. in an air atmosphere, and then the unfired constraining layer was removed to obtain a multilayer wiring board having a thickness of 0.5 mm.

  Next, the unevenness on the surface of the multilayer wiring board was measured, and a reliability test (75 ° C., 95% relative humidity, 25 V DC voltage applied) was performed. Further, as Comparative Example 1, a multilayer wiring board in which a multilayer ceramic capacitor having a size of 0.6 mm × 0.3 mm was incorporated under the same conditions as in this example was produced. And about the multilayer wiring board of the comparative example 1, while measuring the unevenness | corrugation of the board | substrate surface, the reliability test was done on the same conditions as a present Example. Moreover, the reliability test was done on the same conditions as a present Example, using the multilayer ceramic capacitor produced by the present Example as it is as the comparative example 2. These measurement results are shown in Tables 1 and 2. In addition, the unevenness | corrugation of the board | substrate surface was measured just above embedding a multilayer ceramic capacitor.

  According to the results shown in Table 1, since the thickness of the multilayer ceramic capacitor is ½ that of Comparative Example 1, the unevenness is much smaller than that of Comparative Example 1 and is flattened. I found out. Further, according to the results shown in Table 2, the monolithic ceramic capacitor of this example has an insulation resistance that gradually decreases with time, but in this example, it is incorporated in the multilayer wiring board. As a result, it was found that the insulation resistance was stable for a long time and the reliability was high. In addition, in the manufacturing process of the multilayer wiring board of this example, since the internal electrode has no side margin portion, it was found that the influence of printing misalignment, cut misalignment and stack misalignment of the internal electrode can be eliminated, and the workability is excellent. .

Example 2
In this embodiment, the upper and lower margins of the multilayer ceramic capacitor are eliminated, that is, a multilayer ceramic capacitor in which the uppermost internal electrode and the lowermost internal electrode are exposed is manufactured. A multilayer wiring board with built-in was fabricated. As a result, compared with Example 1, it was possible to further reduce the height by 0.02 mm.

  In addition, this invention is not restrict | limited at all to each said embodiment, Unless it is contrary to the meaning of this invention, it is contained in this invention.

  The present invention can be used for a multilayer wiring board having a built-in multilayer electronic component used in an electronic device or the like.

(A)-(c) is a figure which shows one Embodiment of the multilayer wiring board of this invention, respectively, (a) is sectional drawing which shows the whole, (b) expands and shows the principal part of (a). Sectional drawing, (c) is a plan view of (b). (A), (b) is the figure which takes out and shows the multilayer electronic component shown in FIG. 1, respectively, (a) is the perspective view, (b) is a top view which shows the principal part. (A) is a top view which shows the principal part of another type of multilayer electronic component shown in FIG. 1, (b) is a top view which shows the principal part of the conventional product of the multilayer electronic component shown in (a). FIG. 3 is a perspective view showing a process for manufacturing the multilayer electronic component shown in FIG. 2. (A)-(c) is process drawing which shows the principal part of the manufacturing process of the multilayer wiring board shown in FIG. 1, respectively, (a) is sectional drawing which shows a dielectric material green sheet, (b) is shown to (a). Sectional drawing which shows the state which mounts multilayer electronic components on a dielectric green sheet, (c) is sectional drawing which shows the state which laminates | stacks the dielectric green sheet shown in (b), and another dielectric green sheet. (A)-(c) is process drawing following the manufacturing process shown in FIG. 5, respectively, (a) is sectional drawing which shows the crimping | compression-bonding body before baking, (b) is sectional drawing which shows the multilayer wiring board after baking, (C) is sectional drawing which shows the state which mounted the multilayer electronic component on the multilayer wiring board shown to (b). (A)-(c) is a figure which shows other embodiment of the multilayer wiring board of this invention, respectively, (a) is sectional drawing which shows the whole, (b) expands the principal part of (a). Sectional drawing which shows, (c) is principal part sectional drawing which expands and shows (b) further. (A), (b) is process drawing which shows the principal part of the manufacturing process of the multilayer wiring board shown in FIG. 7, respectively, (a) is sectional drawing which shows the state just before incorporating a multilayer type electronic component, (b) FIG. 2 is a cross-sectional view showing a state in which a multilayer electronic component is incorporated. It is sectional drawing which shows the principal part of other embodiment of the multilayer wiring board of this invention. It is sectional drawing which shows the principal part of other embodiment of the multilayer wiring board of this invention. (A), (b) is a figure which shows the multilayer ceramic capacitor which is an example of the conventional multilayer electronic component, respectively, (a) is the sectional drawing, (b) is the ceramic layer and internal electrode which are shown in (a). It is a top view which shows a relationship.

Explanation of symbols

10, 10A, 10B Multilayer wiring board 11 Laminated body (element body)
11A Dielectric ceramic layer (dielectric layer)
12 Wiring Pattern 12A In-plane Conductor 12B Via-hole Conductor 13 Multilayer Electronic Component 13A Dielectric Ceramic Layer (Dielectric Layer)
13B Laminated body (element body)
13C Internal electrode 13D External electrode 15A First connecting conductor 15B Second connecting conductor V Void C Ceramic powder

Claims (11)

A multilayer wiring board with built-in multilayer electronic components,
The multilayer electronic component is
An element body composed of a laminate in which a plurality of dielectric layers are laminated;
An internal electrode interposed between the dielectric layers, an external terminal electrode provided on at least one side surface of the element body so as to be connected to the internal electrode,
Have
The internal electrode is formed so that there is substantially no margin between the other side surfaces of the element body,
The multilayer wiring board is
An element body composed of a laminate in which a plurality of dielectric layers are laminated;
A predetermined wiring pattern provided inside the laminate,
Have
The external terminal electrode of the multilayer electronic component is connected to the wiring pattern of the multilayer wiring board, and the other side surface of the element body of the multilayer electronic component is a dielectric of the multilayer wiring substrate. A multilayer wiring board characterized by facing a layer.   2. The multilayer wiring board according to claim 1, wherein the multilayer electronic component is a component with a built-in capacitor having a capacitor pattern formed over a plurality of layers as the internal electrode.   2. The multi-layer wiring board according to claim 1, wherein the multilayer electronic component is an electronic component with a built-in inductor having a coil pattern as the internal electrode.   The wiring pattern of the multilayer wiring board includes a via-hole conductor, the external terminal electrode of the multilayer electronic component is connected to the via-hole conductor, and a step portion is formed in the via-hole conductor in a connected state. The multilayer wiring board according to any one of claims 1 to 3, wherein the multilayer wiring board is provided. The multilayer wiring board includes, as the wiring pattern, a first connection conductor extending in the stacking direction of the dielectric layers, and a second connection conductor extending on the opposite side of the first connection conductor,
4. The multilayer wiring according to claim 1, wherein the external terminal electrode of the multilayer electronic component is connected to the first connection conductor and the second connection conductor, respectively. 5. substrate.   6. The gap according to claim 1, wherein a gap is interposed between the other side surface of the multilayer electronic component and the dielectric layer of the multilayer wiring board. Multilayer wiring board.   6. The ceramic powder is interposed between the other side surface of the multilayer electronic component and the dielectric layer of the multilayer wiring board. 6. Multilayer wiring board.   The multilayer electronic component according to any one of claims 1 to 7, wherein the multilayer electronic component is a multilayer ceramic electronic component including a multilayer body formed by laminating a plurality of dielectric ceramic layers. Multilayer wiring board.   The multilayer wiring board according to any one of claims 1 to 8, wherein the multilayer wiring board is a ceramic multilayer board having a multilayer body formed by laminating a plurality of dielectric ceramic layers. substrate.   10. The multilayer wiring board according to claim 9, wherein the dielectric ceramic layer is a low temperature sintered ceramic layer. An element body composed of a laminate in which a plurality of dielectric layers are laminated;
An internal electrode interposed between the dielectric layers;
An external terminal electrode provided on at least one side surface of the element body so as to be connected to the internal electrode;
Have
A multilayer electronic component characterized in that there is substantially no margin between the other side surface of the element body and the internal electrode.

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