JP2007095813A - Manufacturing method of laminated capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of cracks and delamination. <P>SOLUTION: A manufacturing method of a laminated capacitor 1 is provided with a first electrode forming process of forming a first electrode pattern 23 on a ceramic green sheet 21; a layer forming process of forming a ceramic green layer 25 on the green sheet 21 and the first electrode pattern 23; a second electrode forming process of forming a second electrode pattern 27 on the ceramic green layer 25 so that pattern 27 does not overlap on the first electrode pattern 23 via the ceramic green layer 25 in a laminating direction, thereby forming a unit laminate 20; a chip forming process of preparing a plurality of unit laminates 20, laminating the unit laminates 20 and cutting them to form a laminate chip body; and a baking process of baking the laminate chip body. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer capacitor.

  Conventionally, a method of forming a multilayer capacitor by laminating ceramic green sheets printed with an electrode pattern is known. On the ceramic green sheet on which the electrode pattern is printed, a step is generated between a portion where the electrode pattern is printed and a portion where the electrode pattern is not printed. When ceramic green sheets having a level difference are laminated to form a multilayer capacitor, the adhesion between the ceramic green sheets decreases and delamination occurs.

In order to solve this problem, the following Patent Document 1 describes a method of manufacturing a multilayer capacitor in which a step is eliminated by printing a ceramic paste on a portion of the ceramic green sheet where an electrode pattern is not printed.
JP 2001-358036 A

  However, the electrode pattern and the ceramic paste may be printed out of alignment on the ceramic green sheet surface. That is, in the method for manufacturing a multilayer capacitor disclosed in Patent Document 1, the ceramic paste may be printed out of a portion where the electrode pattern is not printed. In this case, in addition to not being able to eliminate the step, the ceramic paste adheres on the electrode pattern and further steps are formed. Therefore, the adhesion between the ceramic green sheets may be further reduced and delamination may occur.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a multilayer capacitor capable of suppressing the occurrence of delamination.

  The multilayer capacitor manufacturing method of the present invention includes a first electrode forming step of forming a first electrode pattern on a ceramic green sheet, a layer forming step of forming a ceramic green layer on the ceramic green sheet and on the first electrode pattern, A second electrode forming step of forming a unit laminate by forming a second electrode pattern so as not to overlap the first electrode pattern via the ceramic green layer in the lamination direction on the ceramic green layer, and a plurality of unit laminates A chip forming step of preparing and laminating the plurality of unit laminate bodies to form a laminated chip body, and a firing step of firing the laminated chip body are provided.

  The ceramic green layer is formed on the ceramic green sheet and the first electrode pattern, and the second electrode pattern is formed on the ceramic green layer so as not to overlap the first electrode pattern through the ceramic green layer in the stacking direction. Since the laminated body is formed, a step between the portion where the first electrode pattern is formed and the portion where the first electrode pattern is not formed can be reduced on the ceramic green sheet. Since the unit laminated bodies with reduced steps are laminated, the adhesion between the unit laminated bodies is improved. Since a multilayer capacitor is manufactured by cutting and firing the plurality of stacked unit laminate bodies, the occurrence of delamination can be reduced.

  In the multilayer capacitor manufacturing method of the present invention, it is also preferable that the thickness of the ceramic green layer is smaller than the thickness of the ceramic green sheet. In this way, the thickness in the stacking direction can be reduced.

  In the multilayer capacitor manufacturing method of the present invention, the planar shape of the first electrode pattern and the second electrode pattern is a substantially square shape, and in the first electrode forming step, a plurality of first electrode patterns are formed in a checkered pattern. In the second electrode forming step, a plurality of second electrode patterns are formed in a checkered pattern so as to be positioned between adjacent first electrode patterns, and the first electrode pattern and the second electrode pattern are formed on the ceramic green sheet. In a chip formation step, a plurality of unit laminates are laminated such that the first electrode pattern and the second electrode pattern are alternately shifted in the row direction or the column direction to obtain a green block laminate, It is also preferable to cut the green block laminated body so that the first electrode pattern and the second electrode pattern are exposed as a cross section on the end face of the laminated chip body. Manufacturing in this way can increase the efficiency of the manufacturing process.

  According to the multilayer capacitor manufacturing method of the present invention, the occurrence of delamination can be suppressed.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  The multilayer capacitor according to this embodiment will be described with reference to FIGS. FIG. 1 is a perspective view of the multilayer capacitor 1 according to the present embodiment. FIG. 2 is a cross-sectional view of the multilayer capacitor 1 according to the present embodiment. As shown in FIG. 1, the multilayer capacitor 1 includes a substantially rectangular parallelepiped element 5 and a pair of first terminal electrode 2 and second terminal electrode 4 formed on the element 5.

  The element 5 has a pair of end faces facing the longitudinal direction of the element 5, a pair of side faces facing the stacking direction of the element 5, and a pair of side faces facing the longitudinal direction and the direction perpendicular to the stacking direction. Yes. The first terminal electrode 2 is formed so as to cover the entire surface of one end surface, and further, a part of the first terminal electrode 2 wraps around each side surface. The second terminal electrode 4 is formed so as to cover the entire surface of the other end face, and a part of which wraps around each side face. One of the pair of side surfaces facing the stacking direction of the element 5 is a surface facing the external substrate when the multilayer capacitor 1 is mounted on the external substrate.

  As shown in FIG. 2, the element 5 has a first internal electrode 11, a second internal electrode 13, and a dielectric layer 15. In the present embodiment, the element 5 has two first internal electrodes 11 and second internal electrodes 13. The first internal electrode 11 formed in a substantially square shape is exposed to the end face of the element 5 on which the first terminal electrode 2 is formed, and is mechanically and electrically connected to the first terminal electrode 2. . The second internal electrode 13 formed in a substantially square shape is exposed to the end face of the element 5 on which the second terminal electrode 4 is formed, and is mechanically and electrically connected to the second terminal electrode 4. . The first internal electrodes 11 and the second internal electrodes 13 are alternately stacked via the dielectric layers 15.

  Subsequently, a method for manufacturing the multilayer capacitor 1 according to the present embodiment will be described. FIG. 3 is a flowchart showing a method for manufacturing the multilayer capacitor 1. The manufacturing process of the multilayer capacitor 1 includes a sheet forming process S1, a first electrode forming process S2, a layer forming process S3, a second electrode forming process S4, a chip forming process S5, a firing process S6, and a terminal forming process. And S7. Each step will be described with reference to FIGS.

  FIG. 4 is a diagram illustrating a method for manufacturing the unit multilayer body 20 formed in the manufacturing process of the multilayer capacitor 1. In the sheet forming step S1, as shown in FIG. 4A, a ceramic green sheet 21 is formed on a support (not shown). The ceramic green sheet 21 is a ceramic slurry obtained by adding a binder resin (for example, an organic binder resin), a solvent, a plasticizer, and the like to a dielectric material containing barium titanate as a main component and mixing and dispersing it on a support. After coating, it is dried to form. The thickness of the ceramic green sheet 21 is about 1 to 7 μm.

  After the sheet forming step S1, in the first electrode forming step S2, as shown in FIG. 4B, the first electrode pattern 23 is formed on the ceramic green sheet 21. The first electrode pattern 23 is formed by printing an electrode paste on the ceramic green sheet 21 and drying it. The electrode paste is a paste-like composition obtained by mixing a binder resin, a solvent, or the like with a metal powder such as Ni, Ag, or Pd. The thickness of the first electrode pattern 23 is about 1 to 2 μm.

  After the first electrode forming step S2, a ceramic green layer 25 is formed on the ceramic green sheet 21 and the first electrode pattern 23 in the layer forming step S3 as shown in FIG. The ceramic green layer 25 is formed by applying a ceramic paste and then drying it. The ceramic paste may be the same component as the ceramic slurry or a different component. The thickness of the ceramic green layer 25 is formed thinner than the thickness of the ceramic green sheet 21. The thickness of the ceramic green layer 25 is about 0.1 to 0.5 μm.

  After the layer formation step S3, in the second electrode formation step S4, as shown in FIG. 4D, the second electrode pattern 27 is formed on the ceramic green layer 25 to form the unit laminate 20. The second electrode pattern 27 is formed so as not to overlap the first electrode pattern 23 via the ceramic green layer 25 in the stacking direction perpendicular to the upper surface of the ceramic green sheet 21. The thickness of the second electrode pattern 27 is about 1 to 2 μm.

  The unit laminated body 20 is demonstrated with reference to FIG. FIG. 5 is a top view of the unit laminate body 20. A first electrode pattern 23 indicated by a hidden line in FIG. 5 has a substantially rectangular shape and is formed between the ceramic green sheet 21 and the ceramic green layer 25. In the first electrode formation step S <b> 2, a plurality of first electrode patterns 23 are formed on the ceramic green sheet 21 in a checkered pattern.

  The second electrode pattern 27 is also substantially rectangular and is formed on the ceramic green layer 25. In the second electrode formation step S4, a plurality of second electrode patterns 27 are formed in a checkered pattern so as to be positioned between the adjacent first electrode patterns 23 on the ceramic green layer 25, and the second pattern 27 is formed on the ceramic green sheet 21. The first electrode pattern 23 and the second electrode pattern 27 are arranged in a matrix. In this way, the unit laminate body 20 in which the first electrode pattern 23 and the second electrode pattern 27 are arranged in a matrix is formed.

  Subsequently, a chip formation step S5 is performed after the second electrode formation step S4. In the chip forming step S5, as shown in FIG. 6, a plurality of unit laminated bodies 20 are prepared and laminated to obtain the green block laminated body 30, and then cut to form a laminated chip body. FIG. 6 is a cross-sectional view of the green block laminate 30. In the chip forming step S5, a plurality of unit laminated bodies 20 are laminated so that the first electrode patterns 23 and the second electrode patterns 27 are alternately displaced in the row direction to form the green block laminated body 30. The row direction indicates the row direction of the first electrode pattern 23 and the second electrode pattern 27 arranged in a matrix. The plurality of unit laminate bodies 20 may be laminated while being shifted in the column direction. In this green block laminate 30, a gap surrounded by the ceramic green layer 25, the second electrode pattern 27, and the ceramic green sheet 21 laminated on the second electrode pattern 27 is formed.

  Then, the green block laminated body 30 is cut so that the first electrode pattern 23 and the second electrode pattern 27 are exposed as a cross section on the end face of the laminated chip body. The cut surfaces are two surfaces perpendicular to the stacking direction and orthogonal to each other. One cut plane L is a plane perpendicular to the direction (row direction) shifted when laminating the plurality of unit laminates 20, the central portion of each first electrode pattern 23 and each second electrode pattern 27, and the unit This is a surface passing through between the first electrode pattern 23 and the second electrode pattern 27 adjacent to each other in the stacked body 20. In the cut surface L, the first electrode pattern 23 and the second electrode pattern 27 are exposed. The other cut surface is a surface that passes between the first electrode pattern 23 and the second electrode pattern 27 adjacent to each other in the unit laminate body 20.

  After the chip forming step S5, the laminated chip body is fired in a firing step S6. The laminated chip body is heated to perform drying, binder removal, and firing. When a predetermined temperature is reached during binder removal, the binder contained in the ceramic green sheet 21, the ceramic green layer 25, the first electrode pattern 23, and the second electrode pattern 27 is released as a gas at a stretch. This gas is released through a gap surrounded by the ceramic green layer 25, the second electrode pattern 27, and the ceramic green sheet 21 laminated on the second electrode pattern 27.

  After the firing step S6, a terminal electrode is formed on the outer surface of the multilayer chip body in a terminal formation step S7. The first terminal electrode 2 is formed on one end surface cut by the cut surface L in the multilayer chip body, and the first electrode pattern 23 or the second electrode pattern 27 and the first terminal electrode 2 exposed on the one end surface are formed. Connect electrically. The second terminal electrode 4 is formed on the other end surface cut by the cut surface L in the multilayer chip body, and the first electrode pattern 23 or the second electrode pattern 27 and the second terminal electrode 4 exposed on the other end surface are formed. Connect electrically.

  The first electrode pattern 23 and the second electrode pattern 27 electrically connected to the first terminal electrode 2 correspond to the second internal electrode 13, and the first electrode pattern 23 electrically connected to the second terminal electrode 4. The second electrode pattern 27 corresponds to the second internal electrode 13. The laminated chip body corresponds to the element 5. In this way, the multilayer capacitor 1 is manufactured.

  According to the method for manufacturing the multilayer capacitor 1 of the present embodiment, the ceramic green layer 25 is formed on the ceramic green sheet 21 and the first electrode pattern 23, and the ceramic green layer 25 is formed on the ceramic green layer 25 in the stacking direction. Since the unit electrode stack 20 is formed by forming the second electrode pattern 27 so as not to overlap the first electrode pattern 23, the portion where the first electrode pattern 23 is formed on the ceramic green sheet 21 is not formed. A step difference from the portion can be reduced. Since the green block laminate 30 is formed by laminating the unit laminates 20 with reduced steps, the adhesion between the unit laminates 20 in the green block laminate 30 is improved. Since this green block laminated body 30 is cut and fired to produce the multilayer capacitor 1, the occurrence of delamination can be reduced.

  Further, since the thickness of the ceramic green layer 25 is thinner than the thickness of the ceramic green sheet 21, the thickness in the stacking direction can be reduced.

  In the first electrode forming step S2, a plurality of first electrode patterns 23 are formed in a checkered pattern, and in the second electrode forming step S4, the second electrode patterns 27 are positioned between the adjacent first electrode patterns 23. A plurality of patterns are formed, and the first electrode pattern 23 and the second electrode pattern 27 are arranged in a matrix on the ceramic green sheet 21. In the chip forming step S5, a plurality of unit laminated bodies 20 are laminated so that the first electrode patterns 23 and the second electrode patterns 27 are alternately displaced in the row direction or the column direction to obtain a green block laminated body 30, and the green block Since the laminated body 30 is cut so that the first electrode pattern 23 and the second electrode pattern 27 are exposed as a cross section on the end face of the laminated chip body, the efficiency of the manufacturing process can be increased.

  As a conventional multilayer capacitor manufacturing method, after printing an electrode pattern on a ceramic green sheet, the ceramic paste is printed on the part where the electrode pattern is not formed, and the ceramic paste is printed on the margin of the electrode pattern There is a method of laminating sheets. In the case of this method, the ceramic paste is filled in the gap between the laminated ceramic green sheets and the electrode pattern.

  Thereafter, similarly to the chip formation step S5 and the firing step S6, the laminated ceramic green sheets are cut into a multilayer chip body and fired. In the binder removal step included in this firing step, as described above, the binder contained in the ceramic green sheet and the electrode pattern is discharged as a gas from the multilayer chip body at a predetermined temperature. Therefore, the gap between the multilayer chip bodies manufactured by the above conventional multilayer capacitor manufacturing method is filled with the ceramic paste, so that the gas released from the inside of the multilayer chip body causes cracks and delamination. Cheap.

  The multilayer chip body formed by the method of manufacturing the multilayer capacitor 1 according to this embodiment is surrounded by the ceramic green layer 25, the second electrode pattern 27, and the ceramic green sheet 21 laminated on the second electrode pattern 27. A gap is formed. Therefore, since the gas generated in the binder removal process is released through this gap, the generation of cracks can be suppressed.

  As another conventional method of manufacturing a multilayer capacitor, there is a method of laminating a ceramic green sheet in a state where an electrode pattern is formed on the ceramic green sheet, that is, in a state having a step. Deformation occurs in a laminated chip body formed by laminating and cutting a plurality of ceramic green sheets having steps. When the multilayer chip body is deformed, characteristics of the multilayer capacitor vary, and electrode patterns adjacent in the stacking direction may come into contact with each other. In the method for manufacturing the multilayer capacitor 1 according to the present embodiment, the steps on the unit multilayer body 20 are reduced and laminated as described above, so that the green block multilayer body 30 and the multilayer chip body can be prevented from being deformed.

1 is a perspective view of a multilayer capacitor according to an embodiment. It is sectional drawing of the multilayer capacitor which concerns on this embodiment. It is a flowchart which shows the manufacturing method of the multilayer capacitor which concerns on this embodiment. It is a figure which shows the manufacturing method of the unit laminated body formed in the manufacturing process of the multilayer capacitor concerning this embodiment. It is a top view of the unit multilayer body formed in the manufacturing process of the multilayer capacitor in accordance with this embodiment. It is sectional drawing of the green block laminated body formed in the manufacturing process of the multilayer capacitor concerning this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 2 ... 1st terminal electrode, 4 ... 2nd terminal electrode, 5 ... Element, 11 ... 1st internal electrode, 13 ... 2nd internal electrode, 15 ... Dielectric layer, 20 ... Unit laminated body, 21 ... ceramic green sheet, 23 ... first electrode pattern, 25 ... ceramic green layer, 27 ... second electrode pattern, 30 ... green block laminate.

Claims (3)

A first electrode forming step of forming a first electrode pattern on the ceramic green sheet;
Forming a ceramic green layer on the ceramic green sheet and on the first electrode pattern; and
A second electrode forming step of forming a unit laminate body by forming a second electrode pattern on the ceramic green layer so as not to overlap the first electrode pattern via the ceramic green layer in the stacking direction;
A chip forming step of preparing a plurality of the unit laminated bodies and laminating the plurality of unit laminated bodies and then cutting to form a laminated chip body;
A firing step of firing the laminated chip body;
A method of manufacturing a multilayer capacitor, comprising:   2. The method of manufacturing a multilayer capacitor according to claim 1, wherein the thickness of the ceramic green layer is thinner than the thickness of the ceramic green sheet. The planar shape of the first electrode pattern and the second electrode pattern is a substantially square shape,
In the first electrode forming step, a plurality of the first electrode patterns are formed in a checkered pattern,
In the second electrode forming step, a plurality of the second electrode patterns are formed in a checkered pattern so as to be positioned between the adjacent first electrode patterns, and the first electrode pattern and the second electrode are formed on the ceramic green sheet. The electrode pattern is arranged in a matrix,
In the chip forming step, the plurality of unit laminated bodies are laminated so that the first electrode patterns and the second electrode patterns are alternately shifted in a row direction or a column direction to obtain a green block laminated body, and the green block 3. The method for manufacturing a multilayer capacitor according to claim 1, wherein the multilayer body is cut so that the first electrode pattern and the second electrode pattern are exposed as a cross section on an end surface of the multilayer chip body. 4.

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